Instruction Set Pin Functions

FP
d

d
s

s
Data Transfer Operations Arithmetic Operations

rio

rio
pe C

pe C
te

te

SP
Q
S

S
by

by

M
O

52
51
50
49
48
47
46
45
44
43
42
41
40
MOV A,Rn 1 1 ADD A,Rn 1 1 2 1 P1.1 / AIN2
MOV A,@Ri
MOV A,direct
1
2
2
2
ADD
ADD
A,@Ri
A,direct
add source to A
1
2
2
2
3 2 P1.2 / AIN3 / REFIN2+ ADuC845/ADuC847/ADuC848

56
55
54
53
52
51
50
49
48
47
46
45
44
43
4 3 P1.3 / AIN4 / REFIN2- pin 1 identifier

MicroConverter Quick Reference Guide

1 39
MOV A,#data 2 2 ADD A,#data 2 2 1 42 2 38
®
pin 1 identifier
MOV Rn,A 1 1 ADDC A,Rn 1 1 5 4 AVDD 2 41
3 37
3 40

MOV Rn,direct 2 2 ADDC A,@Ri

add with carry
1 2 - 5 AGND 4
5
6
ADuC845
39
38
37
4
5 ADuC845 36
35
MOV Rn,#data 2 2 ADDC A,direct 2 2 6 6 AGND 7
8
56-pin CSP 36
35
6
7
52-pin MQFP 34
33
MOV direct,A 2 2 ADDC A,#data 2 2 TOP VIEW
move 7 7 REFIN- 9
10
(not to scale)
34
33 8 TOP VIEW 32
MOV direct,Rn 2 2 SUBB A,Rn 1 1 11 32 9 31
MOV direct,@Ri 2 2 SUBB A,@Ri subtract from A 1 2
8 8 REFIN+ 12
13
31
30
10 (not to scale) 30 FUNCTIONAL
11 29
MOV direct,direct 3 3 SUBB A,direct with borrow 2 2
9 9 P1.4 / AIN5 14 29
12 28 BLOCK

P1.1 (AIN2 / REFIN2+)

P1.2 (AIN3 / REFIN2-)
10 10 P1.5 / AIN6 13 27 DIAGRAM

15
16
17
18
19
20
21
22
23
24
25
26
27
28
MOV direct,#data 3 3 SUBB A,#data 2 2

P1.6 (AIN7 / IEXC1)

P1.7 (AIN8 / IEXC2)
11 11 P1.6 / AIN7 / IEXC1

P2.2 (A10 / A18)

P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
P2.6 (A14 / A22)
P2.7 (A15 / A23)
MOV @Ri,A 1 2 INC A 1 1

P2.0 (A8 / A16)

P2.1 (A9 / A17)
MOV @Ri,direct 2 2 INC Rn 1 1 12 12 P1.7 / AIN8 / IEXC2

P1.0 (AIN1)

P1.3 (AIN4)
P1.4 (AIN5)
P1.5 (AIN6)

P3.2 (INT0)
P3.3 (INT1)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

P3.0 (RxD)
P3.1 (TxD)

P3.6 (WR)
P3.7 (RD)
14
15
16
17
18
19
20
21
22
23
24
25
26

P3.4 (T0)
P3.5 (T1)
MOV @Ri,#data 2 2 INC @Ri increment 1 2 13 13 AINCOM / DAC
MOV DPTR,#data16 3 3 INC direct 2 2 14 14 DAC
MOVC A,@A+DPTR move from 1 4 INC DPTR * 1 3

FP

FP

FP

46
47
48
49
52
53
54
55

56

10

12

30
31
32
33
39
40
41
42

18
19
20
21
24
25
26
27
11
MOVC A,@A+PC code memory 1 4 DEC A 1 1

1
2
3
9
SP

SP

SP
Q

Q
M

M
C

C
MOVX A,@Ri 1 4 DEC Rn 1 1 AIN1 56
decrement - 15 AIN9 (CSP package only) 27 29 SDATA (I2C) 40 43 EA
MOVX A,@DPTR move to/from 1 4 DEC @Ri 1 2 AIN2 1 (primary ADC) 16-bit on ADuC848
MOVX @Ri,A data memory 1 4 DEC direct 2 2 - 16 AIN10 (CSP package only) 28 30 P2.0 / SCLOCK (SPI) 41 44 PSEN AIN3 2
MOVX @DPTR,A 1 4 MUL AB multiply A by B 1 9 15 17 RESET 29 31 P2.1 / MOSI (SPI) 42 45 ALE AIN4 3 24-bit
ADC
control ADuC845/7/8
BUF PGA
AIN5 9 SD ADC &
PUSH direct push onto stack 2 2 DIV AB divide A by B 1 9 16 18 P3.0 / RxD 30 32 P2.2 / MISO (SPI) 43 46 P0.0 / AD0 calibration
AIN6 10
POP direct pop from stack 2 2 DA A decimal adjust 1 2 17 19 P3.1 / TxD 31 33 P2.3 / SS / T2 44 47 P0.1 / AD1 AIN7 11 AIN
MUX (auxillary ADC) ADuC845 only DAC
XCH A,Rn 1 1 * INC DPTR increments the 24bit value DPP/DPH/DPL AIN8 12 control DAC BUF 14 DAC
18 20 P3.2 / INT0 32 34 XTAL1 (in) 45 48 P0.2 / AD2
XCH A,@Ri exchange bytes 1 2 AIN9 15 ADC
19 21 P3.3 / INT1 33 35 XTAL2 (out) 46 49 P0.3 / AD3 24-bit control

s
AIN10 16

d
XCH A,direct 2 2 Logical Operations s SD ADC

rio
&

pe C
te

S
by

20 22 DVDD 34 36 DVDD 47 50 DGND AINCOM 13 calibration

XCHD A,@Ri exchg low digits 1 2 O PWM
40 PWM0
ANL A,Rn 1 1 41 PWM1
21 23 DGND 35 37 DGND 48 51 DVDD
ANL A,@Ri 1 2 4K x 8
s

2K x 8
d
s

Boolean Variable Manipulation 22 24 P3.4 / T0 - 38 DGND 49 52 P0.4 / AD4

rio
pe C

data
te

ANL A,direct 2 2 TEMP bandgap user “XRAM”

S
by

logical AND sensor reference Flash/EE 24 T0

CLR C 1 1 ANL A,#data 2 2 23 25 P3.5 / T1 36 39 P2.4 / T2EX 50 53 P0.5 / AD5 256 x 8
clear bit to zero (65,536 counts 62K x 8 1-clock user RAM
16-bit 25 T1
CLR bit 2 2 ANL direct,A 2 2 24 26 P3.6 / WR 37 40 P2.5 / PWM0 51 54 P0.6 / AD6 per oC) counter
code 8052 timers 33 T2
SETB C 1 1 ANL direct,#data 3 3 25 27 P3.7 / RD 38 41 P2.6 / PWM1 52 55 P0.7 / AD7 REFIN+ 8
VREF
Flash/EE watchdog
set bit to one MCU 39 T2EX
REFIN- 7 timer
SETB bit 2 2 ORL A,Rn 1 1 26 28 SCLK (I C)2
39 42 P2.7 / PWMCLK 1 56 P1.0 / AIN1
detect core
REFIN2+ 2 & mux baudrate timer
CPL C 1 1 ORL A,@Ri 1 2 power supply
complement bit REFIN2- 3 downloader monitor time
20 INT0
CPL bit 2 2 ORL A,direct 2 2 debugger interval
logical OR counter 21 INT1
ANL C,bit AND bit with C 2 2 ORL A,#data 2 2 200µA / 400µA
Code Memory Space Options

single-pin
ANL C,/bit AND (NOTbit) with C 2 2 ORL direct,A 2 2 asynchronous

emulator
IEXC1 11
POR serial port SPI I2 C OSC &
ORL C,bit OR bit with C 2 2 ORL direct,#data 3 3 IEXC2 12 (UART) PLL
ORL C,/bit OR (NOTbit) with C 2 2 XRL A,Rn 1 1 62 32 8
MOV C,bit 2 2 XRL A,@Ri 1 2 FFFFh FFFFh FFFFh

22
36
51
23
37
38
50

18
19

30
31
32
33

28
29

34
35
17

45
44
43
move bit to bit

4
5
6
MOV bit,C 2 2 XRL A,direct 2 2 (NOP instructions)
logical XOR F800h (NOP instructions)

SS
AVDD

RxD
TxD

SCLOCK
MOSI
MISO

SCLK
SDATA

XTAL1
XTAL2
RESET

ALE
PSEN
EA
XRL A,#data 2 2 F7FFh

AGND

DVDD

DGND
ds

XRL direct,A 2 2 (NOP instructions)

s

Program Branching
rio
pe C
te

S
by

8000h
O

XRL direct,#data 3 3
ACALL addr11 2 3 7FFFh
call subroutine CLR A clear A to zero 1 1 internal
LCALL addr16 3 4 code space * pin numbers refer to CSP package
CPL A complement A 1 1 internal
RET return from sub. 1 4 2000h
RL A rotate A left 1 1 code space
RETI return from int. 1 4 62kB 1FFFh internal
RLC A ...through C 1 1 code space
AJMP addr11 2 3 Flash/EE
RR A rotate A right 1 1 32kB
LJMP addr16 3 4 Flash/EE 8kB
jump RRC A ...through C 1 1
SJMP rel 2 3 Flash/EE A Precision Analog Flash MCU
SWAP A swap nibbles 1 1 0000h 0000h 0000h
JMP @A+DPTR 1 3
JC rel jump if C set 2 3 The ADuC845/ADuC847/ADuC848 is:
JNC rel jmp if C not set 2 3 Legend ADC:
JB bit,rel jump if bit set 3 4
Rn register addressing using R0-R7 Interrupt Vector Addresses 24-bit* primary ADC, differential w/ programmable gain
JNB bit,rel jmp if bit not set 3 4 24-bit auxiliary ADC, single-ended w/ fixed gain (ADuC845 only)
@Ri indirect addressing using R0 or R1 Vector Relative
JBC bit,rel jmp&clear if set 3 4 Interrupt Bit Interrupt Name 10-channel input mux (*ADC is 16bit on ADuC848)
JZ rel jump if A = 0 2 3 direct 8-bit internal address (00h-FFh) Address Priority
JNZ rel jump if A not 0 2 3 #data 8-bit constant included in instruction
DAC:
PSMCON.5 Power Supply Monitor Interrupt 43h 1 12-bit, 15µs, voltage output
CJNE A,direct,rel 3 4 #data16 16-bit constant included in instruction
compare and WDS WatchDog Timer Interrupt 5Bh 2 <1LSB DNL
CJNE A,#data,rel 3 4 bit 8-bit direct address of bit
jump if not
CJNE Rn,#data,rel 3 4 IE0 External Interrupt 0 03h 3 Flash/EEPROM:
equal rel signed 8-bit offset up to 62kB Flash/EE program memory
CJNE @Ri,#data,rel 3 4
addr11 11-bit address in current 2K page RDY0/RDY1 End of ADC Conversion Interrupt 33h 4 4kB Flash/EE data memory
DJNZ Rn,rel decrement and 2 3
DJNZ direct, rel jump if not zero 3 4 addr16 16-bit address TF0 Timer0 Overflow Interrupt 0Bh 5 Microcontroller:
NOP no operation 1 1 x any of: Rn, @Ri, direct, #data IE1 External Interrupt 1 13h 6 “single-cycle” 8052, up to 12.6MIPS
32 I/O lines, programmable PLL clock
TF1 Timer1 Overflow Interrupt 1Bh 7
(98.3kHz to 12.6MHz from 32kHz crystal)
Instructions That Affect Flags ISPI/I2CI SPI/I2C Interrupt 3Bh 8
Embedded Tools Support:
ADD A,x C = carry out of bit 7 DA A C = C or (x>100) RI/TI UART Interrupt 23h 9 on-chip download/debug & single-pin emulation functions
AC = carry out of bit 3 RRC A C = ACC.7 TF2/EXF2 Timer2 Interrupt 2Bh 10
OV = carry out of bit 6, but not 7
RLC A C = ACC.0
Other on-chip features:
ADDC A,x C = carry out of bit 7 TIMECON.2 Time Interval Counter Interrupt 53h 11 temperature sensor, power supply monitor, watchdog timer,
AC = carry out of bit 3 SETB C C=1 flexible serial interface ports, voltage reference, time interval
OV = carry out of bit 6, but not 7 CLR C C=0 counter, dual 8-/16-bit PWM, power-on-reset
© 2004 Analog Devices, Inc. All rights reserved.
SUBB A,x C = borrow into bit 7 ANL C,bit C = C and bit Trademarks and registered trademarks are the
AC = borrow into bit 3 ANL C,/bit C = C and NOTbit property of their respective owners.
Purchase of licensed I2C components of Analog
OV = borrow into bit 6, but not 7 Devices or one of its sublicensed Associated
ORL C,bit C = C or bit
MUL AB C=0 Companies conveys a license for the purchaser
OV = (result>255) ORL C,/bit C = C or NOTbit under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the
DIV AB C=0 MOV C,bit C = bit system conforms to the I2C Standard Specification
as defined by Philips.
OV = divide by zero CJNE x,y,rel C = (x<y) Printed in the U.S.A. G04923-4-6/04(0) REV. 0
 ADCMODE ADC Mode register T3CON Timer 3 Control register
ADCMODE.6 60Hz reject filter enable (0=disable) T3CON.7 Timer 3 baud rate enable (0=disable)
Data Memory: RAM, SFRs, user Flash/EE (all read/write) SFR Map
ADCMODE.5
ADCMODE.4
primary ADC enable bit (0=disable)
auxiliary ADC enable bit (0=disable)
T3CON.2
T3CON.1
binary divide factor (DIV)
DIV = log[FCORE/(16·baudrate)] / log2
ADCMODE.3 chop mode disable bit (1=disable) T3CON.0 (rounded down)
ADCMODE.2 ADC mode bits:
ADCMODE.1 [off, idle, single-conv, continuous-conv, T3FD Timer 3 Fractional Divider register
ADCMODE.0 zero-cal, fs-cal, sys-zero-cal, sys-fs-cal]

PWMCON CFG845/7/8
T3FD = (2·FCORE) / (baudrate·2(DIV-1)) - 64

00h

DEh

53h

00h

00h

00h

00h

00h

00h

00h
PSMCON
ADCSTAT

PLLCON
ADC Status register

EDATA4
(reserved)

(reserved)

ADC0CON2 (reserved)

(reserved)

(reserved)

(reserved)
DPCON
SPIDAT

EADRH
CHIPID Chip ID Register

EWAIT

PCON
(AX hex = ADuC845/7/8)

SPH
RDY0 ADC0 ready indicator flag
Lower RAM RDY1 ADC1 ready indicator flag
CFG845/CFG847/CFG848 Config. Register
address

address
decimal

CAL calibration start control bit (set to begin cal)

NOXREF no external reference flag (only valid if ADC active) CFG84x.7 extended stack-pointer enable (0=disable)

00h DFh

D7h

00h C7h

00h BFh

00h AFh
B7h

00h A7h
F7h

00h 9Fh

87h
HEX

ERR0 primary ADC error flag (indicates result is clamped) CFG84x.0 internal XRAM select (0=external XRAM)
ERR1 auxiliary ADC error flag (indicates result is clamped)
WDCON Watchdog Timer control register
ADC0CON1 ADC0 Control register #1 PRE3 watchdog timeout selection bits

00h
127 7Fh ADC0CON1.7 buffer configuration bits: PRE2 0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms

EDATA3
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
INTVAL
EADRL

T3CON
ADC1L
ADC0CON1.6 [00=buffered, 10=unbuffered, others reserved] PRE1 8=0ms (immediate reset)
General Purpose

address

address
ADC0CON1.5 unipolar select bit (0=bipolar) PRE0 >8=reserved
... ... Area ADC0CON1.2 range select bits: WDIR watchdog interrupt response bit

MSB

LSB
ADC0CON1.1 [±20mV, ±40mV, ±80mV, ±160mV, WDS watchdog status flag (1 indicates watchdog timeout)
48 30h (bit addresses)

00h DEh

00h BEh

AEh
ADC0CON1.0 ±320mV, ±640mV, ±1.28V, ±2.56V] WDE watchdog enable control (0=disabled)

C6h
*xxh E6h

00h A6h

00h 9Eh
WDWR watchdog write enable bit (set to enable write)
ADC0CON2 ADC0 Control register #2
47 2Fh 7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h ADC0CON2.7 reference select bits PSMCON Power Supply Monitor control register

00h

*xxh

00h

00h

00h
ADC0CON2.6 [internal, REFIN pins, REFIN2 pins, reserved] PSMCON.7 DVDD status bit (1=above / 0=below trip point)

DACCON

EDATA2
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
ADC0CON2.3 channel select bits PSMCON.6 AVDD status bit (1=above / 0=below trip point)
46 2Eh 77h 76h 75h 74h 73h 72h 71h 70h

ADC1H

HOUR
GN1H

OF1H

ICON

T3FD
ADC0CON2.2 [1-COM, 2-COM, 3-COM, 4-COM, 5-COM, PSMCON.5 PSM interrupt bit

TH2

TH1
ADC0CON2.1 6-COM, 7-COM, 8-COM, 9-COM, 10-COM, PSMCON.4 DVDD trip point select bits
45 2Dh 6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h ADC0CON2.0 1-2, 3-4, 5-6, 7-8, 9-10, COM-COM] PSMCON.3 [4.63V, 3.08V, 2.93V, 2.63V]
PSMCON.2 AVDD trip point select bits
ADC1CON ADC1 Control register

00h DDh

00h CDh
*xxh EDh

00h BDh
00h FDh

9Dh

00h 8Dh
*xxh E5h

00h A5h
PSMCON.1 [4.63V, 3.08V, 2.93V, 2.63V]
44 2Ch 67h 66h 65h 64h 63h 62h 61h 60h

45h 0h
ADC1CON.6 REFIN select bit (0=internal reference) PSMCON.0 PSM enable (1=on / 0=off)
ADC1CON.5 unipolar select bit (0=bipolar)
SP Stack Pointer
43 2Bh 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h ADC1CON.3 channel select bits

00h

00h
ADC1CON.2 [1-COM, 2-COM, 3-COM, 4-COM, 5-COM,
SPH

EDATA1
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
PWM1H
Stack Pointer High byte

ADC1M
ADC1CON.1 6-COM, 7-COM, 8-COM, 9-COM, 10-COM,

DACH
42 2Ah 57h 56h 55h 54h 53h 52h 51h 50h

DPP
GN1L

OF1L
ADC1CON.0 1-2, 3-4, 5-6, 7-8, tempsens, COM-COM]

TH0
MIN
TL2
IE

SF
SF Sync Filter Register: Interrupt Enable register #1
41 29h Bit Addressable 4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h fADC = 4,096Hz / (3·SF) (chop on) EA enable interrupts (0=all interrupts disabled)

00h DCh

00h CCh
*xxh ECh

BCh
00h FCh
Area

00h D4h

00h 8Ch
*xxh E4h

00h B4h

00h A4h
fADC = 4,096Hz / (SF) (chop off) EADC enable ADCI (ADC interrupt)

00h 84h
ET2 enable TF2/EXF2 (Timer2 overflow interrupt)
40 28h 47h 46h 45h 44h 43h 42h 41h 40h OF0H,OF0M,OF0L ADC0 offset coefficient ES enable RI/TI (serial port interrupt)
ET1 enable TF1 (Timer1 overflow interrupt)
39 27h 3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h

ADCMODE ADC0CON1 ADC1CON

55h
OF1H,OF1L ADC1 offset coefficient EX1 enable IE1 (external interrupt 1)

RCAP2H

(reserved)

(reserved)

(reserved)

(reserved)
(not used)

I2CADD
PWM1L
ET0 enable TF0 (Timer0 overflow interrupt)

ADC0H
DACL

GN0H

OF0H
EX0 enable IE0 (external interrupt 0)
38 26h 37h 36h 35h 34h 33h 32h 31h 30h GN0H,GN0M,GN0L ADC0 gain coefficient

DPH
SEC

TL1
IEIP2 Interrupt Enable/Priority register #2
37 25h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h GN1H,GN1L ADC1 gain coefficient IEIP2.6 priority of TII interrupt (time interval)

00h DBh

00h CBh
*xxh EBh
FBh

07h D3h
*xxh E3h

00h B3h

00h A3h

00h 9Bh

00h 8Bh

00h 83h
IEIP2.5 priority of PSMI interrupt (power supply monitor)
ADC0H,ADC0M,ADC0L ADC0 data IEIP2.4 priority of ISPI/I2CI interrupt (serial interface)
36 24h 27h 26h 25h 24h 23h 22g 21h 20h IEIP2.3 (this bit must contain zero)
ADC1H,ADC1M,ADC1L ADC1 data IEIP2.2 enable TII interrupt (time interval)

AXh
7Fh
35 23h 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h IEIP2.1 enable PSMI interrupt (power supply monitor)

I2CADD1

HTHSEC
RCAP2L
(reserved)

(reserved)

(reserved)

(reserved)
PWM0H
ADC0M

I2CDAT
CHIPID
IEIP2.0 enable ISPI/I2CI interrupt (serial interface)
ICON

GN0M

OF0M
Current Source Control Register

DPL
IP

TL0
34 22h 17h 16h 15h 14h 13h 12h 11g 10h ICON.6 burnout current enable bit (0=disable) Interrupt Priority register
ICON.3 IEXC2 pin select bit [0=AIN8 / 1=AIN7] PADC priority of ADCI (ADC interrupt)

C2h
ICON.2 IEXC1 pin select bit [0=AIN7 / 1=AIN8] PT2 priority of TF2/EXF2 (Timer2 overflow interrupt)
33 21h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h

00h DAh

CAh
*xxh EAh

08h D2h
*xxh E2h

00h B2h

00h A2h

00h 9Ah

00h 8Ah
F2h

07h 82h
ICON.1 IEXC2 enable bit (0=disable) PS priority of RI/TI (serial port interrupt)
ICON.0 IEXC1 enable bit (0=disable) PT1 priority of TF1 (Timer1 overflow interrupt)
32 20h 07h 06h 05h 04h 03h 02h 01h 00h DACCON DAC Control register
PX1 priority of IE1 (external interrupt 1)
PT0 priority of TF0 (Timer0 overflow interrupt)

00h

A0h
TIMECON
DACCON.4 DAC pin select bit [0=DAC pin, 1=AINCOM pin] PX0 priority of IE0 (external interrupt 0)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
31 1Fh R7

PWM0L
ADC0L

TMOD
ECON
DACCON.3 ModeSelect (0=12bit, 1=8bit)

SBUF
GN0L
TMOD

OF0L

IEIP2
DACCON.2 RangeSelect (0=2.5V, 1=AVDD) Timer Mode register

SP
30 1Eh R6 DACCON.1
DACCON.0
Clear DAC (0=0V, 1=normal operation)
PowerDown DAC (0=off, 1=on)
TMOD.3/.7
TMOD.2/.6
gate control bit (0=ignore INTx)
counter/timer select bit (0=timer)
Register Bank 3

00h D9h

00h D1h
TMOD.1/.5 timer mode selecton bits

00h E9h

00h E1h

00h B9h

FFh B1h

00h A9h

FFh A1h
DACH,DACL

00h 99h

00h 89h

FFh 81h
29 1Dh R5 DAC data registers
Flash/EE “XRAM” TMOD.0/.4 [13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
(upper nibble = Timer1, lower nibble = Timer0)
data space extended RAM space PLLCON PLL Control register
28 1Ch R4 TCON Timer Control register
05h

00h

00h

10h

FFh
ADCSTAT
PLLCON.7 oscillator powerdown control bit (0=XTAL on)
SPICON

I2CCON

WDCON
T2CON
PLLCON.6 PLL lock indicator flag (0=out of lock) TF1 Timer1 overflow flag (auto cleared on vector to ISR)

SCON
27 1Bh R3

TCON
PSW
PLLCON.4 returns state of EA pin latched at power-up TR1 Timer1 run control (0=off, 1=run)

ACC

P3

P2

P1

P0
PLLCON.3 “fast interrupt” control bit (0=normal) TF0 Timer0 overflow flag (auto cleared on vector to ISR)

IP

IE
B

26 1Ah R2 3FFh ( page 1023 ) FFFFFFh PLLCON.2 3-bit clock divider value, “CD” (default=3): TR0 Timer0 run control (0=off, 1=run)
PLLCON.1 FCORE = 12,582,912Hz / 2CD IE1 external INT1 flag (auto cleared on vector to ISR)

D8h

D0h

C8h

C0h
E8h

E0h

B8h

B0h

A8h

A0h
F8h

F0h

98h

90h

88h

80h
PLLCON.0 IT1 IE1 type (0=level trig, 1=edge trig)
25 19h R1 TIMECON Time Interval Counter Control Register IE0 external INT0 flag (auto cleared on vector to ISR)
IT0 IE0 type (0=level trig, 1=edge trig)
TIMECON.6 24-hour mode select (0=0..255hour, 1=0..23hour)
24 18h R0 TIMECON.5 INTVAL timebase select bits TH0,TL0 Timer0 registers
TIMECON.4 [128th sec, seconds, minutes, hours]
23 17h R7 4kB TIMECON.3 single time interval control bit (0=reload&restart) TH1,TL1 Timer1 registers
(1K pages) TIMECON.2
TIMECON.1
time interval interrupt bit, “TII”
time interval enable bit (0=disable&clear) T2CON Timer2 Control register
22 16h R6 data
0

1
WDWR
TIMECON.0 time clock enable bit (0=disable)

CAP2
SPR0

TF2 overflow flag

RXD
PX0

EX0
I2CI

IT0
Flash/EE
Register Bank 2

INTVAL

T2
EXF2 external flag

RI
TIC Interval Register
P
21 15h R5 RCLK receive clock enable (0=Timer1 used for RxD clk)
(accessible
D8h

D0h

C8h

C0h
E8h

E0h

B8h

B0h

A8h

A0h
F8h

F0h

98h

90h

88h

80h
TCLK transmit clock enable (0=Timer1 used for TxD clk)
HTHSEC TIC Elapsed 128th Second Register
20 14h R4 through
EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX)
SEC TIC Elapsed Seconds Register TR2 run control (0=stop, 1=run)
SFRs) CNT2 timer/counter select (0=timer, 1=counter)
0

1
19 13h R3
I2CTX

MIN
SPR1

CNT2 TIC Elapsed Minutes Register

T2EX
CAP2 capture/reload select (0=reload, 1=capture)

WDE

TXD
PT0

ET0

IE0
F1

HOUR TH2,TL2 Timer2 register

TI
TIC Elapsed Hours Register
18 12h R2
D9h

D1h

C9h

C1h
E9h

E1h

B9h

B1h

A9h

A1h
F9h

F1h

99h

91h

89h

81h
ECON Data Flash/EE comand register RCAP2H,RCAP2L Timer2 Reload/Capture
17 11h R1 000h ( page 0 ) 01h
02h
READ page
PROGRAM page
81h READ byte
82h PROGRAM byte P0 Port0 register (also A0-A7 & D0-D7)
1

1
I2CRS
CPHA

ERR1

WDS
04h VERIFY page 0Fh EXIT ULOAD mode

INT0
16 10h R0

RB8
PX1

EX1
TR2
OV

IT1
05h ERASE page F0h ENTER ULOAD mode P1 Port1 register (analog & digital inputs)
7FFh 06h ERASE ALL (all others reserved)
T2EX timer/counter 2 capture/reload trigger
DAh

CAh
EAh

BAh

AAh
15 0Fh R7
D2h

C2h
FAh

E2h

B2h

A2h

9Ah

8Ah
F2h

92h

82h
EADRH,EADRL Data Flash/EE address registers T2 timer/counter 2 external input

14 0Eh R6
RAM & SFRs EDATA1,EDATA2,EDATA3,EDATA4
P2 Port2 register (also A8-A15 & A16-A23)
0

1
EXEN2
CPOL

NOXREF ERR0

WDIR

P3
I2CM

Port3 register
Register Bank 1

INT1
RS0

TB8
Data Flash/EE data registers
PT1

ET1

IE1
13 0Dh R5 RD external data memory read strobe
SPICON SPI Control register
DBh

CBh

WR external data memory write strobe

EBh

BBh

ABh
FBh

D3h

C3h
E3h

B3h

A3h

9Bh

8Bh
F3h

93h

83h
12 0Ch R4
FFh CFG84x.0=1 CFG84x.0=0 ISPI
WCOL
SPI interrupt (set by hardware at end of SPI transfer)
write collision error flag
T1
T0
timer/counter 1 external input
timer/counter 0 external input

11 0Bh R3 128 bytes SFRs SPE SPI enable (0=I2C enable, 1=SPI enable) INT1 external interrupt 1
0

1
INT0 external interrupt 0
internal external
TCLK

PRE0

SPIM master mode select (0=slave)

SPIM

upper RAM

REN
RS1

TR0
MDI

(direct TxD serial port transmit data line

PS

ES

CPOL clock polarity select (0=SCLK idles low)

T0

10 0Ah R2 (indirect data data CPHA clock phase select (0=leading edge latch) RxD serial port receive data line
addressing
DCh

CCh
ECh

BCh

ACh
FCh

SCON
D4h

C4h

9Ch

8Ch
SPR1 SPI bitrate select bits
E4h

B4h

A4h
F4h

94h

84h
Serial communications Control register
addressing memory memory SPR0 bitrate = FCORE / [2,4,8,16] (slave: SPR0=SS)
9 09h R1 only) SPIDAT
SM0 UART mode control bits baud rate:
only) SPI Data register SM1 00 - 8bit shift register - FCORE/12
0

1
8 08h R0 2kB (16MB 01 - 8bit UART - variable
RCLK

PRE1
MCO

I2CCON I C Control register

CAL

SM2
SPE

2
PT2

ET2

TF0
10 - 9bit UART - FCORE/64(x2)
F0

T1

7 07h R7 128 bytes addressable) MDO master mode SDATA output bit
SM2
11 - 9bit UART - variable
in modes 2&3, enables multiprocessor communication
DDh

CDh
EDh

BDh

ADh
FDh

D5h

C5h

9Dh

8Dh
E5h

B5h

A5h
F5h

95h

85h
MDE master mode SDATA output enable (0=disable)
lower RAM MCO master mode SCLK output bit
REN
TB8
receive enable control bit
in modes 2&3, 9th bit transmitted
6 06h R6 (direct or MDI master mode SDATA input bit
RB8 in modes 2&3, 9th bit received
I2CM master mode select bit (0=slave mode)
0

1
WCOL

TI transmit interrupt flag

indirect
Register Bank 0

EADC
PADC
RDY1

PRE2
EXF2

I2CRS serial port reset

MDE

5 05h R5
SM1

TR1 RI receive interrupt flag

WR
AC

I2CTX transmission direction status (0=RX,1=TX)

00h addressing) 000h

I2CI serial interface interrupt SBUF Serial port Buffer register
DEh

CEh
EEh

BEh

AEh

4 04h R4
FEh

D6h

C6h
E6h

B6h

A6h

9Eh

8Eh
F6h

96h

86h
I2CADD,I2CADD1 I2C slave Address registers
PCON Power Control register
3 03h R3 I2CDAT I2C Data register PCON.7 double baud rate control
0

1
PCON.4 ALE disable (0=normal, 1=forces ALE high)
RDY0

PRE3
MDO

SM0
ISPI

PWMCON PWM Control register

TF2

TF1

PCON.3 general purpose flag

RD
CY

EA

2 02h R2 PCON.2 general purpose flag

PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res., PCON.1 power-down control bit (recoverable with hard reset)
DFh

CFh
EFh

D7h

C7h

BFh

AFh
FFh

E7h

B7h

A7h
F7h

9Fh

8Fh
97h

87h

PWMCON.5 2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ,

1 01h R1 PWMCON.4 5=dual/8bit, 6=dual/16bitRZ, 7=reset/disable]
PCON.0 idle-mode control (recoverable with enabled interrupt)
PWMCON.3 PWM clock divide bits PSW Program Status Word
0 00h R0 PWMCON.2 PWM counter = clock / [1,4,16,64] CY carry flag
these bits are contained in this byte PWMCON.1 PWM clock source bits [0=FXTAL/15, 1=FXTAL,
MAP KEY

AC auxiliary carry flag

PWMCON.0 2=ext.clk. on P2.7, 3=FVCO(12.583MHz)] F0 general purpose flag 0
mnemonic mnemonic PWM0H,PWM0L PWM0 data registers RS1 register bank select control bits
SPR1 SPR0 SPICON RS0
OV
active register bank = [0,1,2,3]
overflow flag
PWM1H,PWM1L PWM1 data registers
address F9h 0 F8h 0 F8h 04h reset value F1 general purpose flag 1
lower RAM DPCON Data Pointer Control register
P parity of ACC

details SFR details reset value address DPCON.6 data pointer auto-toggle enable (0=disable)
DPP Data Pointer Page
DPCON.5 shadow data pointer mode control bits
DPCON.4 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl] DPH,DPL (DPTR) Data Pointer
* calibration coefficients are preconfigured at power-up to factory-calibrated values DPCON.3 main data pointer mode control bits
DPCON.2 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl] ACC Accumulator
DPCON.1 (not implemented to allow INC DPCON toggling)
DPCON.0 data pointer select [0=main, 1=shadow] B auxiliary math register