Nama : Daniel Adi Negoro Nim Kls : 1000880944 : 07 PAW

Instruction Set Assembly language

360 Assembly/Branch Instructions Unconditional branch

Register to register (RR)
Example1 Example2 * BR BALR R15 R14,R15 Branch to the location whose address is in Register 15 Branch to the location whose address is in Register 15, put return address in R14

Storage (RS)
Example1 * Example2 * Example3 * Example4 * LABEL1 * EQU * BAL B LABEL1 B X'010'(R15) B 4(R15) Branch to the location in R15 plus the (16 bit) decimal displacement of 4 Branch to the location in R15 plus the (16 bit) hex displacement of decimal 16 Branch to the location with the specified address (Base & displacement set by the Assembler) R14,X'010'(R15) Branch to location in (R15 plus displacement), put return address in R14. A location (within the range of the base register for the program)

Indexed (RX)
Example * B 4(R15,R1) Branch to location whose address is calculated from R15 plus 4 plus R1

Conditional branch
Storage (RS)
Example * Example * * * Example * BC 7,X'010'(R15) BC 8,4(R15) BE 4(R15) Branch to the location in (R15 plus 4), if previous comparison gave "Equal" condition (8) Branch to the location in (R15 plus 4), if previous comparison gave "Equal" condition (8) (same as above but specifying actual condition code value = 8) Branch to the location in (R15 plus X'010') if previous comparison gave "Unequal" condition (7)

Indexed (RX)
Example * BCT R1,4(R15) Reduce value in R1 by 1 and, if it is then zero, branch to location in (R15 plus 4 )

Register to register (RR)

Example * BCTR R1,R15 Reduce value in R1 by 1 and, if it is then zero, branch to address in R15

Arithmetic Operations * Operations are: ADD operand1 + operand2 ADC operand1 + operand2 + carry SUB operand1 - operand2 SBC operand1 - operand2 + carry -1 RSB operand2 - operand1 RSC operand2 - operand1 + carry - 1 * Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 * Examples ADD r0, r1, r2 SUBGT r3, r3, #1 RSBLES r4, r5, #5 Logical Operations * Operations are: AND operand1 AND operand2 EOR operand1 EOR operand2 ORR operand1 OR operand2 BIC operand1 AND NOT operand2 [ie bit clear] * Syntax: <Operation>{<cond>}{S} Rd, Rn, Operand2 * Examples: AND r0, r1, r2 BICEQ r2, r3, #7 EORS r1,r3,r0 Data Movement * Operations are: MOV operand2 MVN NOT operand2 Note that these make no use of operand1. * Syntax: <Operation>{<cond>}{S} Rd, Operand2 * Examples: MOV r0, r1 MOVS r2, #10 MVNEQ r1,#0

INSTRUCTION SUMMARY/M68000 Data Movement Operation Format

Integer Arithmetic Operation Format

Logical Operation Format

Shift and Rotate Operation Format

Program Control Instructions

System Control Operation Format

Data Processing Instructions Instruction

mov rd, n

Operation
rd = n

Example
mov r7, r5 ; r7 = r5

add rd, rn, n rd = rn + n add r0, r0, #1 ; r0 = r0 + 1 sub rd, rn, n rd = rn - n sub r0, r2, r1 ; r0 = r2 + r1 cmp rn, n rn - n cmp r1, r2 ; r1 - r2

ARM7500FE /Assembler syntax

1 MOV,MVN - single operand instructions <opcode>{cond}{S} Rd,<Op2> 2 CMP,CMN,TEQ,TST - instructions which do not produce a result. <opcode>{cond} Rn,<Op2> 3 AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC <opcode>{cond}{S} Rd,Rn,<Op2> where: <Op2> is Rm{,<shift>} or,<#expression> {cond} two-character condition mnemonic, see Figure 5-2: Condition codes on page 5-2 {S} set condition codes if S present (implied for CMP, CMN, TEQ, TST). Rd, Rn and Rm are expressions evaluating to a register number. <#expression> if used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. If this is impossible, it will give an error.

<shift>

is <shiftname> <register> or <shiftname> #expression, or RRX (rotate right one bit with extend). <shiftname> is: ASL, LSL, LSR, ASR, ROR. (ASL is a synonym for LSL; they assemble to the same code.)

Example
ADDEQ R2,R4,R5 TEQS R4,#3 SUB R4,R5,R7,LSR R2; ;logical right shift R7 by the number in ;the bottom byte of R2, subtract result ;from R5, and put the answer into R4 ;return from subroutine ;return from exception and restore CPSR ;from SPSR_mode ;if the Z flag is set make R2:=R4+R ;test R4 for equality with 3 ;(the S is in fact redundant as the ;assembler inserts it automatically)

MOV PC,R14 MOVS PC,R14