Examples of SSI chip pin layouts

7400

7404

7408

7411

7422

7430

7432

7486

A circuit for the majority function of three variables

A chip representation of the majority function A A' A'BC

A'BC+AB'C

. .

B'

C'

. .

AB'C

ABC'

Output

ABC+ABC' A B C

ABC

Design levels for digital computers: - systems level - interfacing the components - CPU chips - memory chips - I/O chips - digital logic level - designing the chips - using logic gates - device level - designing the logic gates - using transistors

Digital Logic Level: - combinational circuits - the input determines the output - if the input changes, the output changes - the system does not have to remember the current state - sequential circuits - the output depends on: - the input - the current state - the sequence is synchronized by a clock - timing determines when a change in input will produce a change in output

Combinational circuits: - have multiple inputs - have multiple outputs - implemented in MSI chips

- typical combinational circuits include: - binary adders - comparators - decoders - encoders - multiplexers - demultiplexers - shifters

Multiplexer

(MUX)

- selects 1 of its (multiple) input lines and sends it to its one output line - has more than 1 input, but only 1 output - the control line determines which input line is selected

- as a block diagram:

data line 0 data line 1 output line X

control line A

Corresponds to: 2-to-1 multiplexer: If A = 0 Output D0 Else Output D1

As a logic diagram:

A 4-input (or 4-to-1) multiplexer (block diagram):

Each AND gate has 3 inputs: 1 data line 2 control lines

The control lines determine which AND gate can output a 1

A 4-input (or 4-to-1) multiplexer:

An eight-input multiplexer circuit

Demultiplexer: - the reverse of a multiplexer - has 1 input signal - has n control lines and 2n output lines - e.g. a 2-bit demultiplexer - value of its 1 input line is sent to 1 of the 4 output lines - depending on the value of its 2 control lines

D0 input D1 D2 D3

C1

C0

Decoder: - takes an n-bit number as input - has 2n output lines (1 for each combination of the n bits) - one of the 2n output lines is set to 1 - the other output lines are 0

Truth table: Input A B 0 0 0 1 1 0 1 1 Output D 1 D2 0 0 1 0 0 1 0 0

D0 1 0 0 0

D3 0 0 0 1

A 2-to-4 decoder

A 3-to-8 decoder circuit

Shifter: - shifts the n-bit input one bit to the right or left - has n input lines and n output lines - has 1 control line to determine direction of shift - 0 = left, 1 = right

A 1-bit left/right shifter

Code converters: - translate input word into a corresponding new code word - number of input lines may differ from number of output lines Problem: - design a BCD-to-some-other-code converter - using dont care conditions, given the following truth table

Inputs (BCD) A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1

Outputs (some other code) W 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 0 1 1 1 1 Y 0 0 1 1 0 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1

0 1 2 3 4 5 6 7 8 9

Code converter - continued

- must build a k-map for each of the output lines - using the values of ABCD when the output line is 1 - can use the dont care conditions to group

AB 00 CD 00 01 11 10

01

11 X

10 1 1 X X

1 1 1

X X X

Inputs (BCD) A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0

Outputs (some other code) D 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 0 1 1 1 1 Y 0 0 1 1 0 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1 W= A + BD + BC

0 1 2 3 4 5 6 7 8 9

AB 00 CD 00 01 11 10 X=

01 1

11 X X

10 1 1 X X

1 1

X X

A + BC + BD'

Code converter - continued

AB 00 CD 00 01 Inputs (BCD) A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 Outputs (some other code) D 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X 0 0 0 0 1 0 1 1 1 1 Y 0 0 1 1 0 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 0 1 11 10 1 1

01

11 X

10 1 1 X X

X X X

0 1 2 3 4 5 6 7 8 9

Y=

A + B'C + BCD

AB 00 CD 00 01 11 10 Z= D 1 1

01

11 X

10

1 1

X X X

1 X X

Code converter - continued - the logic diagram:

W = A + BC + BD X = A + BC + BD' Y = A + B'C + BC'D Z =D

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Comparator: - compares 2 n-bit data words - output will be 1 if the words are equal, 0 if they are not - compares matching bits from 2 words - rst: xor the matching bits - returns 0 if they are equal, 1 if not - then: results from n bits are output to a nor gate - if each pair was 0 (matching), nal result is 1

A simple 2-bit comparator

A simple 4-bit comparator

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-Comparator can also check for > and < - e.g. for a 2-bit word - possibilities are: 00 01 10 11 - possibilities for A > B: A = 11 and B = 10 or 01 or 00 A = 10 and B = 01 or 00 A = 01 and B = 00 or 1110 1101 1100 1001 1000 0100

B1B0

A1A 0 00 00 01 11 10

A0B'1B'0 01 1 11 1 1 10 1 1 A1B'1

1 A1A 0B'0

2-bit comparator for A = B and A > B

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Addition: - the most common arithmetic operation performed by a digital computer - if the hardware can add two binary numbers - the other three primitive arithmetic operations - subtraction, multiplication and division - can be performed with the addition hardware - subtraction is performed using two's complement arithmetic - multiplication can be done using repeated addition (or shifting and adding) - division can be done using repeated subtraction - addition is implemented by using two different types of adder circuits - a half-adder - to add 2 bits -a full adder - to add 3 bits - 2 bits and a carry

Half-adder: - adds 2 1-bit numbers - the sum and carry are generated A0 B0 S0

+ C0

block diagram:

bits to be added

sum

carry

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The half-adder: Sum s 0 1 1 0 Carry c 0 0 0 1

a 0 0 1 1

b 0 1 0 1

Sum : Carry:

s = a'b + ab' = a xor b c = ab

Alternate diagram for Half-Adder

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Full adder: - to add 2 2-bit numbers - the sum and carry are generated for the least signicant digit - but - all subsequent bits need to have the carry bit added in - needs to add 3 bits - so full adder adds 3 bits and generates a sum and a carry - made up of 2 half-adders A1 A0 B1 B0

block diagram:

bits to be added

sum carry

Full adder - continued: - usually the full adder circuit uses 2 half-adders and an OR gate - rst half adder adds A and B (a bit from each number) - second half adder adds the sum from the rst half-adder and the carry in - if either half adder has a carry, it is sent to carry out

First: A plus B:

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Then the second half-adder: - (The sum of A plus B) plus (the carry in)

How the formula is derived:

The full adder: Carry In c 0 1 0 1 0 1 0 1 Sum s 0 1 1 0 1 0 0 1 Carry Out c out 0 0 0 1 0 1 1 1

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

Sum: s = a'b'c + a'bc' + ab'c' + abc

Carry: cout = a'bc + ab'c + abc' + abc

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The full adder: Carry In c 0 1 0 1 0 1 0 1 Sum s 0 1 1 0 1 0 0 1 Carry Out c out 0 0 0 1 0 1 1 1

ab cin
0

00

01 1

11

10 1

a 0 0 0 0 1 1 1 1 Carry

b 0 0 1 1 0 0 1 1

1
1

1 1

Sum: s = a'b'c + a'bc' + ab'c' + abc

Carry: cout = a'bc + ab'c + abc' + abc

= a'bc + ab'c + abc' + abc = a'bc + ab'c + ab(c' + c) = (a'b + ab')c + ab(1) = (a xor b)c + ab or ab + bc + ac

cin

ab
0 1

00

01

11

10

1 1 1 1 1

Sum =

a'b'c + a'bc' + ab'c' + abc = = = = = = = = = = = =

(can reorder) (can factor out c and c)

a'b'c + abc + a'bc' + ab'c

(a'b' + ab)c + (a'b + ab')c (this is a xor b) (and this is a xnor b) (a'b' + ab)''c + (a'b + ab')c [(a'b')'(ab)']'c + (a'b + ab')c [(a'' + b'')(a' + b')]'c + (a'b + ab')c [(a + b)(a' + b')]'c + (a'b + ab')c (aa' + ab' + ba' + bb')'c + (a'b + ab')c (0 + ab' + ba' + 0)'c + (a'b + ab')c (ab' + ba')'c + (a'b +ab')c (a'b + ab')'c + (a'b + ab')c (a xor b)'c + (a xor b)c (a xor b) xor c

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XOR: XNOR: So . . .

AB + AB AB + AB (the 2 cases that are not the XOR)

C (AB + AB) + C (AB + AB) is the same as C (A xnor B) + C (A xor B) which is the same as C (A xor B) + C (A xor B) XY + XY or X xor Y

which is the equivalent of and . . . becomes

C (A xor B) + C (A xor B) C xor (A xor B)

Alternate diagram for Full Adder

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b 3 a3

b 2 a2

b 1 a1

b 0 a0

c3 s3

c2 s2

c1 s1

c0 s0

Circuit design for a 4-bit adder - parallel binary adder (or ripple-carry adder)

A 1-bit ALU

ab a+b Data bus: b

enable lines

output may be from any of the functions

Decoder: (to choose function) F0 0 0 1 1 F1 0 1 0 1 function ab a+b b a plus b

enable line for adder

-anded with the result from the xor gates (sum) and with the gates computing the carry out

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Sequential circuits: - combinational circuits combined with memory - output depends on both input and the current state of the circuit - timing determines when a change in input will produce a change in output - controlled by the clock - use gates and memory elements called ip-ops - this circuit will hold and store its value

The latch: - adds a feedback loop - the output of each gate feeds into the input of another gate - is the basis for computer memory

A latch: - a circuit that will hold and store its values - adds a feedback loop to a circuit - output of each gate feeds back to the input of a previous gate

- a D-latch: (data latch) - has 2 outputs

- the complement of the true output

- the true output

20

gate #1

gate #2

- if D = 1 - output of gate #1 will be 0 (Q') - inputs to gate #2 will both be 0 - Q will be 1 and stay 1 - so the latch is set to 1

- if D = 0 - the reverse process occurs - Q will be 0 - and the latch is reset to 0

Positive Clock Pulses

logical 1

logical 0 Clock cycle

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a clocked D-latch - to prevent the latch from changing its state until we want it to change - adds a clock and 2 and gates - the clock enables the and gates - the inputs are now D and the clock - the outputs are still Q and Q' gate #1

gate #2

- the clock is normally 0 - keeps input to the NOR gates 0 (no matter what the value of D) - so the latch does not change state - when the clock is 1: - the latch is enabled - it responds to the value of D - input to gate 2 is always the complement of D

gate #1

gate #2

22

Clocked D-latch

Truth table: Clk D 1 0 1 1 0 X

Q 0 1 Q

Q 1 0 Q

- if the clock = 0 the latch is stable - it remembers its previous state

- to load the current value of D into the circuit (into memory) - a positive pulse is put on the clock line

Positive Clock Pulses

logical 1

logical 0 Clock cycle Rising edge of pulse (Leading edge) Falling edge of pulse (Trailing edge)

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- a D ip-op - responds to input only when the clock is making the transition from low to high (or high to low) - responds on the leading edge or the trailing edge of the clock pulse

A gate delay

Characteristic Table: - describes the state of a sequential circuit after 1 clock pulse for given inputs and given initial state

- for the D ip-op - only 1 input besides the clock

Before the pulse D(t) 0 0 1 1 Q(t) 0 1 0 1

After the pulse Q(t+1) 0 0 1 1

24

D-latch:

d ck

d ck

State changes on high voltage (level is 1)

State changes on low voltage (level is 0)

D ip-op:

d ck

d ck

Flip-op on the leading edge

Flip-op on the falling edge

Data bus

Logic diagram for a 4 x 3 memory Each row is one 3-bit word. A read or write operation reads or writes a complete word.

Decoder

Control lines Data bus

25

Data bus

3-bit memory (3 ip-ops)

only used for a write operation Logic diagram for a 4 x 3 memory Each row is one 3-bit word. A read or write operation reads or writes a complete word.

Decoder

selects word (address bus)

Chooses read or write operation (control bus)

Control lines

only used for a read operation Data bus

detail from memory diagram: the non-inverting buffer: - has a data input and a control input - has 1 data output - can act like an open circuit - if control signal is high - buffer acts like a conducting wire - if control signal is low - buffer acts like an open circuit data in control in data out

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- the memory circuit - the CS line must be asserted - it is anded with the inverted RD line into the write gate - it is anded with the RD line and the OE line to become a control line for the outputs - the address lines input to a decoder - selects one line that enables one of the memory words - for a READ operation: - the control lines are set to 111 - CS, RD and OE are asserted - the input lines are not used - the address lines are set to the word to be read - the word is placed on the data output lines - Q is anded with the word select line - the result is the input to an OR gate - the output becomes the input to a non-inverting buffer

If: Word 1 = 101

If: A1 = 0 A0 = 1

If: CS = 1 RD = 1 OE = 1

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