Department of Electrical Engineering

McGill University
ECSE 221 Introduction to Computer Engineering I
Final Examination

Thursday, April 21st, 2005 2:00pm

Examiner: Prof. F.P. Ferrie

Associate Examiner: Prof. J. Clark

Instructions:

Answer ALL questions in the examination booklet provided, showing all of your work.
Calculators are permitted, but they must be the Faculty standard. All questions are equally
weighted.

Question 1

a) The IEEE double precision format has a 52-bit mantissa. Determine the precision and
range of real numbers that can be represented using this format. [2 points]
b) Divide 101001112 by 1112 using binary long division. [2 points]
c) Encode the number –1.42 x 10-19 using IEEE-754 single precision floating-point format.
Express your answer an 8-digit hexadecimal number. [2 points]
d) Prove that the contents of two binary variables, A and B, can be exchanged by the
following sequence of operations: A=XOR(A,B) B=XOR(A,B) A=XOR(A,B) [2 points]
e) Determine the minimal canonical forms corresponding to the following sum of products
form: ∑ (5,8,9,10,12,13,14) [2 points]
A,B ,C ,D

Question 2
€

+5V +5V +5V

S S Q1 S Q0
J Q Q2 J Q J Q
C C C
KR Q KR Q KR Q

+5V

Clr

Clk

Mode

1
The circuit shown on the previous page is comprised of rising edge-triggered J-K flip-flops and
combinational logic. At T=0, it is initialized to <Q2=0, Q1=0, Q0=0> by applying a reset pulse
to the asynchronous Clr input. Under normal operation, the circuit will count in one of two
sequences depending on whether the Mode input is 1 or 0. Answer the following questions:

a) Determine the next state equations corresponding to Q2, Q1, and Q0 respectively. Use
these equations to then determine the state transition table corresponding to this circuit.
[3 points]
b) Assume that each gate has Tpd=0.1nS and that gates with inverted inputs (indicated by a
bubble on the inverted input) have Tpd=0.15nS. The timing parameters for flip-flops Q2
and Q0 are identical, Tpd=1nS, Th=0.1nS, and Tsu=0.25nS. Flip-flop Q1 has
Tpd=1.5nS, Th=0nS, and Tsu=0.4nS. Determine the maximum frequency of operation
for this circuit. Next, produce a detailed timing diagram showing three clock transitions
beginning with <Q2=0, Q1=0, Q0=0> and Mode=0. [3 points]
c) Show how this circuit can be re-implemented with a read-only memory (ROM) and 3 D
flip-flops. List the contents of the ROM using hexadecimal notation and determine the
minimum access time (i.e. Tpd) necessary for the resulting circuit to operate at the same
maximum frequency as the initial implementation. Assume that the D flip-flops have
identical parameters to Q1 in the original circuit. [2 points]
d) Suppose the edge-triggered J-K flip-flops were replaced by master-slave versions.
Compute the maximum frequency of operation assuming identical Tpd to the edge-
triggered flip-flop, and a clock that is high for exactly half the clock period. [2 points]

Question 3

a) Translate the following “C” function into MIPS assembly language, strictly adhering to
context save/restore conventions. [4 points]

int bitrev(unsigned int arg)

{
int i;
char stack[33], *stkptr;

stkptr = &stack[0];

for (i=0; i<32; i++) {

*++stkptr=arg&1;
arg >>= 1;
}

arg = 0;

for (i=0; i<32; i++) {

if (*stkptr-- == 1) arg |= 0x80000000;
if (i < 31) arg >>= 1;
}

return(arg);

2
 The single function argument is to be passed in $4 with the function return in $6. Notice
that the function implements stack PUSH and POP operations using a local array for
storage. It is not necessary to replicate this in your assembly code – use the actual stack
instead (this simplifies the code considerably).

Useful hints on “C” syntax:

*++stkptr = arg; Increments the pointer and then assigns arg to the pointer location.
arg = *stkptr--; Reads arg from the pointer location and then decrements pointer.

b) Consider the following snippet of MIPS assembly code:

.text 0x4000000

li $10, 10
li $11, 0x1000000

la10: sw $0, 0($11)

addi $10, $10, -1
beq $10, $0, la20:
j la10:
la20: li $2, 10
syscall

Determine the memory address of the beq instruction and the contents of this memory
location. Do the same for the j instruction. Express all answers as 8-digit, hexadecimal
numbers. [2 points]

c) Consider the following data segment in MIPS assembly code:

.data 0x10001a
string1: .asciiz “ASCII-encoded string!\n”

.align 2
array1: .word 34, 55, –24, -17
string2: .asciiz “Another string\n”

.align 2
array2: .word 4, -3, 16, 17

Determine the memory location of the second element of array2. Explain in one sentence
precisely what the .align 2 pseudo-instruction does. [2 points]

d) Answer the following questions about the MIPS architecture:

i) What is the range of a branch instruction?
ii) Why is a branch preferred over a jump (1 or 2 sentences)?
iii) What is the range of a jump instruction?
iv) Under what circumstances is it necessary to include $31 in the context save
portion of a function?
[2 points]

3
Question 4

A 36-bit ALU is fabricated using six 6-bit modules with 2 levels of carry generation.
Assuming that all gates used in fabrication have a propagation delay Tpd = 0.1 nS, answer
the following questions:

a) Write down the expression for the carry out of the first 6-bit module in terms of pi = ai +
bi and gi = ai bi and the carry in c0. What is Tpd for carry out? [2 points]
b) The ALU is required to perform 4 basic operations: ADD, SUBTRACT, bitwise AND,
and bitwise OR. Assuming that a 1-bit full-adder module is available, draw the circuit
diagram for the corresponding 1-bit ALU cell. Including carry generation, calculate Tpd
for the 6-bit ALU assuming that multiplexer delays are negligible. [2 points]
c) Each six-bit ALU generates corresponding Pi and Gi terms for the second level of carry
generation. Write down the expressions for P0 and G0 in terms of the corresponding pi
and gi. Taking into account this second level of carry generation, what is Tpd for the 36-
bit ALU? Suppose that carries were instead propagated serially by connecting the carry
out of a 6-bit module to the carry in of the adjacent module. What would be the Tpd for
the 36-bit ALU in this case? [2 points]
d) In Assignment 5, you implemented a non-restoring divider with an 8-bit datapath.
Consider a 4-bit implementation of this datapath. On the first clock pulse, 2816 is loaded
into the remainder register, and 7 is loaded into the divisor register. For each remaining
clock pulse, list the contents of the remainder register (H and L). [2 points]
e) Assume that a non-restoring divider is fabricated for a 36-bit datapath using the ALU
from Part (b), Tcl ≈ Tpd(ALU), and all other delays are negligible. What is the worst
case time required to perform binary division? [2 points]

4
Question 5

The datapath for the multi-cycle implementation of the MIPS architecture is shown below.

Assume that the datapath has the following parameters:

For all registers: Tsu = 0.1nS, Th = 0nS, Tpd = 1.5nS
For all multiplexers: Tpd = 0.2nS
For the register file: Ta = 1nS
For the ALU Tpd = 10nS
For the Memory Ta = 10.2nS (for both read and write operations)
All other delays may be neglected.

a) Write down the sequence of microinstructions corresponding to the J instruction. List

them by name along with their corresponding register transfers and datapath settings.
Make sure to use register transfer notation (do not use micro-program notation).
[2 points]
b) Although the microinstructions corresponding to the JR instruction were not discussed in
the Patterson and Hennessy text, they are relatively easy to figure out from examination
of the J instruction and the datapath. Write down this sequence of microinstructions
and datapath settings using the same format as Part (a). (Since the first two
microinstructions are common, you may begin with the third microinstruction in the
sequence). [2 points]
c) Given the parameters listed above, determine Tcl for this datapath. Make sure to clearly
show how you arrived at this number. Determine the datapath’s maximum frequency of
operation. [2 points]
d) Assume that the datapath controller were implemented directly from its corresponding
state transition table, using the ROM-based technique discussed in class and used in
Assignment 5. How many inputs, state variables, and outputs need to be represented in

5
 order to implement the simplified version of the MIPS architecture (no exception
handling)? How many address lines and how many data lines are required for the
corresponding ROM? Assuming that the registers used in this controller are identical to
the ones used in the MIPS datapath, what is the minimum access time (e.g. Tpd) for this
ROM? [2 points]
e) Answer the following general questions about the MIPS architecture:
i) Give a one sentence definition of an exception.
ii) Aside from the underlying gate (switch) technology, what are the primary
limitations on the speed of the MIPS datapath?
iii) List two advantages of the multi-cycle datapath over the single-cycle
implementation.
iv) Some machines automatically push the return address of a function call onto
the stack. Why is this not necessarily a good idea? (one sentence)
[2 points]

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Appendix - MIPS Instruction Set

7
Appendix – MIPS Machine Language