Department of Electrical Engineering

McGill University
ECSE 221 Introduction to Computer Engineering I
Final Examination

Friday, April 25th, 2003 2:00pm

Examiner: Prof. F.P. Ferrie

Associate Examiner: Prof. D. Lowther

Instructions:

Answer ALL questions in the examination booklet provided, showing all of your work.
Calculators are permitted, but they must be the Faculty standard. All questions are equally
weighted.

Question 1

a) A particular computer represents a long integer using a 24-bit register. Determine the
number ranges corresponding to data types long and unsigned long. [2 points]
b) This same computer uses an IEEE like representation to encode floating point numbers
using a single 24-bit register. Assuming that the precision of the mantissa is guaranteed
to a maximum of 4 significant figures (base 10), determine the bias, exponent range, and
number range that can be represented using this scheme. [3 points]
c) Encode the number 5.37 x 10-21 to equivalent precision using this representation and
express your result as a hexadecimal number. If you are unsure of your answer to (b),
you may use IEEE 754 instead, but with a penalty of 1 point. [3 points]
d) Finally, assuming that this computer uses a MIPS like memory accessing scheme (i.e.
lw/sw instructions), then what is the maximum size of memory that can be installed in
this computer? [2 points]

Question 2

Mult
A1 P3
A0 P2
B1 P1
B0 P0

a) Write down the truth table corresponding to the 2-bit x 2-bit binary multiplier shown
above, where [A1,A0] and [B1,B0] correspond to the multiplicand and multiplier
respectively. Make sure that your truth table is ordered as follows: (A1 A0 B1 B0) |
(P3 P2 P1 P0). [2 points]

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 b) Determine the minimal forms (∑∏, ∏∑) corresponding to the P1 output of the multiplier.
[3 points]
c) For the circuit shown below, determine the next state equations for each flip-flop as well
as the corresponding state transition table. In producing your table, make sure that the
order is [Q1, Q0]. [3 points].
+5V

+5V

S Q1 S Q0
J Q D Q
C
KR Q C R Q

1 Reset
Clock
0

d) Assume that the circuit is implemented with rising edge-triggered flip-flops. The
parameters for the JK flop-flop are Tsu=2nS, Th=0nS, Tpd=6nS, and for the D flip-flop
Tsu=1nS, Th=3nS, Tpd=8nS. Tpd for the exclusive OR gate is not known directly, but
the gate is known to be comprised (internally) entirely of NAND gates, each with
Tpd=1nS. Determine the maximum frequency of operation of the circuit. Sketch the
corresponding timing diagram showing the complete set of state transitions (you may
ignore the delays in your diagram).

Question 3

a) Write a MIPS assembly language function that computes the sum of the ASCII values of
a character string to 8-bits (modulo 255), and then adds this value to the end of the string.
The following prototype is to be used:

void cksum(char *s);

Example: If the string passed is “ABCDE” (0x41 0x42 0x43 0x44 0x45 0x00), then on
completion the string becomes “ABCDEO” (0x41 0x42 0x43 0x44 0x45 0x4f 0x00).
You may assume that the pointer to the string is passed in $4. Your function must follow
proper conventions with respect to context. [4 points]
b) Explain the essential difference between a branch and a jump instruction (1 sentence).
Under what circumstance must a branch be replaced by a jump instruction (1 sentence).
[2 points]
c) Some machines automatically push the return register ($31) on the stack on a function
call. Explain under what circumstance this would not be desirable and the consequence
(penalty). [2 points]

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 d) Analyze the following MIPS assembly segment and determine the address corresponding
to the 3rd element of array2. [2 points]

.data 0x100006

.align 2

string1: .asciiz “This is a string”

.align 2

array1: .word 0x37, 0x38, 0x39, 0x40

array2: .word 0x100, 0x101, 0x102, 0x103, 0x104

Question 4

a) A 36-bit full adder is composed of six 6-bit units, each of which incorporates a carry
lookahead generator. Assuming that pi and gi are available as inputs to the carry
generator function, write down the expression for the carry out of a single 6-bit module.
[2 points]
b) The carry in to each 6-bit module is determined by a second level of carry generation.
Assuming that each module generates Pi and Gi outputs, what is the expression for the
carry input to the 5th module in the chain? Calculate the propagation delay associated
with this input, showing how you arrived at your answer. [2 points]
c) Sketch the datapath corresponding to the final version of the binary division algorithm
described in the text, clearly labeling each of the necessary control lines. Briefly describe
the action associated with each control line. [2 points]
d) List the changes (to the datapath) necessary to implement a non-restoring division
algorithm. Assuming that the MIPS implementation of the div instruction uses the same
algorithm, what is the maximum number of ALU operations necessary to perform all
steps of the algorithm. [2 points]
e) Using the expression obtained in (a), determine the total number of switches necessary to
implement the carry generator, assuming that no passive devices are used in the gate
construction. [2 points]

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 Question 5

The datapath for the multi-cycle implementation of the MIPS architecture is shown below.

Assume that the datapath has the following parameters:

For all registers: Tsu = 500pS, Th = 0nS, Tpd = 5nS

For all multiplexers: Tpd = 1nS
For the register file: Ta = 2nS
For the ALU Tpd = 10nS
For the Memory Ta = 15nS (for both read and write operations)
All other delays may be neglected.

a) All MIPS instructions have the same first two microinstructions in common. For each of
these microinstructions list the register transfer operations that take place (using register
transfer notation) along with the necessary control line settings. [2 points]
b) List the register transfer operations corresponding to the third step of the jump (j)
instruction and associated control line settings. Using this as a starting point, describe
what would be needed to implement the jump and link (jal) instruction. First, describe
what needs to be done to the datapath. Next, describe how the 3rd microinstruction needs
to be modified to support jal. Is a 4th microinstruction necessary? [3 points]
c) What changes to the datapath would be necessary to support the jump register (jr)
instruction? How would the 3rd microinstruction need to be modified to support jr? Is a
4th microinstruction necessary? If so, describe the corresponding register transfer
operations. [3 points]
d) Given the datapath timing parameters, estimate the maximum clock frequency for this
datapath. [2 points]

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Appendix - MIPS Instruction Set