Design and implementation of general purpose opamp using multipath frequency compensation

Pawel Fiedorow , Philippe Maige , Daniel Subiela , Thierry Tixier and Nacer Abouchi
- Grenoble, France Email: pawel.edorow@cpe.fr, philippe.maige@st.com, daniel.subiela@st.com University of Lyon - Lyon Institute of Nanotechnology (INL) - CPE Lyon, France Email: thierry.tixier@cpe.fr, nacer.abouchi@cpe.fr
STMicroelectronics

AbstractThis paper shows the multipath frequency compensation in a general purpose operational amplier. Firstly, it deals with the requirements of a general purpose opamp and introduces the need of the frequency compensation in the current circuits. Then, the rules to integrate multipath in an opamp are developed and the transfer function is presented and compared to the one of the nested miller compensation. Next, an implementation of the multipath nested miller compensation is described. Finally, simulation result which proves the efciency of this compensation is given. The multipath compensation improves the classical compensation structure as it does not cutoff the initial unity gain frequency by four but only by two.

of nowadays compensation structure and their limitations. The third part describes the characteristics of the different multipath compensation and the aim of these compensations. In the fourth part, the design of a full general purpose opamp is proposed. The different blocks of the opamp are analyzed. Finally, the same part illustrates the great effect of the multipath add-on. II. D ESIGN OF THE GENERAL PURPOSE AMPLIFIER A. Requirements The main difculty of the general purpose opamp design is the incertitude of the environment in which the opamp will be used. The specication are as large as possible. However analog design is a trade-off history. Some common properties are dening the general purpose area : rail to rail input and/or output, high factor of merit, class AB output stage, unity gain stability. With this aim, the following part presents the main step of one circuit design. As the voltage supply are lowering, schematics have a trend to be more horizontal than vertical. It means that transistors are no more stacked but they are cascaded. Thus, for readability and understanding the circuit is analyzed in three functional parts. B. Block analysis The rst block illustrated on gure 1 represents the input stage. The transistors M3-M4 and M8-M9 are the PMOS and
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I. I NTRODUCTION The shrinking of the digital circuit to integrate more and more functions on a cell is also impacting the development of analog parts. In this way, the general purpose operational amplier (opamp) has to deal with the reduction of supply voltage and current consumption on one side and with the increase of functionalities like class AB output stage on the other side. The general purpose opamp is characterized by rail to rail input and output stages with a gain bandwidth product of hundreds of kilohertz and supply voltages around several volts. The load capacitance and power consumption is the discriminant between the constructors. In this context, the design of general purpose opamp is leaded by the power consumption and the obtainable gain bandwidth product for a dened load capacitance. The reduced supply voltage range has leaded to the multiplication of the gain stages [1]. Besides, each gain stage has an high output impedance node. Consequently, as each high impedance node produces a pole, the more gain stages are needed to achieve high low-frequency gain the more poles are introduced. Beyond two poles, the phase rolls over one hundred eighty degrees and the structure is stable if the poles are separated and one of them is at a higher frequency than the unity gain frequency. This separation is done with the frequency compensation [1]. Numerous articles [2] deal with the studies of frequency compensation method in the eld of dedicated opamp. In [1], [3], [4] is presented the multipath technique for opamp applications. However, none of these articles describe the implementation of the multipath technique into a general purpose opamp. In the second part, this article tries to give an overview of the frequency compensation in opamp through the explanation

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Fig. 1.

MNMC - Block 1

NMOS input differential pairs respectively. They are biased with the PMOS M5 and the NMOS M7. While the common mode voltage is increasing, the transition between the PMOS

pair and the NMOS pair is assured by the transistors M0-M1M2-M6. The threshold is xed through M0 biased by M1. In this way, all the common mode swings from the upper to the lower rail. The folded-cascode current mirror M10-M17 acts as a level shifter and allows the connection to the second block. It subtracts the differential output currents of the input stage and brings the result out at a single terminal. This last terminal is connected to the gate of the common source NMOS M28. With the modied folded-cascode M29M38, they form the second gain stage described on gure 2. In fact, the multipath stage is also presented on gure 2. The
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around 1.4 V in a typical case. If we consider the process and temperature variation from 40 to 125 , this value increases to 2.2 V. Thus, this stage is quite often the one which limits the upper supply rail for low voltage application. The active devices of the frequency compensation have been presented on gure 2. Figure 4 shows the capacitor network related to the NMC. The circuit needs ve of them. As the
Y1 Cc1p X Cc2 Cc1n Y2 Cc1bn Yb2 Yb1 Cc1bp OUT

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Fig. 4.

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Fig. 2.

MNMC - Block 2

same input stage as in gure 1 is made with M18 - M27. Thus, the multipath block behaves like the input pair of the main chain. We call back that the gain-bandwidth product of the main chain and the one of the multipath have to be equal. In the second block, the biasing of the folded-cascode current mirror is made with a oating current source. It is linked to the architecture of the class AB output stage. Consequently, Y1 and Y2 are the driver of output PMOS and NMOS respectively. The output stage [5] is a standard in the eld of class AB drivers. It uses the properties of MOS translinear loop. The complementary output devices M48 - M49 change their conduction in response to the complementary common-gate level shifters M44 - M43. In a standard process, the main
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second gain stage is made of one common source transistor, the outer capacitor Cc2 is implemented in the same way on the two gures. Moreover the capacitor Cc1 is split into two groups of two capacitors. The rst division is used to satisfy the symmetry between the N side and the P side on the output transistors. On each side, the capacitor is divided again in a ratio (Cc1bx = {2/3}, Cc1x = {1/3}). A theoretical study not developed in this paper has led to these ratios. This type of splitting allows the use of the buffer effect of the cascode transistor M32 and M36 on the P side and on the N side respectively. It enhances the phase margin in a range of 10 and has no design coast. C. Results The design of the opamp has been done with the constraint of using less than 40 A while having a gain bandwidth product greater than 500 kHz for a load of 100 pF and 10 k. Finally, the opamp uses 35 A and has a gain bandwidth product of 708 kHz. III. C ONCLUSION This article has developed the constraints of integrating a multipath frequency compensation network in a general purpose opamp. Furthermore, the result proves the benet and the good performances in terms of gain bandwidth product and current consumption. R EFERENCES
[1] R. Eschauzier and J. Huijsing, Frequency Compensation Techniques for Low-Power Operational Ampliers, ser. The Springer International Series in Engineering and Computer Science. Springer, 1995. [2] P. Fiedorow, D. Subiela, N. Abouchi, and T. Tixier, Nmc vs. rnmc : An experimental study of the two main compensation networks, in NEWCAS Conference, 2010 8th IEEE International, 2010, pp. 285 288. [3] A. D. Grasso, G. Palumbo, and S. Pennisi, Analytical comparison of frequency compensation techniques in three-stage ampliers, International Journal of circuit theory and applications, vol. 36, pp. 53 80, 2008. [4] R. Eschauzier, L. Kerklaan, and J. Huijsing, A 100MHz 100dB operational amplier with multipath nested miller compensation structure, Solid-State Circuits, IEEE Journal of, vol. 27, no. 12, pp. 17091717, Dec 1992. [5] D. Monticelli, A quad cmos single-supply op amp with rail-to-rail output swing, Solid-State Circuits, IEEE Journal of, vol. 21, no. 6, pp. 1026 1034, Dec 1986.

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Fig. 3.

MNMC - Block 3

drawback of this structure is the minimum supply voltage. The circuit needs at least Vssmin = Vgs45 + Vgs47 + Vds46 to be correctly biased. A standard value of the threshold voltage in MOS transistor is around 0.7 V and the drain-source saturation voltage is approximatively 200 mV. Even if M47 and M45 should be in weak inversion, it means that Vssmin is