106 IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-18, NO.

1, FEBRUARY 1983

Impact of Scaling on MOS Analog Performance

STEPHEN WONG AND C. ANDRE T. SALAMA, MEMBER, IEEE

Abstract–A first-order analysis of the impact of scaling on MOS ana- TABLE I

log performance under moderate scrding conditions is presented in this
paper. Aasumirtg a polysilicon gate iort-implanted MOS techitology,
quasi-constant voltage (QCV) scaling is shown to be the optimal scaling
law, offering the best overall analog performance and resulting in an in-
crease in functional density, gain-bandwidth product with a moderate
degradatiotr in gain, and signal-t~noise ratio. The first-order anafysis
agrees fairly well with computer simulation. A typicaf case study shows
that under moderate scaling conditions, CMOS can generally offer a
higher voltage gain when compared to depletion load NMOS and is the
preferred technology for scaJed analog implementations.
I. INTRODUCTION
ITH the ever increasing complexity of very large scale
w integrated circuits, it has become highly desirable to
integrate analog and digital circuits on a single silicon chip.
The primary VLSI focus has been on those technologies which
permit high density integration of analog and digital circuits
on a single chip. The most useful MOS technologies in this
context are FJMOS and CMOS [ 1] .
The increasing complexity of digital MOS VLSI was spurred
by the concept of device scaling [2]. The density of digital cir-
cuits has increased continuously and the area consumed by the
analog portion of a digital-analog circuit has become relatively
larger. This fact has provided a strong impetus for scaling the
analog portion of the circuit as well as the digital one.
The scaling of analog circuits can benefit from the consider-
able amount of information available on the scaling of digital
MOS 1(2’s. Various scaling laws have been proposed and are
summarized in Table I [2] , [3] . The first of these is constant
field (CE) scaling [2] which was introduced as a means of al-
leviating the difficulties arising from two-dimensional parasitic
effects associated with short channels in MOS transistors.
Basically, CE scaling involves a reduction of voltages, currents,
and lateral and vertical dimensions by a factor A afid an in-
crease in the substrate doping concentration by the same fac-
tor A (k > 1). The linear reduction of voltage associated with
CE scaling generally results in a sizeable deterioration of the
signal-t&noise ratio as well as a lack of TTL interface com-
patibilityy. To avaid thi~ difficulty, the current trend is taward~
nonconstant field scaling in the form of constant voltage (CV)
or quasi-constant voltage (QCV) scaling [3]. Constant voltage
scaling implies a fixed nonscaled power supply (compatible
with TTL) and a slower than X (approximately fi) scaling of
gate-oxide thickness to reduce oxide field and improve reli-
Manuscript received December 4, 1981; revised April 23, 1982. This
work was supported by the Natural Sciences and Engineering Research
Councif of Canada.
The authors are with the Department of Electrical Engineering, Uni-
versity of Toronto, Toronto, Ont., Canada MSS 1A4.
SCALING
LAWS
CE QCV Cv
~-l ~-tp
Voltages 1
A k ~-l
Lateral dimensions ~-1/2
Vertical dimensions k;: k~:
Doping concentration L A A
ability and yield. Quasi-constant voltage scaling, ini~hes a
slower than k (taken as m for convenience sake) decrease in
voltage while the other factors scale as in the CE case.
QCV scaling was found to provide optimum drive current
capability in digital VLSI MOS circuits [3]. Although this fac-
tor is an important criterion in digital applications, parameters
such as gain, bandwidth, and signal-to-noise ratio are more suit-
able criteria to evaluate the performance of analog circuits.
One of the objectives of this paper is to investigate the im-
pact of the scaling laws discussed above on MOS analog com-
ponent performance. Only moderate scaling factors are consid-
ered and no attempt is made to approach the ultimate scaling
limits being considered for digital circuits [4]. Present day
MOS analog circuits have minimum channel lengths of about
8 vm. The scaling factors considered here will be limited to
the range A = 1 to X =4. A scaling of h = 4 would reduce the
minimum channel length to 2 #m and the circuit area by ap-
proximately a factor of 16 while still keeping second-order ef-
fects within bounds [5] , [6]. Any further scaling would lead
(as will be seen from the following discussion) to unacceptable
degradation in analog performance. Another objective of this
paper is to establish the optimum technology for scaled ana-
log MOS circuits and to evaluate the performance of a scaled
MOS analog op amp as a typical example of analog circuit
implementation.
Many intricate technology related problems are expected
during device scaling. Presently, innovative processing tech-
niques are being applied to reduce such problems as device
mismatch, junction depth control, and reliability of scaled
down oxide layers. It k neither the aim fior the ~cope of this
paper to suggest solutions to these related problems, but merely
to investigate the effects on analog performance when scaling
is achieved.
II. MOSFET MODELING
MOS analog integrated circuitsl consist for the vast majority
of MOSFET’S used as drivers, active loads for analog switches,
lion-imp~nted silicon gate technology is assumed throughout the
discussion.

0018-9200/83/0200-0106$01 .00 @ 1983 IEEE

WONG AND SALAMA: SCALINCJAND MOS ANALOG PERFORMANCE 107

as well as MOS capacitors, resistors (diffused orpolysilicon), high doping concentration on mobility, respectively. Above
and interconnections. saturation, the parameter 81 is defined as
Since the MOSFET’S are the most critical components in
‘D sat
any analog implementation, the discussion will focus mainly &=l+&~-VT)+~ (5)
on those MOSFET parameters which have a direct influence c

on analog performance. where O is a constant (typically 3 X 10-7 cm/V), EC is the crit-

A. I-V Characteristics
In order to account for second-order effects which may arise
due to scaling, a set of analytical equations must be used.
Modeling of small geometry (short and narrow channel) de-
ical field for velocity saturation (2 X 104 V/cm for NMOS and
2 X 105 V/cm for PMOS), VD,~atis the saturation voltage and
is taken as ( VG - VT)for a first-order analysis. The parameter
8 ~ accounts for impurity scattering effects and is defined as

‘2=(’+:10J”2
vices have been treated extensively by many authors [7] - [10]. (6)
These models generally include the following phenomena: 1)
threshold dependence on two-dimensional charge sharing ef-
The gain constant ~ of the transistor is defined as
fects [11 ], [12], 2) mobility-degradation due to increased
normal and lateral fields [13], and 3) velocity saturation of
(7)
carriers causing premature saturation of current and lower out-
put conductance [14], [15].
where Z is the channel width and 8 ~ accounts for the feedback
When moderate scaling effects are considered, two additional
factors must be considered. These are 1) mobility degradation degradation due to the source resistance R~
due to impurity scattering when the effective substrate doping ?i3 = 1 +~~,(v~ - VT). (8)
exceeds 5 X 1016 cm”3 [16], and 2) gain reduction via feed-
back through the parasitic drain and source resistances. R~ is proportional to the length but inversely proportional to
The saturation region of the MOSFET plays an important the width, depth, and doping of the source junction. The ef-
role in determining analog performance parameters such as fects of the inversion layer capacitance and contact resistance
transconductance, output resistance, and voltage gain. The on /3 are neglected here. These effects are only relevant for
set of equations selected for the analysis are based on a semi- channel lengths below 1.5 pm [6].
empirical model of the MOSFET operation in this particular The saturation current of the device can be expressed as
region of operation.
The threshold voltage VT of the device can be expressed as (9)

v== VTO - AVT8+AVTN (1)

where 8 ~ is a second-order parameter which takes into account
where VTO is the threshold voltage for a large geometry device the body effect on the channel. ti4 is defined as
and A VTsand A VTN are the corrections for short and narrow
channel effects, respectively [7] . VTOis given by ‘-Y
aq=l+ (lo)
2(2@ - v~)l/2
(2) where

where r$&fSis the work function difference between gate and
bulk material, OF is the Fermi potential given by
(3)
where NB is the bulk doping concentration under the channel
and Qss, QB are the oxide and bulk charges, respectively. The
last term in (2) represents the effect of the ion implant used to
adjust the threshold voltage. NiD is the effective implant dose
and D is the implant depth which is assumed to be very shallow.
Mobile carriers in the channel of a scaled MOST normally
experience scattering effects due to the electric fields and in-
creased impurity levels. This leads to a significant degradation
of the channel mobility p which is usually expressed as
(4)
where P. is the zero field mobility and 6 ~, 8 ~ are second-order
parameters describing the degradating effects of high field and
(11)
where es is the dielectric constant of silicon.
The transconductance in the saturation region can be ex-
pressed as
(12)
B. Output Conductance
The output conductance of the device in the saturation re-
gion is critical in determining the voltage gain of inverters as
well as the output impedance of current source. Three impor-
tant phenomena affect the channel conductance of the satu-
rated enhancement mode MOSFET. These are 1) classical
pinchoff [17], 2) velocity saturation [14], [15], and 3) feed-
back caused by drain induced barrier lowering [18], [19].
For moderate channel lengths, the first two phenomena
dominate. The current in the device beyond saturation is
108 IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-18, NO. 1, FEBRUARY 1983

increased by channel length modulation and is given by C. Subthreshold Current

L The exponential dependence of the subthreshold current
ID = ID, sat ~ (13) plays an important role in analog applications. For VG < VT
~nd VD >>-kT/q, the weak inversion current can be expressed
For long channel lengths, AL is the reverse bias depletion as 2
width formed between the drain and the channel and is de-
fined as (22)
AL ‘~1 [~D - ~D,~~~]l/2 (14)
where VOn is the turn on voltage at a surface potential @~=
where
1.5 OF, Cd is the surface depletion region capacitance defined
K, = [2eJqN~]
112. (15) as

As the internal field in a scaled device increases as a result of

(23)
nonconstant field scaling, velocity saturation of mobile carriers,
and the deterioration of the gradual channel approximation
make it necessary to modify the drain depletion length AL as
follows [14] , [15]: and n is given by
1/2
~=l+g
AL=
[( ) EPK~ 2
—
2
+K~(VD - VD,Sat)
1
EPK;
- —
2
(16)
co -
(24)

where EP is the lateral field at the drain during channel pinch- Due to the exponential nature of the subthreshold current, it
off. Out of convenience, EP is usually equated to the critical does not scale linearly with A. A commonly used figure of
field for velocity saturation EC [20] . A more realistic value merit to describe subthreshold behavior is the slope S~ of the
of EP has been derived by Rossel [15] to ensure the con- log ID versus VG curve. S~ can be expressed as
tinuity of current and conductance in the triode and satura-
d log lD,~at q
tion regions. His expression for EP can be approximated by s.= .— (25)
dVG 2.3 nkT”

(17) In an analog switch, for instance, S~ is a significant factor in

determining the on-off current ratio of the device.
For moderate Ep, (16) can be rewritten as (see Appendix I)
D. Noise
AL = K1(VD - VD,,~~)112&5 (18) The noise in MOS devices, working at low frequencies, is
where 6 ~ is a correction factor for channel shortening given by high due to the dominant contribution of l/~ noise [22].
The rms equivalent gate noise voltage, in this case, can be
EPKI expressed as
85=1- (19)
2(VD - v~,,aJ1/2 “

Differentiating (13), using the value of AL given by (18),

yields the output conductance
‘..=($$%1’2
where an is a constant dependent on the interface trap den-
(26)

dID ID,satKl sity at the Si-Si02 interface, Af is the bandwidth and f is

gd~ . — (20)
dVD = ‘2L(VD - vD,m) 112fi6 the frequency.

where 8 ~ is defined as HI. EFFECT OF SCALING ON MOS PARAMETERS

AL 2 In this section, the effect of scaling on the MOS device

66.
()
l. —..—
L“
(21) parameters previously discussed in first investigated.
effect of scaling on MOS circuit components is then dis-
The

From (20), gd~ is proportional to ID,,at, as observed experi-
mentally in moderately scaled devices.
For very short channel lengths, extensive drain induced bar-
rier lowering (DIBL) occurs resulting in a large dependence of
threshold voltage on VD as observed by Masuda [21] . As a
direct consequence of this effect, gd. will be directly propor-
tional to ( VG - VT) and inversely proportional to L 3 (as
shown in Appendix II). This strong dependence of gd~ on L
cannot be tolerated in analog applications and in general the
DIBL regime must be avoided.
cussed. The fact that scaling will limit the accuracy and the
ability to match components is not considered in detail here
since it is technology dependent.
A. Subthreshold Current
In order to avoid large subthreshold currents (and the onset
of substantial DIBL), the long channel index M suggested by
zAS~~~i~g the surface state density at the Si-SiC)2 interface to be
negligible.
WONGAND SALAMA: SCALING AND MOS ANALOG PERFORMANCE 109

Brews etal. [23] can be used. Thisindex isdefinedas TABLE 11

DEVICESCALING
A[(xjto) (WS + w~y] 1/3
M. (27) CE Qcv w Equation
L
~-1 1 ~1/2
where A is a constant and W8, WD are the widths of source ‘D,sat
~1/2
9
1 ~1/2
gm 12
and drain depletion regions, respectively, and are given by ~3/4
gds(enh) 1 A 20
~1/4 ~1/2
1/2 {ds(dep) 1 34
w~ = #
[
(2@~- v’)
1 1/2
(28) cd
El
s;
1 ~-1/4 1 23
25
WD .

[
* (21#~
- v’+ v~)
1 .

For xi, W~, WD, and L inmicrons and toin& the value of A
(29) M‘w 26
27

is 0.41(A)l/3 for n-channel devices. Upon scaling, a value of
M < I will guarantee that long channel subthreshold behavior
is maintained. When M >1 undesirable short channel effects
are expected.
B. Threshold Voltage
For successful scaling, the threshold voltage must scale with
the other voltages. However, due to the nonsalable term
(@mrs+ 2@F) in (2), it is unlikely that VT can be scaled prop-
erly without compensation. In general, scaling of this term
produces a VT which is too large for CE scaling and too small
for QCV scaling. The problem is more critical in the PMOS
case (assuming an n+ polysilicon gate technology), where
(@MS+ 2@F) is more significant. While some adjustment can
be made by varying VB in NMOS technology, this is not pos-
sible in CMOS.
Fortunately, ion implantation can be used in both NMOS
and CMOS to adjust the threshold voltage. In a typical de-
vice which uses a shallow implant as a threshold adjust, it is
common to obtain cancellation between the implant term
and (@MS+ 2@F), whenever necessary3, so that VT becomes
approximately
(30)
(positive sign applies for NMOS while the negative sign applies
for PMOS). If QSS << QB, the above equation will generally
yield the desired threshold voltages.
With (30), proper scaling for VT is easily achieved under the
CV and QCV laws, resulting in a threshold voltage scaled by
=1 and XA-li2, respectively. To ensure that (30) remains
valid, one requires that the condition
(31)
holds under scaling. Since it is desirable that lVj scales with A,
this implies that the implant depth D must scale with A-1/2 in
the CV case, and remain f~ed for QCV and CE scaling. How-
ever, adjustment of D may be necessary to scale VT with I/a
(instead of l/@) under the CE law, and to compensate for
the second-order short channel and narrow width effects.
s For instance, in an n+ polysificon gate p-well CMOS Process, the
PMOSthreshold voltage is adjusted in this manner.
Nevertheless, proper scaling of VT seems feasible using ion im-
plantation and has been assumed in the following discussion.
C First-Order Parameter Scaling
In the model already described, the 8‘s represent second-
order effects which do not scale linearly with A. Their mag-
nitudes are strong functions of the initial unscaled device and
the scaling laws. To obtain a first-order estimate of the effect
of scaling on device parameters as well as to keep the analysis
independent of the unscaled conditions, the parameters 6 are
first assumed to be unity. This implies an ideal long channel
MOSFET as the unscaled device. Justification for this assump-
tion, and a comparison of first-order scaling estimates with
computer simulated results on analog performance, taking into
consideration the effect of ti‘s, are given in Section V.
The first-order scaling for some relevant device parameters
are listed in Table II. Limitations can be expected from the
parameters S$ and Vng, which do not scale-down as desired.
D. Capacitor Scaling
In MOS technology, capacitors are realized between metal
and heavily doped silicon or between two layers of heavily
doped polysilicon. Thermally grown silicon dioxide is used
Scaling of capacitors is straightforward.
as the dielectric.
A direct scale down of the surface area and dielectric thick-
ness lead to a reduction in total capacitance. However, diffi-
culties arise in absolute accuracy and matching of component
values as the effects of misalignment and fringing become rela-
tively more important. Electron quantization noise may also
become a problem as capacitors become smaller.
E. Resistor Scaling
In MOS technology, resistors are fabricated using either dif-
fused layers or polysilicon layers deposited on oxide. The lat-
ter alternative is preferred since it produces minimal parasitic
capacitance. Scaling, again, is relatively simple; however ac-
curacy and matching as well as conduction mechanisms [24]
in the polysilicon become serious limits as the resistors be-
come smaller.
F. Interconnection Scaling
Three items are of prime concern in interconnection scaling.
These are electromigration, in the very thin, narrow aluminum
 110 IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-18, NO. 1, FEBRUARY 1983

conductors, contact resistance in the very shallow junctions, TABLE III

and polysilicon interconnection sheet resistance. For the scal- SCALING
OFANALOG CIRCUITS
ing conditions under consideration here, the first two items do CE Qcv Cv Equation
not present serious constraints. As far as the third item is
concerned, refractory metal silicides, which offer low sheet re- Gain Stages
A V,CMOS 1 ~-1/4 ~-1/2
32
sistance, are a good alternative to polysilicon. In addition, it A V, NMOS 1 ~ 1/4 1 33
is reasonable to expect that, at least some of the longest inter-
Ou Amu
connections will not scale-down at ail, resulting in adverse ef-
fects on parasitic capacitance and line driving capabilities.

IV. EFFECT OF SCALING ON ANALOG

BUILDING BLOCK PERFORMANCE
This section investigates the scaling tendencies of some basic
analog building blocks with the objective of determining the
optimal scaling law for analog applications. Two technologies
are considered: CMOS and NMOS with depletion load. The GBW is normally determined by the second parasitic pole
of the amplifier which can be approximately expressed as
A. Gain Stage Performance
The most useful figure of merit in evaluating performance of (37)
gain stages is the voltage gain. In a CMOS stage, this gain is
given by where gm2 is the effective transconductance of the second
stage, and Cl and C2 are the input (gate) and load capaci-
A ~,CMOS= - gin
(32) tances associated with the second stage [25]. From (36) and
kis,rs + gd.,p) (37), it appears that CC will be proportional to (Cl + C2). If
where gd$ ~ and g&, ~ are the n- and p-channel device output one assumes C2 to be the input (gate) capacitance of the sub-
conductance respectively, as defined by (20). In NMOS tech- sequent stage, and that the overlap gate capacitance is small,
nology, where a depletion device is used as load, the bulk then (Cl + C2), and therefore CC, will be directly proportional
threshold feedback effect normally dominates over channel to xl CO, where A is the active gate area of an individual transis-
length modulation effects in determining gal,, d~~ [X)] . The tor. This implies that the area of CC will scale with A and that
voltage gain, in this case, is given by the ratio of capacitor to op amp areas will remain constant
under scaling.
17m
Av, NMos =-— (33) Signal-to-Noise Ratio (S/N) –From (26), the signal to noise
gals, dep ratio for low-frequency analog applications can be expressed as
where v@/m-
S/N=~a (38)
gd~,dep = 1 ~T,dep I (&D’: V. + 4$7) (34) w to

where the input signal amplitude V~gis assumed to scale with

where VT,d~p is the threshold voltage of the depletion mode other voltages. This implies that the signal-to-noise ratio is
device, VO is the quiescent output voltage, and VDD is the sup- dependent on device geometry.
ply voltage. Slew Rate SR –The slew rate normalized to the supply volt-
age VDD can be used to provide an indication of large signal
B. Op Amp Performance op amp response
Since the operational amplifier is one of the basic building
blocks in analog circuitry, an evaluation of its performance
s~
—= _lD sat
(39)
vj~ v~&~ “
subject to scaling would be useful, For such an analysis, the
following performance indices must be considered. Power DensiW–The power density is a useful figure of merit
Voltage Gain Au–In a typical two-stage op amp which uses a in determining the maximum packing density of op amps per
Miller capacitor for compensation, the voltage gain is unit area.

(35) ID,~t VDD

power density a (40)
ZL “
Unity Gain Bandwidth (GB W)–The unity bandwidth is
mainly determined by the transconductance of the first stage C. Optimum Scaling Law
gm 1, and the compensation capacitor CC and can be expressed The three scaling laws presented in the introduction were
as applied to the first-order scaling of the basic gain stages and
the op amp parameters. The results are listed in Table III.
fJBw . ‘~ (36) Other than an increase in speed resulting from reduction of
cc “ CC, the majority of the analog performance parameters remain
WONG AND SALAMA: SCALING AND MOS ANALOG PERFORMANCE
*? CE b~)
w) 6u?
14 14
12 - 12
b
10
10
08 -
08
06 ~06~06~
1 2
A3
(a)
Fig.1. Effect ofscalingon8’s.
invariant to the application of CE scaling. The exception be-
ing that the signal-to-noise ratio is severely degraded,
Although both nonconstant field scaling laws offer improve-
ments in speed and frequency response, CV scaling appears un-
acceptable for analog applications because it results in the
largest voltage gain degradation, the highest power dissipation
per unit area without a significant gain in signal-to-noise per-
formance. In addition (referririg to (27) and Table II), the
parameter M increases with CV scaling, resulting in short chan-
nel subthreshold effects becoming dominant at low values of L
QCV scaling offers an acceptable compromise, yielding ini-
proved speed and signal-to-noise ratio over the CE case, while
exhibiting a higher gain and lower power dissipation than CV
scaling.
V. CASE STUDY
The scaling amilysis perf~rmed in the previous sections ne-
glected ail second-order effects by assuming an ideal long chan-
nel MOSFET as the unscaled device. This allows simple first-
order scaling factors to be computed without involving the
nonlinear 8 terms. In this section, computer simulation involv-
ing the 8’s is performed using 7 pm channel length MOSFET’S
as the initial unscaled devices. The simulation focuses mainly
on the QCV law in light of the results of the previous section.
These results are compared with the first-order scaling theory
of Tables 11 and HI. Scaling simulation is achieved by manu-
ally scaling all voltages, dimensions, and doping concentrations
in accordance with the QCV law and then inputing them into
a simulation program which accommodates our model. A rep-
resentative case study of such a simulation is presented in the
following paragraphs.
A. Effect of Scaling on the 8 Parameters
As an example, consider a typical n-channel device having
the following initial unscaled characteristics: Z = 70 Mm, L =
7 Mm, to = 800 A,xj = 1.2Vm,NA = 5 X 1015 cm-3, EP =
1.1 X 104 V/cm, V“=5V, (VG - VT)= 1.5V, VB=O, R~=
20$2. In this case the value of M is 0.788, implying that the
device is still in its long channel mode of operation. From
Table II and (27), it is seen that M does not increase for CE or
QCV scaling, but becomes greater than 1 for X >2 ‘in the case
of CV scaling. Using the unscaled device characteristics de-
Ili
Caw
64
A A
(b) (c)
(a)CE. (b) QCV. (c)CV.
fined above, the 8 values for 1= 1 are 81(1)= 1.163, 6,(1)=
1.049, 83(1)=1.008,84(1)= 1.590,85 (1)=0 .855, and66(l]=
0.785. The effect of scaling on the 8(1) parameters were com-
puted and are plotted in Fig. l(a), (b), and (c) for CE, QCV,
and CV scalings. The graphs show that in most cases the
ti(X)/6(1) ratio remains very near unity (i.e., the 8‘s do not
change drastically with scaling). For 83 and 8 ~, this is true
for all three scaling laws, implying that parasitic resistance and
velocity saturation effects are still negligible in the scaling
range under consideration. Under worst case conditions, the
8(h)/8(1 ) factors do not deviate by more than 20 percent from
unity for CE and QCV scaling and by more than 40 percent
for CV scaling. If CV scaling is restricted to k <2 (which as
discussed above is required to prevent the onset of DIBL), the
maximum deviation is 20 percent. These results imply that
the second-order effects described by the 8 terms can be ig-
nored in establishing the general trend of scaling on device pa-
rameters as was done in Sections III and IV. The error caused
by ignoring the 6‘s may sometimes be significant but not
dominant.
B. Gain Stage Simulation
The performance of the NMOS and CMOS gain stages, shown
in Fig. 2, were investigated using computer simulation. To pro-
vide a fair comparison, the two stages were designed to have
identical operating conditions and Z/L ratios. To achieve a
zero quiescent output voltage in the NMOS stage with quiescent
input voltage Vh = VDD/2 (typical operating conditions in a
gain stage), one requires the ratio (Z/L )tiver: (Z/L)lo,d to be
2.8. In the CMOS stage, the same current and aspect ratios
are maintained if Vbti is Set at -0.9 VDD.
Scaling was carried out starting with a set of unscaled de-
vices with characteristics listed in Table IV. The simulated
gain for both gain stages as a function of the scaling factor X,
is shown in Fig. 3. Also shown in the figure are the corre-
sponding gains observed from first-order scaling theory (Table
IV). The maximum discrepancy between simulation and first-
order theory is of the order of 20 percent. The unscaled gain
of the CMOS stage remains higher than that of the NMOS
stage. However, the gain in the NMOS case increases with in-
creasing A while the opposite is true in the CMOS case. The
two gains approach each other at 1 cx 4. The relative increase
112 IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-18, NO. 1, FEBRUARY 1983

PALOAD
[
i’LOAD VT,

VT, dep
VIN

VBM

( Z/L
enh

)DRIVER
0.2 Vn.
‘0.7

0.5
-0.9

2.8
V.rr

VDD

vm

( Z/L) LOAD 1

VDD(A=I) 5V

(a) (b) (c)

Fig. 2. Gain stages. (a) CMOS. (b) NMOS with depletion load. (c)
Specifications.

TABLE IV
NMOS AND CMOS UNSCALED
DEVICECHARACTERISTICS
NMOS Stage CMOS Stage v~,/&
Driver Load Driver Load

Type Enhancement Depletion n-channel p-channel

VT~) 1 -3.5a 1 -la
1.5 x 1015
‘d
Ndcm-3) 5 x 1015 5 x 10*5 5 x 1015
&;m2/V’. s) 600 600 600 300
EC(V/cm) 2 x 104 2 x 104 2 x 104 2 x 105
Xj(/.lnl) 1.2 1.2 2.2 1.2 rWr4

L(pm) 7 7 ‘1 7
..
‘VDD
aThreshold voltages adjusted by means of shallow implants.

(a)

‘V(d’)i--- I z(w) L(Pm)

24
CMOS
Ml 100 7

22
M2 100 7

20
M3 100 7
18
M4 100 7
16
M5 400 7
14
M6 400 5
12 rw17 100 7
— COMPUTER SlhlULATION

10 ---- ls’ ORDER THEORY M8 200 7

1
s~ A M9 100 7

%D 5V
Fig. 3. lnverter voltage gain as a function of L
[BIAS 2V

in the gain of the NMOS stage can be attributed to the fact cc 10pF
that gd~,~eP due to body effect increases at a slower rate (A1/4 )
than that due to channel length modulation (X3/4). However,
this cannot be regarded as an advantage, since the latter mecha- Fig. 4. CMOS operational amplifier. (a) Circuit diagram. (b) Unscaled
specifications.
nism present in the depletion NMOS would eventually over-
take that due to body effect. From the above results, it ap-
pears that in the low k (X < 4) range, the CMOS stage can of- C. Op Amp Simulation
fer a higher gain than that of its NMOS equivalent. This result In light of the conclusion that, in general, scaled CMOS of-
is not specific to the particular set of device parameters fers a gain advantage over scaled NMOS gain stages, a CMOS
chosen, but was found to be true in the majority of the cases op amp was selected for simulation. The unscaled op amp and
investigated. its imuortant lavout characteristics are shown in Fig. 4. The
WONG AND SALAMA: SCALING AND MOS ANALOG PERFORMANCE 113

TABLE V
SCALINGRESULTSOFOP AMP

Voltage Gain Av GBW (MHz) Power Dissipation (mW) Rout (kQ)

First-Order First-Order First-Order First-Order

Simulation Theory Simulation Theory Simulation Theory Simulation Theory

1 903 903 5 5 16.1 16.1 28 28

2 589 639 12.6 14.1 11.3 11.4 15.7 16.6
4 357 452 31.6 40 8.3 8.2 8.7 9.9
~-1/2 ~3/2 ~-1/2 ~3/4
ScalingFactor

circuit configuration is typical of op amps presently used in If x is small, implying a moderate EP,(A2) can be simplified to
telecommunication applications. It consists of two gain stages
X2
with a total gain of about 60 dB. A buffer stage is used in AL =KI(VD - VD,at)l/2
1 ‘X+7 . (A3)
the feedback compensation loop to eliminate an undesirable ()
zero at gm /CC [25]. The op amp has a useful feature asso- Differentiating (A3) yields
ciated with the fact that all the transistor channel lengths are
8AL _ ~ KI l-x+x;
nearly equal which guarantees equal Jj. for all the transistors,
even under scaled conditions. ti
v~ 2 (VD - v~mt)l/2 ()
Table V lists the results of the simulation as a function of A.
Also shown in the table are the results obtained from first- +Kl(~D - bsat)112(x- l)—
6 VD
order scaling theory. Agreement between the simulation and
first-order theory appears reasonable, confirming the validity =—1
of using the first-order theory to estimate trends in amilog 2 (VD - ‘1
J’--sat) 112 l-x+~+x}
scaling.
=_1 KI
l-x; . (A4)
VI. CONCLUSION 2 (VD - v~wt)liz {}
A theoretical analysis of the impact of scaling on analog com- Substituting (A3) and (A4) into
ponent and circuit performance has been presented. Among
‘D, sat _6AL
the three scaling laws considered, QCV appears to be the opti- gds = (A5)
AL 2 tiVD
mum for analog scaling. Its application results in small area, L1-7
high speed and moderate degradation in gain, power density, ()
and signal-to-noise ratio. The selection of QCV is compatible and neglecting all X2 terms yields
with Chatterjee’s [3] choice of the same scaling law for digi-
tal applications. Thus it appears feasible to scale both the ID,satK~
analog and digital portions of a circuit using the same scaling ‘ds = 2L(VD- VDWt)li2
[1 - KI (VD- VDWt)112
(1 - x)] 2
law.
(A6)
A typical case study comparing the performance of NMOS
and CMOS gain stages under moderate scaling conditions shows which is (20). Note also that by neglecting X2, (A3) becomes
that CMOS offers the optimum gain configuration for scaled equivalent to (18).
analog implementations. A comparison between computer
simulation (of gain stages and a CMOS op amp) and first-order APPENDIX II
scaling theory shows that second-order effects produce signifi- Consider the ideal current equation
cant but nondominant errors in ewduating the performance of
analog components under scaled conditions. Thus, first-order (Bl)
theory can be used to estimate scaling tendencies in analog
applications.
When DIBL is present, the threshold voltage VT is a function
of VD~, accotding to Masuda [21], the dependence is
APPENDIX I
VT= v~o - q(vDJ - +) (B2)
Considering (16), if one lets
where
EPKI
~. (Al)
2(VD- V&#’ (B3)
this equation becomes
J+., q., and @ are constants dependent on the technology.
AL = KI(VD- vD@)lt2{(1 +x’) ’/2 - x}. (A2) By substituting VT into (Bl) and differentiating with respect
114 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-I 8, NO. 1, FEBRUARY 1983
to VDs, one obtains
(B4)
Therefore, as L becomes smaller, this effect will become a
dominant factor in determining gd$.
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Stephen L. Wong was born in Singapore on
June 25, 1957. He received the B.A.SC. degree
in Engineering Science fiqm the University of
Toronto, Toronto, Ont., Canada, in 1980, where
he is now finishing the requirements for the
M.A.SC. degree in electrical engineering.
Since 1979 he has been concerned with the
modeling and design of CM(X3analog circuits,
particularly the effects of scaling for VLSI
applications.
C. Andre T. Salama (S’60-M’66) received the
B.A.SC., M.A.SC., and Ph.D. degrees, all in elec-
trical engineering, from the Univemity of British
Columbia, Vancouver, B.C., in 1961, 1962, and
1966, respectively.
From 1962 to 1963, he served as a Research
Assistant W the University of California, Berke-
ley. From 1966 to 1967 he was employed at
Bell Northern Research, Ottawa, Ont., Canada,
as a member of the scientific staff working in
the area of integrated circuit design. Since
1967 he has been on the staff of the Debarment of Electrical Engineer-
ing, University of Toronto, Toronto, ‘Ont., Canada, where he ;S cur-
rently a Professor. For the 1975-1975 term, he was a Visiting Professor
at the Katholieke Universiteit, Leuven, Belgium. He has served as a
Consultant in the integrated circuits industry. His research interests
include the design and fabrication of semiconductor devices and inte-
grated circuits.
Dr. Salama is a member of the Association of Professional Engineers
of Ontario and the Electrochemical Society.