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Lecture
Dr. Shoab Khan
Though Verilog is C like in syntax but has distinct character and interpretation. A programmer must set his perception right before coding in Verilog. He must visualize hardware in his mind while structuring Verilog modules consisting of procedural blocks and assignments.
Design Specification
H/W
S/W
Functional Verification
Synthesis
System Integration
Lay Out
Design Component
Clk
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History
Invented by Philip Moorby in 1983/1984 at Gateway Design Automation Enables specification of a digital system at a range of levels of abstraction: switches, gates, RTL, and higher Verilog-based synthesis tool introduced by Synopsys in 1987 Verilog placed in public domain to compete with VHDL Open Verilog International (OVI) IEEE 1364
Modules
The Module Concept The module is the basic building block in Verilog Modules are:
Declared Instantiated
Hierarchical Design
Verilog code contains a top-level module and zero or more instantiated modules The top-level module is not instantiated anywhere Several copies of a lower-level module may exist Each copy stores its own values of regs/wires Ports are used for interconnections to instantiated modules Order of ports on first line of module definition determine order for connections of instantiated module Order of listing inputs, outputs, and inouts on the following lines is not important
AND a0(i0, i1, temp); endmodule AND a1( i2, temp, o); endmodule i0 i1 i2 0 temp
Logic Values
0: zero, logic low, false, ground 1: one, logic high, power X: unknown Z: high impedance, unconnected, tri-state
Data Types
Nets Nets are physical connections between components Nets always show the logic value of the driving components Many types of nets, we use wire in RTL Registers Implicit storage unless variable of this type is modified it retains previously assigned value Does not necessarily imply a hardware register Register type is denoted by reg
Variable Declaration
Declaring a net wire [<range>] <net_name> [<net_name>*]; Range is specified as [MSb:LSb]. Default is one bit wide Declaring a register reg [<range>] <reg_name> [<reg_name>*]; Declaring memory reg [<range>] <memory_name> [<start_addr> : <end_addr>]; Examples reg r; // 1-bit reg variable wire w1, w2; // 2 1-bit wire variable reg [7:0] vreg; // 8-bit register reg [7:0] memory [0:1023]; //a 1 KB memory
Constants
decimal (default) 13, d13 binary 4b1101 octal 4o15 hexadecimal 4hd
Levels of Abstractions
Switch Level: The lowest level of abstraction is the switch or transistor Level Modeling. Gate Level: Synthesis tools compile high level code and generate code at gate level. Dataflow Level: The level of abstraction higher than the gate level. Behavioral Level: In more complex digital designs, priority is given to the performance and behavior algorithm.
Example
module mux(out, in1, in2, sel); output out; input wire and or not in1, in2, sel; out1, out2, sel_n; #5 a1(out1, in1, sel_n), a2(out2, in2, sel); #5 o1(out, out1, out2); n1(sel_n, sel);
in1
out1
endmodule
sel out2 out
in2
Dataflow Modeling
Expressions, operands and operators form the basis of dataflow modeling.
Verilog Operators
Arithmetic: +, = , *, /, % Binary bitwise: ~, &, |, ^, ~^ Unary reduction: &, ~&, |, ~|, ^, ~^ Logical: !, &&, ||, ==, ===, !=, !== == returns x if any of the input bits is x or z === compares xs and zs Relational: <. >, <=, >+ Logical shift: >>, << Conditional: ?: Concatenation: {}
Arithmetic Operators
Operator Type Arithmetic * / + % Operator Symbol Operation performed Multiply Divide Add Subtract Modulus
Conditional Operators
Operator Symbol ?:
Concatenation Replication
{ } {{}}
Concatenation Replication
Logical
! && ||
MSB
Tied to
LSB
13 bits
Replication Operator!
Arithmetic Operators
Operator Type Operator Symbol Operation performed Right Shift Left Shift Greater than Less than Greater than or equal Less than or equal
Shift
>> <<
Relational
Reduction Operators
Operator Symbol
Operation performed Reduction and Reduction nand Reduction or Reduction nor Reduction xor Reduction xnor
^~ or ~^
Equality Operators
endmodule
module mux2_1(in1, in2, sel, out); input in1, in2, sel; output out;
module stimulus; reg IN1, IN2, SEL; wire OUT; mux2_1 MUX(IN1, IN2, SEL, OUT);
initial begin
endmodule
IN1 = 1; IN2 = 0; SEL = 0; #5 #5 end initial $monitor($time, ": IN1=%b, IN2=%b, SEL=%b, OUT=%b\n", IN1, IN2, SEL, OUT); endmodule SEL = 1; IN1 = 0;
Behavioral Modeling
High level language constructs are used for loop if else while etc All statements come in a procedural block Two types of procedural blocks always initial A subset of constructs are synthesizable and called RTL Verilog
initial Block
This block starts with initial keyword This is non synthesizable Non RTL This block is used only in stimulus All initial blocks execute concurrently in arbitrary order They execute until they come to a #delay operator Then they suspend, putting themselves in the event list delay time units in the future At delay units, they resume executing where they left off.
Procedural assignments
Blocking assignment = Regular assignment inside procedural block Assignment takes place immediately LHS must be a register
always begin A=B B=A end A=B, B=B
Procedural assignments
Nonblocking assignment <= Compute RHS Assignment takes place at end of block LHS must be a register
always begin A <= B B <= A end Swap A and B
# Time Control
$time A built-in variable that represents simulated time a unitless integer $display($time, a=%d, a); # Time Control #<number> statement statement is not executed until <number> time units have passed control is released so that other processes can execute used in test code used to model propagation delay in combinational logic
# Time Control
Delay parameter for a built-in logic gate wire c; xor #2 x2(c, a, b);
@ Time Control
@(expression) @(expression or expression or ) @(posedge onebit) @(negedge onebit) do not execute statement until event occurs @(clk) is same as @(posedge clk or negedge clk)
@ Time Control
Used to model combinational logic behaviorally always @ (a or b) c = a^b; Every gate input must be included in the sensitivity list Used to model synchronous registers always @(posedge clk) if (load) dout <= din;
In feedback registers, if we dont reset the feedback register at a proper time, we keep getting x.
Is resetting necessary!!
In feed forward registers we dont need to reset, as x gets flushed out in few cycles.
// resetting inside the module always @ (posedge clk or negedge rst_n) begin If (! rst_n) // If rst_n=0 reg a <= 4b0; else a_reg <= a; end
acc.v
Veriwell.exe
module mux4_1(in1, in2, in3, in4, sel, out); input [1:0] sel; input [15:0] in1, in2, in3, in3; output [15:0] out; reg [15:0] out; always @(in1 or in2 or in3 or in4 or sel) case (sel) 2'b00: out = in1; 2'b01: out = in2; 2'b10: out = in3; 2'b11: out = in4; default: out = 16'bx; endcase endmodule
Conditional statements
If, If-else
case
Could also use casez (treats z as dont cares ) and casex ( treats z and x as dont cares)
Loop Statements
Repeat
While
For
Macros
Preprocessing commands
`ifdef DIFFERENCE $display (defined); `endif
Include File
Example: Accumulator
cloud x
A 4-bit register
a
clk rst_n
Feed back
module test;
module acc(a, clk, rst_n, acc_out); input [3:0] a; input clk, rst_n; output [7:0] acc_out; reg [7:0] acc_out; reg [7:0] sum;
reg [3:0] A; reg CLK, RST_N; wire [7:0] ACC_OUT; integer i; acc ACC0(A, CLK, RST_N, ACC_OUT); initial begin #5 RST_N = 0; #2 RST_N = 1; end
always @(a or acc_out) sum = a + acc_out; always @(posedge clk or negedge rst_n) begin if(!rst_n) acc_out <= 0; else acc_out <= sum; end endmodule
initial begin #5 A = 1; for(i=0; i<10; i=i+1) #20 A = A + 1; end always #10 CLK = ~CLK; initial $monitor($time, " A=%d, sum=%d, ACC_OUT=%d", A, ACC0.sum, ACC_OUT); initial $vw_dumpvars; initial begin #60 end endmodule $stop;
Timing Diagram!
10 time units
Start
10 time units
X
reg a
X X
0
valid
valid
We get a valid value after the register is reset!
Test Vectors
simulator
RTL
TRUE
COMPARISON
Verilog Testbench
A testbench facilitates verification of a design or module by providing test vectors and comparing the response to the expected response The design (top- evel module) or (lower-level) module is instantiated inside the testbench, and behavioral statements are used to apply test vectors and evaluate the response Constructs that are not synthesizable can be used
Parameter
Parameters are not variables they are constants Parameter declaration examples parameter size = 8; // defines size as a constant with value 8
Verification Environment
Simulators
Differences Highlighted
Software Debugger
Verification Window
SoC
Interrupt Flags
Interrupt Flags are fired by Monitors embedded in the Wrapper on FPGA