Print 4 Pran

Rajagiri School of Engineering &
Technology, Kakkanad
INDEX
NO CONTENTS PAGE NO
1 INTRODUCTION 2
2 INTERFACING OF ANALOG TO DIGITAL CONVERTER 3
WITH MICROCONTROLLER
3 INTRODUCTION TO SERIAL COMMUNICATION 8
4 MICRO-CONTROLLER ARCHITECTURE 14
5 INTERFACING AN LCD TO THE AT89C51 34
6 SENSOR INTERFACING 38
7 POWER SUPPLY DESIGN 40
8 PROGRAMMING SECTION 41
9 PCB DESIGN 45
10 SERIAL COMMUNICATION PC-MICROCONTROLLER 46
Uni.Reg.No : 26034 –1–

CHAPTER 1:
INTRODUCTION
The project, titled PC BASED DATA ACQUISITION SYSTEM, aims at
developing an indigenous data acquisition system, of which the hardware part of the
whole project is our immediate concern. The literal meaning of a data acquisition system
is to acquire data, to process it and display it. The hardware section, which deals with the
acquiring and displaying of the data, makes use of a Sensor, Analog to Digital converter,
Micro Controller and a LCD display.
The sensor senses the physical parameter in terms of a measurable electrical
parameter. This electrical signal is then provided to an ADC which converts the analog
signal to an equivalent digital signal which is provided to the micro controller. The micro
controller transmits the data serially to another micro controller (remote station) which
then displays the data on LCD (16 x 2 ) display.
Parallel
Serial
ADC804 Microcontroller
8051 PC
Uni.Reg.No : 26034 –2–

CHAPTER 2:
2.1 INTERFACING OF ADC WITH MICROCONTROLLER
OBJECTIVE:
Our project is ‘PC BASED DATA ACQUISITION’. As a part of this
project, our main aim is to implement the hardware section of this module. The hardware
section consists of the sensors, ADC, micro controllers.
2.1.1 BRIEF DESCRIPTION OF THE COMPONENTS:

In data acquisition module, to acquire a physical parameter a sensor is
required(for instance if the parameter is temperature then LM35 can be used as the
sensor). Digital computers use binary (discrete) value but in physical world everything is
analog, so to convert the analog to digital value ADC is used. This project uses the ADC
MCP3201.But for our demonstration we have used ADC804.The micro controller used
was 89C51. In our project an ADC is interfaced with the 89C51 and it is serially
communicated to another 89C51.
Parallel
Serial
ADC804 Microcontroller Microcontroller
8051 8051
LCD
Display /
DAC
Fig 1: Block schematic of hardware section
Uni.Reg.No : 26034 –3–

CIRCUIT COMPONENTS:
1. Controlling section
2. Analog to digital converter
3. Display Section
4. Sensors
5. Light emitting diodes
6. Power Supply
2.2 ANALOG TO DIGITAL CONVERTER (ADC):
An ADC is used to translate the analog signals to digital number so that
micro controller can read them. A widely used ADC chip is ADC804.
2.2.1 ADC804:
The ADC804 IC is an analog-to-digital converter in the family of ADC800
series from National Semiconductor. It works with +5 volts and has a resolution of 8bits.
Conversion time is another major factor in judging an ADC. It can be defined as the time
taken by the ADC to convert the analog to digital value. In the ADC804, the conversion
time varies depending on the clocking signals applied to the CLK R and CLK IN pins, it
cannot be faster than 110 microseconds.
Vcc
Vin+ D0
Vin- D1
A GND D2
Vref/2 D3
CLk R D4
CLK IN D5
CS D6
RD D7
D GND WR
INTR
ADC 804 Pin Out
Uni.Reg.No : 26034 –4–

Fig 2: Interfacing of ADC804 with AT89C51
2.2.2 PIN DESCRIPTION:
CS:
Chip select is an active low input used to activate the ADC chip.
RD(READ):
This is an input signal and is active low. The ADC converts the analog input to
its binary equivalent and holds it in an internal register. RD is used to get the converted
data out of the ADC chip.
WR(WRITE):
This is an active low input used to inform the ADC804 to start the conversion.
The ADC804 starts conversion only when WR makes a low to high transition.
Uni.Reg.No : 26034 –5–

CLK IN and CLK R:

CLK IN is an input pin connected to an external clock source when an
external clock is used for timing. The 804 is having an internal clock generator. To use it
the CLK IN and CLK R pins are connected to a capacitor and a resistor.
F = 1/(1.1RC)
For conversion time to be 110 microseconds typical values of R and C are 10
kohms and 150 pF respectively.
INTR(INTERRUPT):
This is an output pin and is active low. It is a normally high pin when the
conversion is finished, it goes low to signal the CPU that the converted data is ready to be
picked up.
Vin(+) and Vin(-) :

These are the different analog inputs where Vin=Vin (+)- Vin(-)
The Vin(-) pin is grounded and the Vin(+) pin is used as the analog input to be converted
to digital.
Vcc:
This is the +5v power supply. It is also used as a reference voltage when the Vref/2
input is open.
Vref/2:
It is an input voltage used for the reference voltage. If this pin is not connected
,the analog input voltage for the ADC804 is in the range of 0 to 5v(same as that of Vcc
supply). Vref/2 is used to implement analog input voltages other than 0-5v. For instances
if the analog input range needs to be 0-4V, Vref/2is connected to 2V.
Uni.Reg.No : 26034 –6–

D0-D7:
D0-D7(where D7 is the MSB , D0 is the LSB).are the digital data output pins.
These are tri-state buffered and the converted data is accessed only when CS=0 and RD is
forced low.
Dout= Vin/(step size)
Dout=digital data output (in decimal)
Vin= analog input voltage
Step size=(resolution) it is the smallest change, which is ( 2*Vref/2)/256 for an 8-bit
ADC.
ANALOG GROUND and DIGITAL GROUND

These are the input pins providing the ground for both the analog signal and
digital signal. Analog ground is connected to the ground of the analog Vin while digital
ground is connected to the ground of the Vcc pin. The reason for the two ground pin is to
isolate the analog Vin signal from transient voltage caused by digital switching of output
D0-D7. In our project both are connected to the same ground.
Uni.Reg.No : 26034 –7–

CAPTER: 3
INTRODUCTION TO SERIAL COMMUNICATION
All IBM PC and compatible computers are typically equipped with two serial ports
and one parallel port. Although these two types of ports are used for communicating with
external devices, they work in different ways. A parallel port sends and receives data
eight bits at a time over 8 separate wires. This allows data to be transferred very quickly;
however, the cable required is more bulky because of the number of individual wires it
must contain. Parallel ports are typically used to connect a PC to a printer and are rarely
used for much else. A serial port sends and receives data one bit at a time over one wire.
While it takes eight times as long to transfer each byte of data this way, only a few wires
are required. In fact, two-way (full duplex) communications is possible with only three
separate wires - one to send, one to receive, and a common signal ground wire.
3.1 Advantages of Serial Communication
 Serial Cables can be longer than Parallel cables. The serial port transmits a '1' as -3 to
-25 volts and a '0' as +3 to +25 volts where as a parallel port transmits a '0' as 0v and a
'1' as 5v. Therefore the serial port can have a maximum swing of 50V compared to the
parallel port which has a maximum swing of 5 Volts. Therefore cable loss is not going
to be as much of a problem for serial cables than they are for parallel.
 You don't need as many wires than parallel transmission. If your device needs to be
mounted a far distance away from the computer then 3 core cable (Null Modem
Configuration) is going to be a lot cheaper that running 19 or 25 core cable. However
you must take into account the cost of the interfacing at each end.
 Infra Red devices have proven quite popular recently. You may of seen many
electronic diaries and palmtop computers which have infra red capabilities build in.
However could you imagine transmitting 8 bits of data at the one time across the
Uni.Reg.No : 26034 –8–

room and being able to (from the devices point of view) decipher which bits are
which? Therefore serial transmission is used where one bit is sent at a time. IrDA-1
(The first infra red specifications) was capable of 115.2k baud and was interfaced into
a UART. The pulse length however was cut down to 3/16th of a RS232 bit length to
conserve power considering these devices are mainly used on diaries, laptops and
palmtops.
 Microcontroller's have also proven to be quite popular recently. Many of these have in
built SCI (Serial Communications Interfaces) which can be used to talk to the outside
world. Serial Communication reduces the pin count of these MPU's. Only two pins
are commonly used, Transmit Data (TXD) and Receive Data (RXD) compared with
at least 8 pins if you use a 8 bit Parallel method (You may also require a Strobe).
3.2 Basics of Serial Communication

Computers transfers data in two ways: parallel and serial .In parallel data
transfers, often 8 or more lines are used to transfer data to a device that is only a few feet
away. Examples of parallel transfers are printers and hard disks; each uses cables with
many wire strips. Although in such cases a lot of data can be transferred in a short amount
of time by using many wires parallel, the distance can not be great. To transfer to a device
located many metes away, the serial method is used. In serial communication, the data is
sent a byte or more at a time. The 8051 serial communication capability built in to it,
there by making possible fast data transfers using only few wires.
When a microprocessor communicates with the outside world, it provides the data
in byte –sized chunks. In some cases, such as printers, the information is simply grabbed
from the 8 bit data bus and presented to the 8-bit data bus of the printer. This can work
only if the cable is not too long, since long cables diminish and even distorts signals.
Furthermore, an 8-bit data path is expensive. For these reasons, serial communication is
used for transferring data between two systems located at distances of hundreds of feet to
millions of miles apart.
The fact that in serial communication a single data line is used instead of the 8-bit
data lines of parallel communication makes it not only much cheaper but also makes it
Uni.Reg.No : 26034 –9–

possible for two computers located in two different cities to communicate over the
telephone.
For serial data communication to work, the byte of data must be concerned to
serial bits using a parallel –in-serial-out shift register; then it can be transmitted over a
single data line. This also means that at receiving end there must be a serial-in-parallel-
out shift register to receive the serial data and pack them into a byte. Of course, if the data
is to be transferred on the telephone line, it must be converted from 0s and 1s to audio
tones, which are sinusoidal-shaped signals. This conversion is performed by a peripheral
device called modem, which stands for “modulator/demodulator”.
When the distance is short, the digital signal can be transferred as it is on a simple
wire and requires no modulation. This is how IBM pc keyboards transfer data to the
motherboard. However , for long distance data transfers using communication lines such
as telephone, serial data communication requires a modem to modulate (convert from 0s
and 1s to audio tones)and demodulate(converting from audio tones to 0s and 1s).
Serial data communication uses two methods, asynchronous and synchronous.
The synchronous method transfers a block of data(characters) at a time while the
asynchronous transfers a single byte at a time. It is possible to write software to use either
of these methods, but the program cans be tedious and long. For this reason , there are
special IC chips are commonly referred to as UART(universal asynchronous receiver-
transmitter) and USART(universal synchronous-asynchronous receiver-transmitter)
3.2.1 Half-and full-duplex transmission

In data transmission if the data can be transmitted and received, it is a duplex
transmission. This is in contrast to simplex transmission such as with printers, in which
the computer only sends data. Duplex transmission can be half or full duplex, depending
on whether or not the data transfer can be simultaneous. If data is transmitted one way at
a time, it is referred to as half duplex. If the data can go both ways at the same time, it is
full duplex. Of course, full-duplex requires two wire conductors for the data lines (in
addition to the signal ground), one for transmission and one for reception, in order to
transfer and receive data seriously.
Uni.Reg.No : 26034 – 10 –
3.2.2 Asynchronous serial communication and data framing

The data coming in at the receiving end of the data line in serial data transfer is all
0s and 1s;it is difficult to make sense of the data unless the sender and receiver agree on a
set of rules, a protocol, on how the data is packed, how many bits constitute a character
and when the data begins and ends.
Start and stop bits:

Asynchronous serial data communication is widely used for character-oriented
transmissions, while block-oriented data transfers use the synchronous method. In the
asynchronous method, each character is placed in between start and stop bits. This is
called framing. In data framing for asynchronous communications, the data, such as
ASCII characters, are packed in between a start bit and stop bit. The start bit is always a 0
(low) and the stop bit is 1 (high).
In asynchronous serial communication, peripheral chips and modems can be

programmed for data that is 7 or 8 bits wide. This is in addition to the number of stop
bits, 1 or 2.While in older systems ASCII characters were 7-bit,in recent years due to the
extended ASCII characters, 8-bit data has become a common. In some older systems,
due to the slowness of receiving mechanical device two stop bits were used to give the
device sufficient time in to organize itself before transmission of the next byte. However,
in modern PCs the use of one stop bits standard. Assuming that we are transferring a text
file of ASCII characters using 1 stop bit, we have a total of 10 bits for each character. 8
bits for the ASCII code, and 1 bit each for the start and start and stop bits. Therefore, for
each eight bit character there are an extra 2 bits, which gives 25% overhead.
3.2.3 Synchronous Communication

1. Clock bit is transmitted from one device to another. The clock signal is a pulse stream
of logic high and low level at a fixed frequency.
Uni.Reg.No : 26034 – 11 –
2. Data bits are transmitted /received with reference to the edges of the clock signal.
3. All data transfer is thus synchronized to this clock. Typical examples include Serial
Programming Interface(SPI) and (Inter Integrated communications(I2C))
4. High speed of data communications possible. Typically > 1 M bit/second.
The clock signals is the control signal whose edges are used to shift data serially in both
directions between one device to another. The rising edges of the clock signal is used to
shift data from the first device to the second device one bit at a time. Similarly the falling
edge of the clock signal is used to shift the data from the second device to the first device
one bit at a time.
The data transmitted from the first device to the second device take a finite time delay
from the rising edge of the clock pulse. The finite time delay is used to the physical
delays in the gates and other circuitry used. The data shifted in to the first device from the
second device is on the falling edge of the clock. Here again the data has to be stable a
finite amount of time before and after the falling edge of the clock pulse. The finite time
before the corresponding edge is called the setup delay. This delay is required for the data
to stabilize before the clock edge occurs. Similarly the data has to be valid a finite
amount of time after the clock edge. This is again to ensure data validity. In addition to
this, manufactures of devices specify timings on the rate of rise, rate of fall, clock ON –
time, clock- OFF-time, clock frequency and much more.
Certain synchronous protocol formats are designed in such a way that the bi-
directional transfers happen simultaneously on the rising edge of the clock signal.
In some systems in order to maintain data integrity, the parity bit of the character
byte is included in the data frame. This means that for each character (7-or 7-bit,
depending on the system) we have a single parity bit in addition to start and stop bits. The
parity bit is odd ,or even. In the case of an odd parity bit the number of data bits,
including the parity bit, has an odd number of ones. Similarly, in an even parity bit
system the total number of bits, including the parity bit, is even.
Uni.Reg.No : 26034 – 12 –
3.3 Data transfer rate

The data transfer in serial communication is stated in bps (bits per
second).Another widely used terminology for bps is baud rate. However, the baud and
bps rates are not necessarily equal. This is due to the fact that the baud rate is the modern
terminology and is defined as the number of signals changes per second. In modems,
there are occasions when a single change of signal transfers several bits of data. As far as
the conductor wire is concerned, the baud rate and the bps are the same.
The data transfer rate of a given computer system depends on communication
ports incorporated into that system.
3.4 Parallel Communication

1. Data transfer rate of 8 bit width require a minimum of 8 data lines plus one
ground reference. Data transfer of 32 bit width will require 32 lines plus one
ground.
2. Additional control lines for direction control may be needed.
3. This is a fast method of data transfer used for short distances only since the costs
of wiring are high.
4. Applications include communications of PC with printers and hard disks.
Uni.Reg.No : 26034 – 13 –
CHAPTER 4:
MICRO-CONTROLLER ARCHITECTURE
The Atmel 89C51 forms the main processing unit of the board. AT89C51 is a 40
pin IC and has 4 Ports P0 to P3 and has an 8 bit architecture.
4.1 89C51 MICROCONTROLLER HARDWARE
Uni.Reg.No : 26034 – 14 –
Fig 3:AT89C51 Micro controller Hardware
The 8051 architecture consists of these specific features:
 Eight bit CPU with registers A (accumulator) and B

 Sixteen bit program counter and data pointer (DPTR)
 Eight bit program status word
 Eight stack pointer
 Internal ROM or EPROM (8751) of 0(8031) to 4k(8051)
 Internal RAM of 128 bytes: Four register banks each contain eight registers
 Sixteen bytes, which may be addressed at the bit level
 Eighty bytes of general purpose data memory
 Thirty two input/output pins arranged four eight bit ports: p0-p3
 Two sixteen bit timer/counters: t0-t1
 Full duplex serial data receiver/transmitter: SBUF
 Control registers: TCON, TMOD, SCON, PCON, IP and IE
 Two external three internal interrupt sources Oscillator and clock circuits
4.2 Special Function Registers
Uni.Reg.No : 26034 – 15 –
A map of the on-chip memory area called the Special Function Register
(SFR) space is shown in Figure 2. Note that in the SFR s not all of the addresses are
occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these
addresses will in general return random data, and write accesses will have no effect. User
software should not write 1s to these unimplemented locations, since they may be used in
other 80C51 Family derivative products to invoke new features. The functions of the SFR
s are described in the text that follows.
Accumulator :
ACC is the Accumulator register, it is generally used for temporary storage
with in the CPU, simply referred as A..
B Register:
The B register is used during multiply and divide operations. For other
instructions it can be treated as another scratch pad register.
Program Status Word:

The PSW register contains program status information
Stack Pointer:
Uni.Reg.No : 26034 – 16 –
The Stack Pointer register is 8 bits wide. It is incremented before data is
stored during PUSH and CALL executions. While the stack may reside anywhere in on-
chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to
begin at locations 08H.
Data Pointer:
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte
(DPL). Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit
register or as two independent 8-bit registers.
Ports 1 & 3:
P1 and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively. Writing a
one to a bit of a port SFR (P0, P1, P2, or P3) causes the corresponding port output pin to
switch high. Writing a zero causes the port output pin to switch low. When used as an
input, the external state of a port pin will be held in the port SFR (i.e., if the external state
of a pin is low, the corresponding port SFR bit will contain a 0; if it is high, the bit will
contain a 1).
Serial Data Buffer:

The Serial Buffer is actually two separate registers, a transmit buffer and a
receive buffer. When data is moved to SBUF, it goes to the transmit buffer and is held for
serial transmission. (Moving a byte to SBUF is what initiates the transmission.) When
data is moved from SBUF, it comes from the receive buffer.
Timer Registers Basic to 80C51:

Register pairs (TH0, TL0), and (TH1, TL1) are the 16-bit Counting registers
for Timer/Counters 0 and 1, respectively. Control Register for the 80C51
Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON
Uni.Reg.No : 26034 – 17 –
Contain control and status bits for the interrupt system, the Timer/Counters,
and the serial port. They are described in later sections.
4.3 Port Structures and Operation
All four ports in the 80C51 are bidirectional. Each consists of a latch
(Special Function Registers P0 through P3), an output driver, and an input buffer. The
output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to
external memory. In this application, Port 0 outputs the low byte of the external memory
address, time-multiplexed with the byte being written or read. Port 2 outputs the high
byte of the external memory address when the address is 16 bits wide. Otherwise, the
Port 2 pins continue to emit the P2 SFR content.
All the Port 3 pins are multifunctional. They are not only port pins, but also
serve the functions of various special features as listed below:
4.3.1 Port Pin Alternate Function
P3.0 RxD (serial input port)

P3.1 TxD (serial output port)
P3.2 INT0 (external interrupt)
P3.3 INT1 (external interrupt)
P3.4 T0 (Timer/Counter 0 external input)
P3.5 T1 (Timer/Counter 1 external input)
P3.6 WR (external Data Memory write strobe)
P3.7 RD (external Data Memory read strobe)
4.4 Timer/Counters
The 80C51 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1.
Both can be configured to operate either as timers or event counters (see Figure 6). In the
“Timer” function, the register is incremented every machine cycle. Thus, one can think
Uni.Reg.No : 26034 – 18 –
of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods,
the count rate is 1/12 of the oscillator frequency. In the “Counter” function, the register is
incremented in response to a 1-to-0 transition at its corresponding external input pin, T0
or T1. In this function, the external input is sampled during S5P2 of every machine cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is
incremented. The new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since it takes 2 machine cycles
(24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of
the oscillator frequency. There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once before it changes, it should
be held for at least one full cycle. In addition to the “Timer” or “Counter” selection,
Timer 0 and Timer 1 have four operating modes from which to select.
Fig 4: TCON register and TMOD register
Timer 0 and Timer 1:
Uni.Reg.No : 26034 – 19 –
The “Timer” or “Counter” function is selected by control bits C/T in the
Special Function Register TMOD. These two Timer/Counters have four operating modes,
which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for
both Timers/Counters. Mode 3 is different. The four operating modes are described in the
following text.
Mode 0:
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is
an 8- bit counter with a divide-by-32 prescaler. Figure 7 shows the Mode 0 operation as it
applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TF1. The counted
input is enabled to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. (Setting
GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse
width measurements). TR1 is a control bit in the Special Function Register TCON
(Figure 8). GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the
lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored.
Setting the run flag (TR1) does not clear the registers. Mode 0 operation is the same for
the Timer 0 as for Timer1. Substitute TR0, TF0, and INT0 for the corresponding Timer 1
signals in Figure 7. There are two different GATE bits, one for Timer 1 (TMOD.7) and
one for Timer 0 (TMOD.3).
Fig 5: Block schematic of mode0 timer
Mode 1:
Uni.Reg.No : 26034 – 20 –
Mode 1 is the same as Mode 0, except that the Timer register is being run
with all 16 bits.
Mode 2:
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with
automatic reload, as shown in Figure 9. Overflow from TL1 not only sets TF1, but also
re loads TL1 with the contents of TH1, which is preset by software. The reload leaves
TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0.
Fig 6: Block schematic of mode2 timer
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic
for Mode 3 on Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: C/T,
GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls
the “Timer 1” interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer
on the counter. With Timer 0 in Mode 3, an 80C51 can look like it has three
Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by
switching it out of and into its own Mode 3, or can still be used by the serial port as a
baud rate generator, or in fact, in any application not requiring an interrupt.
Uni.Reg.No : 26034 – 21 –
4.5 Standard Serial Interface
The serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can commence reception of a
second byte before a previously received byte has been read from the register. (However,
if the first byte still hasn’t been read by the time reception of the second byte is complete,
one of the bytes will be lost.) The serial port receive and transmit registers are both
accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register,
and reading SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes:
Mode 0:
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency.
Mode 1:
10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8
data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.
Uni.Reg.No : 26034 – 22 –
Mode 2:
11 bits are transmitted (through TxD) or received (through RxD): start it (0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th
data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity
bit (P, in the PSW) could be moved into TB8. On receive,
the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is
ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency.
Mode 3:
11 bits are transmitted (through TxD) or received (through RxD): a start bit (0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that uses SBUF as a
destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN =
1. Reception is initiated in the other modes by the incoming start bit if REN = 1.
4.5.1 Multiprocessor Communications:
Modes 2 and 3 have a special provision for multiprocessor communications.

In these modes, 9 data bits are received. The 9 th one goes into RB8. Then comes a stop
bit. The port can be programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in
SCON. A way to use this feature in multiprocessor systems is as follows:
When the master processor wants to transmit a block of data to one of several
slaves, it first sends out an address byte which identifies the target slave. An address byte
differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte.
With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit and prepare to receive the data
bytes that will be coming.
Uni.Reg.No : 26034 – 23 –
The slaves that weren’t being addressed leave their SM2s set and go on about
their business, ignoring the coming data bytes.SM2 has no effect in Mode 0, and in Mode
1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a valid stop bit is received.
Serial Port Control Register:
The serial port control and status register is the Special Function Register
SCON, shown in Figure 11. This register contains not only the mode selection bits, but
also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt
bits (TI and RI).
Fig 8:SCON register
Baud Rates:
Uni.Reg.No : 26034 – 24 –
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator Frequency
/ 12. The baud rate in Mode 2 depends on the value of bit SMOD in Special Function
Register PCON. If SMOD = 0 (which is the value on reset), the baud rate is 1/64 the
oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency.
Mode 2 Baud Rate = 2SMOD * 64/ Oscillator Frequency
In the 80C51, the baud rates in Modes 1 and 3 are determined by the Timer 1
overflow rate.
Using Timer 1 to Generate Baud Rates:

When Timer 1 is used as the baud rate generator, the baud rates in Modes 1
and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows:
Mode 1, 3 Baud Rate = 2SMOD * 32 /Timer 1 Overflow Rate:
The Timer 1 interrupt should be disabled in this application. The Timer itself can be
configured for either “timer” or “counter” operation, and in any of its 3 running modes.
In the most typical applications, it is configured for “timer” operation, in the auto-reload
mode (high nibble of TMOD = 0010B). In that case the baud rate is given by the formula:
Mode 1, 3 Baud Rate = 2SMOD * Oscillator Frequency / (32 *12 (256-(TH1)))
One can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt
enabled, and configuring the Timer to run as a 16-bit timer (high nibble of TMOD =
0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Figure 12 lists
various commonly used baud rates and how they can be obtained from Timer 1.
Fig 9: Baud rate setting
Uni.Reg.No : 26034 – 25 –
Fig 10: Interrupt sources
4.6 Interrupts:
Uni.Reg.No : 26034 – 26 –
The 89C51 provides 5 interrupt sources. These are shown in Figure 12. The
External Interrupts INT0 and INT1 can each be either level-activated or transition-
activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually
generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is
generated, the flag that generated it is cleared by the hardware when the service routine
is vectored to only if the interrupt was transition-activated. If the interrupt was level-
activated, then the external requesting source is what controls the request flag, rather than
the on-chip hardware. The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1,
which are set by a rollover in their respective Timer/Counter registers (except see Timer
0 in Mode 3). When a timer interrupt is generated, the flag that generated it is cleared by
the on-chip hardware when the service routine is vectored to. The Serial Port Interrupt is
generated by the logical OR of RI and TI.
Neither of these flags is cleared by hardware when the service routine is vectored to. In
fact, the service routine will normally have to determine whether it was RI or TI that
generated the interrupt, and the bit will have to be cleared in software. All of the bits that
generate interrupts can be set or cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts can be generated or pending
interrupts can be canceled in software.
Each of these interrupt sources can be individually enabled or disabled by setting or
clearing a bit in Special Function Register IE (Figure 18). IE also contains a global
disable bit, EA, which disables all interrupts at once.
Priority Level Structure:
Each interrupt source can also be individually programmed to one of two

priority levels by setting or clearing a bit in Special Function Register IP (Figure 19). A
low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by
another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other
interrupt source. If two requests of different priority levels are received simultaneously,
the request of higher priority level is serviced. If requests of the
Uni.Reg.No : 26034 – 27 –
Same priority level are received simultaneously, an internal polling sequence determines
which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as follows:
Source Priority within Level:
1. IE0 (highest)
2. TF0
3. IE1
4. TF1
5. RI+TI (lowest)
Note that the “priority within level” structure is only used to resolve
Simultaneous requests of the same priority level. The IP register contains a number of
unimplemented bits. IP.7, IP.6, and IP.5 are reserved in the 80C51. User software should
not write 1s to these positions, since they may be used in other 8051 Family products.
4.6.1 How Interrupts Are Handled:
The interrupt flags are sampled at S5P2 of every machine cycle. The samples
are polled during the following machine cycle. If one of the flags was in a set condition
at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will
generate an LCALL to the appropriate service routine, provided this hardware-generated
LCALL is not blocked by any of the following
Conditions:
1. An interrupt of equal or higher priority level is already in progress.

2. The current (polling) cycle is not the final cycle in the execution of the instruction in
progress.
3. The instruction in progress is RETI or any write to the IE or IP registers.
Uni.Reg.No : 26034 – 28 –
Any of these three conditions will block the generation of the LCALL to the interrupt
service routine. Condition 2 ensures that the instruction in progress will be completed
before vectoring to any service routine. Condition 3 ensures that if the instruction in
progress is RETI or any access to IE or IP, then at least one more instruction will be
executed before any interrupt is vectored to. The polling cycle is repeated with each
machine cycle, and the values polled are the values that were present at S5P2 of the
previous machine cycle. Note that if an interrupt flag is active but not being responded to
for one of the above conditions, if the flag is not still active when the blocking condition
is removed, the denied interrupt will not be serviced. In other words, the fact that the
interrupt flag was once active but not serviced is not remembered. Every polling cycle is
new. The polling cycle/LCALL sequence is illustrated in Figure 20.
Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine
cycle labeled C3 in Figure 20, and then in accordance with the above rules it will be
vectored to during C5 and C6, without any instruction of the lower priority routine
having been executed. Thus the processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate servicing routine. In some
cases it also clears the flag that generated the interrupt, and in other cases it doesn’t. It
never clears the Serial Port flag. This has to be done in the user’s software. It clears an
external interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware-
generated LCALL pushes the contents of the Program Counter on to the stack (but it does
not save the PSW) and reloads the PC with an address that depends on the source of the
interrupt being vectored to, as shown below:
Source Vector Address:
IE0: 0003H
TF0: 000BH
IE1: 0013H
TF1: 001BH
RI+TI: 0023H
Uni.Reg.No : 26034 – 29 –
Execution proceeds from that location until the RETI instruction is encountered.
Fig 11: Interrupt Enable register
Fig 12: Interrupt priority register
4.7 Power-on Reset:
An automatic reset can be obtained when VCC is turned on by connecting

the RST pin to VCC through a 10 f capacitor and to VSS through an 8.2k resistor,
providing the VCC rise time does not exceed 1 millisecond and the oscillator start-up
time does not exceed 10 milliseconds. This power-on reset circuit is shown in Figure 13.
The CMOS devices do not require the 8.2k pull down resistor, although its presence does
no harm. When power is turned on, the circuit holds the RST pin high for an amount of
time that depends on the value of the capacitor and the rate at which it charges. To ensure
Uni.Reg.No : 26034 – 30 –
a good reset, the RST pin must be high long enough to allow the oscillator time to start-
up (normally
a few ms) plus two machine cycles. Note that the port pins will be in a random state until
the oscillator has started and the internal reset algorithm has written 1s to them. With this
circuit, reducing VCC quickly to 0 causes the RST pin voltage to momentarily fall below
0V. However, this voltage is internally limited, and will not harm the device.
U 1
3 9 2 1
3 8 P 0 . 0 / A D 0 P 2 . 0 / A 8 2 2
3 7 P 0 . 1 / A D 1 P 2 . 1 / A 9 2 3
3 6 P 0 . 2 / A D 2 P 2 .2 /A 1 0 2 4
3 5 P 0 . 3 / A D 3 P 2 .3 /A 1 1 2 5
3 4 P 0 . 4 / A D 4 P 2 .4 /A 1 2 2 6
3 3 P 0 . 5 / A D 5 P 2 .5 /A 1 3 2 7
3 2 P 0 . 6 / A D 6 P 2 .6 /A 1 4 2 8
P 0 . 7 / A D 7 P 2 .7 /A 1 5
1 1 0
2 P 1 . 0 P 3 .0 /R XD 1 1
3 P 1 . 1 P 3 .1 /T XD 1 2
4 P 1 . 2 P 3 .2 /IN T O 1 3
5 P 1 . 3 P 3 .3 /IN T 1 1 4
6 P 1 . 4 P 3 .4 /T O 1 5
7 P 1 . 5 P 3 .5 /T 1 1 6
V C C 8 P 1 . 6 P 3 .6 /W R 1 7
P 1 . 7 P 3 .7 /R D
C 9 1 9 2 9
1 0 M F D 1 8 XT A L 1 P S E N
9 XT A L 2 3 0
R S T A L E /P R O G
R 3 3 1
E A /V P P
1 0 K
A T 8 9 C 5 1
C 4 C 3
1 8 p F 1 8 p F
;
Fig 13: Power-on reset connection
4.7.1 Power-Saving Modes of Operation:
For applications where power consumption is critical the CMOS version

provides power reduced modes of operation as a standard feature. The power down mode
in NMOS devices is no longer a standard feature.
Uni.Reg.No : 26034 – 31 –
CMOS Power Reduction Mode:
CMOS versions have two power reducing modes, Idle and Power Down.
The input through which backup power is supplied during these operations is VCC.
Figure 23 shows the internal circuitry which implements these features. In the Idle
modes (IDL = 1), the oscillator continues to run and the Interrupt, Serial Port, and Timer
blocks continue to be clocked, but the clock signal is gated off to the CPU. In Power
Down (PD = 1), the oscillator is frozen. The Idle and Power
Down Modes are activated by setting bits in Special Function Register PCON. The
address of this register is 87H. Figure 24 details its contents. In the NMOS devices the
PCON register only contains SMOD. The other four bits are implemented only in the
CMOS devices. User software should never write 1s to unimplemented bits, since they
may be used in other 80C51 Family products.
Idle Mode:
An instruction that sets PCON.0 causes that to be the last instruction
executed before going into the idle mode, the internal clock signal is gated off to the CPU
but not to the Interrupt, Timer, and Serial Port functions. The CPU status is preserved in
its entirety; the Stack Pointer, Program Counter, Program Status Word, Accumulator, and
all other registers maintain their data during Idle.
The port pins hold the logical states they had at the time Idle was activated. ALE and
PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of
any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle
mode. The interrupt will be serviced, and following RETI, the next instruction to be
executed will be the one following the instruction that put the device into Idle. The flag
bits GF0 and GF1 can be used to give an indication if an Interrupt occurred during
normal operation or during an Idle. For example, n instruction that activates Idle can also
set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service
routine can examine the flag bits. The other way of terminating the idle mode is with a
hardware reset. Since the clock oscillator is still running, the hardware reset needs to be
held active for only two machine cycles (24 oscillator periods) to complete the reset. The
Uni.Reg.No : 26034 – 32 –
signal at the RST pin clears the IDL bit directly and asynchronously. At this time the CPU
resumes program execution from where it left off; that is, at the instruction following the
one that invoked the Idle Mode. As shown in Figure, two or three machine cycles of
program execution may take place before the internal reset algorithm takes control. On-
chip hardware inhibits access to the internal RAM during this time, but access to the port
pins is not inhibited, so, the insertion of 3 NOP instructions is recommended following
the instruction that invokes idle mode. To eliminate the possibility of unexpected outputs
at the port pins, the instruction following the one that invokes Idle should not be one that
writes to a port pin or to external Data RAM.
Fig 14:SCON register
Uni.Reg.No : 26034 – 33 –
CHAPTER 5:
INTERFACING AN LCD TO THE 89C51
This section describes the operation modes of LCD’s, then describes how to
program and interface an LCD to an 8051.
5.1 LCD operation
In recent years the LCD is finding wide spread use replacing LED’s (seven
segment LED’s or other multi -segment LED’s). This is due to the following reasons:
1. The declining prices of LCD’s

2. The ability to display numbers, characters, and graphics. This is in contrast to LED’s,
which are limited to numbers and few characters.
3. Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of
the task of refreshing the LCD. In contrast, the LED must be refreshed by the CPU(or
in some other way) to keep displaying the data.
4. Ease of programming for characters and graphics.
5.1.1 LCD pin descriptions
Vcc, Vss, and Vee:
While Vcc and Vss provide +5v and ground, respectively, Vee is used for
controlling the LCD contrast.
RS, register select:
Uni.Reg.No : 26034 – 34 –
There are two very important registers inside the LCD. The RS pin is used for
their selection as follows. If RS=0, the instruction command code register is selected,
allowing the user to send a command such as clear display, cursor at home, etc. If RS=1
the data register is selected, allowing the user to send data to be displayed on the LCD.
R/W, read/write:
R/W input allows the user to write information to the LCD or read
information from it. R/W=1 when reading; R/W=0 when writing.
E, enable:
The enable pin is used by the LCD to latch information presented to its data pins.
When data is supplied to data pins, a high-to-low pulse must be applied to this pin in
order for the LCD to latch in the data present at the data pins. This pulse must be a
minimum of 450ns wide.
D0-D7
The 8-bit pins, D0- D7, are used to send information to the LCD or read the
contents of the LCD’s internal registers. To display letters and numbers, we send ASCII
codes for the letters A-Z, a-z, and numbers 0-9 to these pins while making RS=1.There
are also instruction command codes that can be sent to the LCD to clear the display or
force the cursor to the home position or blink the cursor,
We also use RS=0 to check the busy flag bit to see if the LCD is ready to
receive information. The busy flag is D7 and can be read when R/W=1 and RS=0, as
follows: if R/W=1, RS=0. When D7=1(busy flag=1) , the LCD is busy taking care of
internal operations and will not accept any new information. When D7=0, the LCD is
ready to receive new information.
Uni.Reg.No : 26034 – 35 –
Fig 15: Interfacing of AT89C51 with LCD
Pin descriptions for LCD:
Pin Symbol I/O Descriptions
1. VSS -- Ground
2. VCC -- +5V power supply.
3 VEE -- Power supply to control
Contrast.
4. RS 1 RS=0 to select command
Uni.Reg.No : 26034 – 36 –
Register,
RS=1 to select data
register
5 R/W 1 R/W=0 for write, R/W=1
For read
6 E I/O Enable
7 DB0 I/O the 8 bit data bus
15 LCD+ -- VCC
16 LCD- -- Ground
5.2 Display Section

Display section is implemented using a Liquid Crystal Display in this circuit 16*2 LCD
is used. That means 16 column and two rows. LCD module has 16 pins by which it is
connected and controlled by micro controller.
Fig 16:LCD Pin diagram
Uni.Reg.No : 26034 – 37 –
CHAPTER 6:
SENSOR INTERFACING:
Sensing section is implemented using a LDR. One pin of LDR is connected to

ground and the second pin is connected to VCC using a 10K resistor
VC C
R 2
10 K
J8
1
2
LD R
Fig 17:LDR connection
6.1 Light sensing:

Sensing section is implemented using a LDR. One pin of LDR is
connected to ground and the second pin is connected to VCC using a 10K resistor. Output
is taken from the second pin. It is given to a comparators non inverting pin. Reference
voltage is given to inverting pin of comparator through a preset (variable resistor).
Assume reference voltage is VCC/2. Light in the room is high then LDRs resistance will
be very low. So comparators non inverting pin will be low. So its output will be Zero.
When room is darken LDRs resistance will be high and connected pin of comparator will
be high compared to reference pin. Then the output will be high.
Uni.Reg.No : 26034 – 38 –
VC C
R 6
10K
LD R
VC C
VR 2 U 6B
8
5
3
10 K +
7
6
2
- Buzzer
LM 358
4
Fig18:Light sensing using LDR

1
6.2 Temperature sensing:
A temperature sensing module is used instead of LDR. Its output will be a

voltage directly proportional to the temperature. This voltage is given to comparator.
VC C
VC C
J5
3
1 VR 1
2
3 2 10 K
LM 35
U 6A
1
3
+
1
2
-
LM 358
4
Fig 19:Temperature sensing using LM35
Uni.Reg.No : 26034 – 39 –
CHAPTER 7:
POWER SUPPLY SECTION
U 2
D I1 +12V P o w e r su p p ly LM 7805 +5V
A C 1 3
J2 V IN VO U T
G N D
1N 4007 C 2
2
3 10 m fd
D I2 C 1
2
1 2 -0 -1 2 v a .c A C
2 2 0 0 M F D /2 5 v
1N 4007
Fig 20:Power supply section
Power supply is built by using center tapped rectifier, filter and regulators. 7805 is used
for 5v.
7.1 Features of 7805 Regulators:
• Output current up to 1.5 a

• Thermal overload protection
• Short circuit protection
• Output transition protection
The L7800 series of three-terminal positive regulators is available packages and several
fixed output voltages, making it useful in a wide range of applications. These regulators
can provide local on-card regulation, eliminating the distribution problems associated
with single point regulation. Each type employs internal current limiting, thermal shut-
down and safe area protection, making it essentially indestructible. If adequate heat
sinking is provided, they can deliver over 1A output current. Although designed primarily
as fixed voltage regulators, these devices can be used with external components to obtain
adjustable voltages and currents.
Uni.Reg.No : 26034 – 40 –
CHAPTER 8:
PROGRAMMING SECTION
8.1 Algorithm for ADC interface and serial communication:
1. Initialize serial port.

2. Load timer mode register (TMOD).
3. Load TH1 (in order to baud rate setting).
4. Load SCON (for serial transmission).
5. Give a square wave at P3.3 by using a delay routine.
6. Check TI bit (to check whether the transmission is over).
7. Clear TI bit.
8. Go to step 2
8.1.1 Program code for ADC interface and serial communication

ORG 0000H
SJMP MAIN
ORG 30H
MAIN: CLR EA
MOV P1,#0FFH ; make input port
MOV TMOD,#20H ; mode2 timer1
MOV TH1,#0FDH ; for setting baud rate
MOV SCON,#50H ; enable for serial communication
SETB TR1 ; start timer1
REPEAT: CPL P3.3 ; to generate a square wave at this pin
MOV R0,#0FFH ; to make delay loop
L4: MOV R1,#0FFH
L3: MOV R2,#0FFH
L2: MOV R3,#0FFH
Uni.Reg.No : 26034 – 41 –
L1: MOV A,P1
MOV P2,A
MOV SBUF, A
LOOP: JNB TI, LOOP
CLR TI
DJNZ R3,L1
DJNZ R2,L2
DJNZ R1,L3
DJNZ R0,L4
SJMP REPEAT
END
8.1.2 Program code for LCD interface and serially reception

ORG 0000H
SJMP MAIN
ORG 0030H
MAIN:
MOV TMOD,#20H
MOV TH1,#0FDh
MOV SCON,#50H
SETB TR1
CLR RI
HERE:JNB RI,HERE
MOV A,SBUF
MOV P2,A
MOV R7,A
LCDWEL: MOV A,#3CH
CALL COMMAND
MOV A,#01H
CALL COMMAND
MOV A,0EH
Uni.Reg.No : 26034 – 42 –
CALL COMMAND
MOV A,#80H
CALL COMMAND
CLR RI
DIV: MOV A,R7
MOV B,#10
DIV AB
MOV R1,A
MOV R2,B
MOV A,R1
MOV B,#10
DIV AB
MOV R6,A
MOV R5,B
MOV DPTR,#300H
CLRA
MOV A,R6
MOVC A,@A+DPTR
ACALL DATA
MOV DPTR,#300H
CLR A
MOV A,R5
MOVC A,@A+DPTR
ACALL DATA
MOV DPTR,#300H
CLRA
MOV A,R2
MOVC A,@A+DPTR
ACALL DATA
LJMP HERE
COMMAND: MOV P1,A
Uni.Reg.No : 26034 – 43 –
CLR P3.2
SETB P3.4
CLR P3.4
MOV R3,#32
M:MOV R4,#255
N:DJNZ R4,N
DJNZ R3,M
RET
DATA: MOV P1,A

SETB P3.2
SETB P3.4
CLR P3.4
MOV R3,#32
R:MOV R4,#255
Q:DJNZ R4,Q
DJNZ R3,R
RET
ORG 300H
DB ‘0’
DB ‘1’
DB ‘2’
DB ‘3’
DB ‘4’
DB ‘5’
DB ‘6’
DB ‘7’
DB ‘8’
DB ‘9’
Uni.Reg.No : 26034 – 44 –
CHAPTER 9:
PCB DESIGN:
Orcad is used to prepare PCB and schematic. Orcad capture is used to draw
the schematic, Orcad layout is used to draw the PCB layout.
Netlist is generated from schematic drawn in orcad capture. It is imported
in Orcad layout, placed and routed the PCB.
9.1 PCB Preparation:
Layout is printed on a butter paper (transparent paper). It is screen printed

on the copper clad, etched by using ferric chloride solution and drilled by using a PCB
drill.
Prepare
Schematic in
Orcad Capture
Generate Netlist
for Layout
Prepare
Schematic in
Orcad Capture
Generate Gerber
file and make
printouts
Uni.Reg.No : 26034 – 45 –
CHAPTER 10:
INTERFACING 89C51 WITH PC SERIALLY

10.1 Aim:
Interface serially ATMEL89C51 with a standard IBM PC and to transfer the data
received by the PC to another PC using JAVA socket programming.
10.2 Objectives:
• Study and implement voltage level conversion using MAX232

• Establish serial connection between PC and the microcontroller
• Using HyperTerminal transfer data between microcontroller and PC
Uni.Reg.No : 26034 – 46 –
10.3 Circuit Diagram:
Fig. 21
10.4 Theory:
MICRO-CONTROLLER
Micro Controller used in this circuit is AT89C51. It is a 40 pin IC. It has 4 Ports P0 to P3.
1. 89C51 MICROCONTROLLER HARDWARE

The 8051 architecture consists of these specific features:
 Eight bit CPU with registers A (accumulator) and B
 Sixteen bit program counter and data pointer (DPTR)
Uni.Reg.No : 26034 – 47 –
 Eight bit program status word

 Eight stack pointer
 Internal ROM or EPROM (8751) of 0(8031) to 4k(8051)
 Internal RAM of 128 bytes: Four register banks each contain eight registers
 Sixteen bytes, which may be addressed at the bit level
 Eighty bytes of general purpose data memory
 Thirty two input/output pins arranged four eight bit ports: p0-p3
 Two sixteen bit timer/counters: t0-t1
 Full duplex serial data receiver/transmitter: SBUF
 Control registers: TCON, TMOD, SCON, PCON, IP and IE
 Two external three internal interrupt sources Oscillator and clock circuits
10.4.1 MAX 232:
The voltage level used in 89C51 is 5V (TTL)and that used in RS232 standards is 12V.So
the PC cannot be connected directly to the microcontroller. Between these two MAX232
is used as a voltage level converter. It can convert 5V to 12V while transmitting signals
from microcontroller to PC and also convert 12V to 5V while transmitting signals from
PC to microcontroller.
Fig. 22
Uni.Reg.No : 26034 – 48 –
10.4.2 Loop Back Plug
Fig. 25
This loop back plug can come in extremely handy when writing Serial / RS232
Communications Programs. It has the receive and transmit lines connected together, so
that anything transmitted out of the Serial Port is immediately received by the same port.
If you connect this to a Serial Port an load a Terminal Program, anything you type will be
immediately displayed on the screen.
10.5.1 Algorithm:
1. Start
2. Initialize port1
3. Wait for a data in port1
4. If there is data receive it and display it
5. Save the character received to a file named file.txt
6. Else check for any keystroke
7. If there is a keystroke send it to port 1
8. Go to step3
10.5.2 Microcontroller Programming:
Uni.Reg.No : 26034 – 49 –
Algorithm:
1. Start
2. Set timer 1 in mode 2
3. Set baud rate to 9600
4. Set SCON in mode1
5. Start timer 1
6. Set P1=01101110b
7. Receive a value from PC serially
8. Display the value in P1
9. Transmit the value to PC
10. Go to step 7
11. Stop
Program Code:
ORG 00H
SJMP MAIN
ORG 30H
MAIN:
MOV TMOD,#20H ;timer 1, mode 2(auto reload)
MOV TH1,#-3 ;9600 baud rate
MOV SCON #50H ;8 bit, 1 stop bit, REN enabled
SETB TR1 ;start timer 1
MOV A,#66h
MOV P1,A
AGAIN:
CLR RI
LOOP:
JNB RI LOOP
MOV A,SBUF ;receiving a byte
MOV P1,A
CLR TI
MOV SBUF,A ;transmitting a byte
ALOOP:
JNB TI ALOOP
SJMP AGAIN
Uni.Reg.No : 26034 – 50 –
10.6 Screenshots of output
Using HyperTerminal:-
Adjusting the settings like baud rate, parity bit etc..
Uni.Reg.No : 26034 – 51 –
Sending character by character
Uni.Reg.No : 26034 – 52 –
Sending text file

!!!$$$%^^&^*&*(***())_)_}}{}|}???>>????>><>
!!!$$$%^^&^*&*(***())_)_}}{}|}???>>????>><>
Uni.Reg.No : 26034 – 53 –
BIBLIOGRAPHY
1. PROGRAMMING WITH 8051, MUHAMMED ALI MAZIDI
2. 8051 PROGRAMMING , KENNETH J. AYALA
Uni.Reg.No : 26034 – 54 –
CONCLUSION
The hardware section of the data acquisition was implemented. This
hardware part can be upgraded to be used in the data acquisition system, for which the
ADC has to be replaced with MCP3201. The ‘brain’ of the data acquisition can be
upgraded from AT89C51 to TINI, for greater efficiency. Different parameters can be
acquired and displayed or processed using the data acquisition system.
Uni.Reg.No : 26034 – 55 –

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Rajagiri School of Engineering &

Uni.Reg.No : 26034 –1–

The project, titled PC BASED DATA ACQUISITION SYSTEM, aims at

Micro Controller and a LCD display.

The sensor senses the physical parameter in terms of a measurable electrical

then displays the data on LCD (16 x 2 ) display.

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2.1.1 BRIEF DESCRIPTION OF THE COMPONENTS:

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Fig 2: Interfacing of ADC804 with AT89C51

2.2.2 PIN DESCRIPTION:

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CLK IN and CLK R:

Vin(+) and Vin(-) :

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ANALOG GROUND and DIGITAL GROUND

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INTRODUCTION TO SERIAL COMMUNICATION

3.1 Advantages of Serial Communication

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3.2 Basics of Serial Communication

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3.2.1 Half-and full-duplex transmission

3.2.2 Asynchronous serial communication and data framing

Start and stop bits:

In asynchronous serial communication, peripheral chips and modems can be

3.2.3 Synchronous Communication

3.3 Data transfer rate

3.4 Parallel Communication

4.1 89C51 MICROCONTROLLER HARDWARE

Fig 3:AT89C51 Micro controller Hardware

The 8051 architecture consists of these specific features:

 Eight bit CPU with registers A (accumulator) and B

4.2 Special Function Registers

Program Status Word:

Serial Data Buffer:

Timer Registers Basic to 80C51:

4.3 Port Structures and Operation

4.3.1 Port Pin Alternate Function

P3.0 RxD (serial input port)

Fig 4: TCON register and TMOD register

Timer 0 and Timer 1:

Fig 5: Block schematic of mode0 timer

Fig 6: Block schematic of mode2 timer

4.5 Standard Serial Interface

The serial port can operate in 4 modes:

4.5.1 Multiprocessor Communications:

Modes 2 and 3 have a special provision for multiprocessor communications.

Serial Port Control Register:

Fig 8:SCON register

Using Timer 1 to Generate Baud Rates:

Fig 9: Baud rate setting

Fig 10: Interrupt sources

Priority Level Structure:

Each interrupt source can also be individually programmed to one of two

Source Priority within Level:

4.6.1 How Interrupts Are Handled:

1. An interrupt of equal or higher priority level is already in progress.

Source Vector Address:

Fig 11: Interrupt Enable register

Fig 12: Interrupt priority register

4.7 Power-on Reset: