Ti Jtag Seminar

Topic 8 - JTAG Boundary Scan
JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory
Agenda
■ What Is JTAG? (5 minutes)
JTAG ■
■
The Increasing Problem of Test
Conventional Methods of Test
(5 minutes)
(10 minutes)
■ The Boundary-Scan Idea (15 minutes)
(IEEE 1149.1/P1149.4) ■ The Boundary-Scan Architecture (15 minutes)
■ Typical Applications (15 minutes)
Tutorial —
—
Interconnect Testing
Logic Cluster Testing
Introductory ■
—
—
Memory Testing
System-Level Test
Real JTAG Applications (10 minutes)
■ For More Information (5 minutes)
■ Q&A (10 minutes)
AL 10Sept.-97 1149.1(JTAG)-Tut.I-1 1997 TI Test Symposium AL 10Sept.-97 1149.1(JTAG)-Tut.I-2 1997 TI Test Symposium
Standard Approach To Test
JTAG / IEEE 1149.1

What Is JTAG?
■ Developed by Joint Test Action Group (over 200 SC, test, and
system vendors) starting in mid '80's
■ Sanctioned by IEEE as Std 1149.1 Test Access Port and
Boundary-Scan Architecture in 1990
■ Solution: Build test facilities/test points into chips
■ Focus: Ensure compatibility between all compliant ICs
Standard Test Access Port ... … and Boundary-Scan

Architecture
User Register
TDI TDO ■ Scan effectively partitions digital
Bypass Register logic to facilitate control and
DR Decode Logic
observation of its function
TMS CORE
TAP ■ Chip-Internal Scan: Partitions

TCK IR Instruction Register
Controller chips at storage cells (latches/ flip-
flops) to effectively partition
TRST*
sequential logic into clusters of
■ 4/5-Wire Interface at Chip-Level combinational logic
■ Boundary-Scan: Partitions boards
■ Serial Instruction/Serial Data Port
at chip I/Os for control and
■ Extensible to Include observation of board-level nodes
— user-defined instructions
— user-defined data registers
The Incredible Shrinking

Board
■ Miniaturization results in loss of test access
The Increasing
Problem of Test
Yesterday Today Tom orrow ?
Can’t Afford Not To Test

The Ever-Expanding Chip
Cost will increase by a factor of
■ Increasing integration at chip level ten as fault finding moves
complicates controllability from one level of complexity
to the next. The result:
■ Reduced Profit Margins
■ Delayed Product
Introduction
1 0 ■ Dissatisfied Customers
1 C1 C1
?
1D 1D
1. Device level 1 unit of cost

2. Board level 10 units of cost
3. System level 100 units of cost
Yesterday Today 4. Field level 1,000 units of cost
Conventional Methods
of Board Test
Functional Test
Conventional (‘Edge-Connector’ Test)
■ Based on board function,
Methods of rather than structure
■ Test generation primarily
Test manual
■ Test access limited to

primary I/O only
Conventional Methods Conventional Methods

of Board Test of Board Test
In-Circuit Test In-Circuit Test
(‘Bed-of-Nails’ Test) (‘Bed-of-Nails’ Test)
■ Based on board structure, but ■ Chip function can be
limited by chip complexity ignored for shorts testing
■ Expensive testers and fixtures
■ Chip function must be
required
considered for continuity
■ Test access limited by: test
— Fine pitch packages
■ Test generation, though
— Double-sided boards
automated, requires ICT
— Conformal coating
models
— MCMs
The Boundary Scan Idea
■ ‘In-Circuit’ test points moved

The onto the silicon, creating
‘Virtual Nails’
Boundary-Scan
CORE CORE
■ Boundary scan cells bound
each net, providing for
continuity testing
Idea ■ Observe/Control cells provide

for test and normal function
The Boundary Scan Idea Boundary Scan Method

of Board Test
■ Scan provides a means CORE CORE
to arbitrarily observe ■ Based on board structure;

CORE CORE
test results and source Not limited by chip
test stimulus function/ complexity
CORE CORE
■ Scan method requires ■ Test access is not limited

minimal on chip/board by board physical factors
resources (pins/nets)
CORE CORE
J
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Boundary Scan Method The Boundary Scan Cell

of Board Test
NI (Normal Input)
SO (Serial Output)
■ Chip function need not be
considered for board test
OBSERVE CONTROL
(shorted/open nets)
TEST/DATA
MUX
NO (Normal Output)
■ Test generation is highly CAPTURE/SCAN MUX
automated; Simple CORE

‘In-Circuit Library’ models
(BSDL) are vendor- SCAN
LATCH/FLOP
UPDATE
LATCH/FLOP
supplied or
EDA-generated SI (Serial Input)
The Test Access Port Controller

The Control Architecture
1 Test Logic Reset
0
■ Boundary scan and other test 1 1 1 ■ 16-state TAP
0 Run Test/Idle Select DR-Scan Select IR-Scan
data registers operate under provides 4 major
0 0
control of instruction operations:
1 1
Capture DR Capture-IR — RESET
register
0 0 — RUN-TEST
■ Data is scanned from TDI to — SCAN-DR

CORE state 0 Shift-DR Shift-IR 0
TDO through selected test transitions 1 1 — SCAN-IR
occur on
data register or instruction 1 1
rising edge Exit 1-DR Exit 1-IR
register under control of Test of TCK 0 0 ■ Scans consist of 3
ID Register based on primary steps:
TDI TDO Access Port (TAP) controller the current 0
Bypass Register
Pause-DR Pause-IR 0 — CAPTURE
state and
1 1
TMS
DR Decode Logic ■ TAP operates synchronously the TMS — SHIFT
input value 0 0
TCK
TAP IR Instruction Register
to TCK using TMS for state ONLY
Exit 2-DR Exit 2-IR — UPDATE
Controller
selection 1 1
Update-DR Update-IR
1 0 1 0
The Extest Instruction The Sample/Preload Instruction

(REQUIRED) (REQUIRED)
■ Provides for test external to chip, ■ Provides means to preload
such as interconnect test boundary before entry to test
mode
Output pins operate in test mode,
driven from contents of BSC ■ Output and input pins operate
update latch in normal mode
CORE Input data captured in BSC scan CORE Input pin data and core logic
latches prior to shift operation output data captured in BSC
scan latches
■ Shift operation allows test
response to be observed at TDO ■ Shift operation allows test
ID Register ID Register
TDI TDO
while next test stimulus inserted TDI TDO response to be observed while
Bypass Register
at TDI Bypass Register
next test stimulus inserted at
TMS
DR Decode Logic TMS
DR Decode Logic TDI
TAP
Following shift operation, new TAP
TCK IR TCK IR Instruction Register
Controller
Instruction Register
test stimulus transferred to BSC Controller Following shift operation,
update latches new stimulus transferred to
BSC update latches
The Bypass Instruction

(REQUIRED)
■ Provides for abbreviated scan

path through chip
CORE ■ Output and input pins operate

in normal mode
Typical JTAG
TDI
ID Register
TDO
■ The one-bit bypass register is
selected for scans
Applications
Bypass Register
TMS
DR Decode Logic ■ Mandatory that an all-ones
TCK
TAP
Controller
IR Instruction Register value updated into the IR
decodes to Bypass, as well as
any opcodes which are
otherwise undefined
Interconnect Test Interconnect Test

Full B/S Board Partial B/S Board
■ Not all nets are bound by

■ All nets bound by BSC's boundary scan and/or primary
and/or primary I/O requiring I/O, perhaps requiring some ICT
no physical access access
■ Parallel access reduced ■ Expense and complexity reduced

to card edge only for test generation and test
application for chips/nets with
■ Test generation and B/S access
application fast and easy
■ Cluster testing may be used to
J J
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A
access non-scan nets
G G
Logic Cluster Test Logic Cluster Test

■ Random-logic cluster is
Buffer Latch
bound by boundary-
‘ABT18502
‘LVT18502
scannable chips
Address
Microprocessor
■ Deterministic test stimulus Control

Memory
Logic
(ATPG-generated) can be Array
"CLUSTER"
(Non-Scan)
Buffer Buffer
LOGIC
driven to cluster from B/S

‘ABT18502
‘LVT18502
outputs Control
■ Test response can be captured

at B/S inputs
Registered Transceiver
■ BIST methods (PRPG/PSA) Buffer
‘LVT18504
can be used for increased test ‘LVT18502 Data

Scan Path
throughput and near
IEEE 1149.1
"At-speed" performance
Parallel Data In
TMS
TCK
TDO
TDI
Memory Test Memory Test

SN74BCT8245 256 x 8 RAM Array SN74BCT8244
1B1 1A1 D0 A0 1Y1 1A1
Latch 1B2 1A2 D1 A1 1Y2 1A2
‘ABT18502
1B3 1A3 D2 A2 1Y3 1A3

1B4
■ Memory array bound by 2B1
1A4
2A1
D3
D4
A3
A4
1Y4
2Y1
1A4
2A1
boundary scan chips 2B2 2A2 D5 A5 2Y2 2A2
Address 2B3
2B4
2A3
2A4
D6
D7
A6
A7
2Y3
2Y4
2A3
2A4
■ Automatic test patterns can be DIR G2
Memory generated and driven from B/S G WE G1
Buffer Array outputs TDO TDI
CS
TDO TDI
‘ABT18502
TMS TCK TMS TCK
■ Test response can be captured at

Control B/S inputs SN74BCT8244 256 1,000,000
1A1 1Y1 MODE ACCESSES ACCESSES
■ Transceivers can test for net 1A2 1Y2
IEEE 1149.1 Time To Apply 5.625000 Seconds 375.00 Minutes
1A3 1Y3
shorts w/o memory R/W 1A4 1Y4 EXTEST & Scans 512 2,000,000
Registered Transceiver 2A1 2Y1 SAMPLE) Patterns 512 2,000,000
2A2 2Y2
‘LVT18504
■ BIST methods (PRPG/PSA) can 2A3 2Y3 IEEE 1149.1 Time To Apply 0.000041 Seconds < 0.01 Minutes
2Y4
Data be used for increased test 2A4 (with BIST Scans 7 28,000
G2 capability) Patterns 512 2,000,000
throughput G1
TDO TDI
TMS TCK
System-Level Test
■ TAP-addressable interface unit

extends JTAG access beyond
board-level
■
■
System-level test
System design verification
Real JTAG
A A A
S
P
S
P
S
P TDO
TDI
TMS
TCK
■
■
Sys integration (Mfg test)
Sys self-test (Field Svc)
Applications
■ Supports in place board test and
board-to-board test
■ Allows reuse of device/
board test data
✦ ASP-Addressable Scan Port Device
Real Applications of the TAP Design Verification/Debug

■ Provides control and observation of
■ Scan access to chips, boards, system under test without need for
I N T E R N A L systems for: physical access
— Design verification/debug
S C A N — Ease of set-up for test
— Manufacturing test
T E S T — Hardware/software integration
— Can be used in standard system
CORE BIST
■
— Field test/diagnostics
Access built-in self-test (BIST)

configuration (no need for card
extenders, etc.)
Emulation ■ Access on-chip/in-circuit — Can be used in environmental
emulation (ONCE/ICE) chambers
Programming
■ Access in-system programming — Can access on-chip emulation for
TAP (ISP) of PLDs/EEPROMs software/debug
■ Let your imagination run wild!!!
TDI TCK TMS TDO
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A
— Can access ISP for code
G
download/offload/ changes
Manufacturing Test System Configuration

Maintenance
■ Provides test and diagnostic ■ Provides low-level test access
ICT capabilities of in-circuit test within configured systems for:
without need/expense of
— In-house system integration
physical access
— Fielded-system test and
— Improved fault
coverage/diagnostic without
J diagnostics
T
large capital expense A — Built-in self-test
G
— Highly automated test — In-field upgradability
generation reduces test via ISP, etc.

development time
— Remote field test,
diagnostic and upgrade

J
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TI’s JTAG Educational Products IEEE Standards

Call (214)-638-0333 to ORDER Call (800) 678-IEEE to ORDER
■ IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), IEEE Standard

■ Scan Educator
Test Access Port and Boundary-Scan Architecture, ISBN 1-55937-350-4,
— PC-based tutorial with interactive IEEE order number SH16626.
boundary-scan simulation.
— The official document which specifies the international standard for a test
— FREE download at access port and boundary-scan architecture. Informally known as the JTAG
http://www.ti.com/sc/data/jtag/scanedu.exe standard, it was officially ratified by the IEEE in February 1990. Since, it has
been supplemented twice. The first supplement, ratified in June 1993, is
■ IEEE 1149.1 Testability videotapes included in the referenced document. The second supplement is currently a
— Two-part video presenting an overview and separate document, as referenced below.
instructions for boundary scan. IEEE 1149.1
Boundary-Scan
■ IEEE Std 1149.1b-1994, Supplement to IEEE Std 1149.1-1990, ISBN 1-
— Item No. SATV001 (NTSC VHS) and 55937-497-7, IEEE order number SH94256.
SATV002 (PAL VHS), $149 each. — The official document which specifies the international standard for a
— In process of converting to MPEG on CD-ROM boundary-scan description language. This supplement to IEEE Std 1149.1-1990
was ratified in September 1994.
Tutorials/Handbooks Abbreviations/Acronyms
ASIC Application-Specific Integrated Circuit IEEE Institute of Electrical & Electronics Engineers IR
ASP Addressable Scan Port Instruction Register
■ The Test Access Port and Boundary-Scan Architecture, Colin M. Maunder, Rodham
ATE Automatic Test Equipment ISP In-System Programming
E. Tulloss, ed., IEEE CS Press, ISBN 0-8186-9070-4.
ATPG Automatic Test Pattern Generation JTAG Joint Test Action Group
— Edited by two principal chairs of the IEEE 1149.1 working group, this
BIST Built-In Self-Test MCM Multi-Chip Module
Computer Society tutorial compiles several of the seminal papers on boundary- Mfg Manufacturing
B/S Boundary-Scan
scan along with several invited papers on various topics including applications, PCB Printed Circuit Board
BSC Boundary-Scan Cell
implementation, and others. It will primarily be of interest to the design and/or PLD Programmable Logic Device
BSDL Boundary-Scan Description Language
test engineer.
BSR Boundary-Scan Register PRPG Pseudo-Random Pattern Generation
■ The Boundary-Scan Handbook, Kenneth P. Parker, Kluwer Academic Publishers, PSA Parallel Signature Analysis
BST Boundary-Scan Test
ISBN 0-7923-9270-1. PWB Printed Wiring Board
CAE Computer-Aided Engineering
— Authored by the principal force behind the Boundary-Scan Description SPL Scan Path Linker
DFT Design-for-Test
Language (BSDL) and an IEEE 1149.1 working group principal as well as a DR Data Register SVF Serial Vector Format
long time manufacturing and design-for-test expert, this is truly considered DSP Digital Signal Processing/Processor TAP Test Access Port
THE indispensable handbook on boundary scan for the design and/or test TBC Test Bus Controller
EDA Electronic Design Automation
engineer. TCK Test Clock
eTBC Embedded Test Bus Controller
■ Boundary-Scan Test - A Practical Approach, Harry Bleeker, Peter van den Eijnden, TDI Test Data Input
FPGA Field-Programmable Gate Array
Frans de Jong, Kluwer Academic Publishers, ISBN 0-792-9296-5. HSDL Hierarchical Scan Description Language TDO Test Data Output
— Authored by several JTAG and IEEE 1149.1 working group principals, this TMS Test Mode Select
ICE In-Circuit Emulation
book is a ready reference to boundary-scan technology, its benefits, and ICT In-Circuit Test TRST Test Reset
considerations for design and test managers and engineers. UUT Unit Under Test

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Topic 8 - JTAG Boundary Scan

Standard Approach To Test

JTAG / IEEE 1149.1

Standard Test Access Port ... … and Boundary-Scan

TAP ■ Chip-Internal Scan: Partitions

— user-defined data registers

The Incredible Shrinking

Yesterday Today Tom orrow ?

Can’t Afford Not To Test

1. Device level 1 unit of cost

Methods of rather than structure

■ Test generation primarily

■ Test access limited to

Conventional Methods Conventional Methods

The Boundary Scan Idea

■ ‘In-Circuit’ test points moved

Idea ■ Observe/Control cells provide

The Boundary Scan Idea Boundary Scan Method

■ Scan provides a means CORE CORE

to arbitrarily observe ■ Based on board structure;

■ Scan method requires ■ Test access is not limited

Boundary Scan Method The Boundary Scan Cell

automated; Simple CORE

The Test Access Port Controller

■ Data is scanned from TDI to — SCAN-DR

The Extest Instruction The Sample/Preload Instruction

The Bypass Instruction

■ Provides for abbreviated scan

CORE ■ Output and input pins operate

Interconnect Test Interconnect Test

■ Not all nets are bound by

■ Parallel access reduced ■ Expense and complexity reduced

Logic Cluster Test Logic Cluster Test

■ Deterministic test stimulus Control

driven to cluster from B/S

■ Test response can be captured

can be used for increased test ‘LVT18502 Data

Memory Test Memory Test

1B3 1A3 D2 A2 1Y3 1A3

TMS TCK TMS TCK

■ Test response can be captured at

■ TAP-addressable interface unit

Real Applications of the TAP Design Verification/Debug

Access built-in self-test (BIST)

Manufacturing Test System Configuration

generation reduces test via ISP, etc.

diagnostic and upgrade

TI’s JTAG Educational Products IEEE Standards

■ IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), IEEE Standard

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