Professional Documents
Culture Documents
Resource Management
Multitasking
Pause
(a) State transition diagram
Queue
Enter Dispatch Exit
Processor
Pause
Time-out
Event Event
Occurs Wait
Blocked
Process Resource Management
Memory
I/O
all Policies
Ti ⎝ ⎠ 2 0.828
3 0.779
Sufficient 4
5
0.756
0.743
∞ 0.693
Example on handout
Response Analysis for RM
Highest priority process
R1 = C1
Next highest priority process could get
preempted by highest ⎡ R ⎤ times
2
⎢ ⎥
⎢ T1 ⎥
Ceiling function
⎡ 1 ⎤ ⎡ 15 ⎤
⎢⎢ 2 ⎥⎥ = 1, ⎢⎢ 7 ⎥⎥ = 3
Response Analysis cont I
Second highest priority process could be
delayed (at worst) by:
⎡ R2 ⎤
R2 = C 2 + ⎢ ⎥C1
⎢ T1 ⎥
Response Analysis cont II
General priority process i, could get
preempted by any higher priority process j
Worst case response
⎡ Ri ⎤
Ri = C i + ∑ ⎢ ⎥C j
j ⎢T j ⎥
Known OS behaviour
RTOS Responsiveness
An OS provides a uniform interface to the
hardware - including interrupts
When a hardware interrupt occurs, the low-
level interrupt handler is part of the OS
kernel which must then start the ISR
On certain occasions this overhead is
excessive and want interrupt to completely
bypass OS (“fast interrupt response”) - eg
exception conditions
Interrupt response latency
Time between kernel receiving interrupt and
start of first instruction of ISR
Hardware interrupt latency itself is small
global RAM
task 3 code
A000 1A000
task 3 RAM
task 2 code
8000 18000
task 2 RAM
task 1 code
Microkernel