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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO.

11, NOVEMBER 2002 1485

A 44-mm2 Four-Bank Eight-Word Page-Read 64-Mb


Flash Memory With Flexible Block Redundancy and
Fast Accurate Word-Line Voltage Controller
Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba,
Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, and
Shigeru Atsumi

Abstract—The highest bit-density 64-Mb NOR flash memory


with dual-operation function of 44 mm2 was developed by in-
troducing negative-gate channel-erase NOR flash memory cell
technology, 0.16- m CMOS flash memory process technology, and
four-bank hierarchical word-line and bit-line architecture. The
chip has flexible block redundancy for high yield, a fast accurate
word-line voltage controller for a fast erasing time of 0.5 s, and an
eight-word page-read access capability for high read performance
of an effective access time of 30 ns at a wide supply voltage range
of 2.3–3.6 V.
Index Terms—0.16 m, 64 Mb, dual operation, flash memories,
page read, redundancy, voltage controller. (a)

I. INTRODUCTION

H ANDHELD digital equipment such as personal digital as-


sistants is composed of CPU, flash, and other memories.
For simplicity in the system, the power supply should be com-
monly utilized for these devices. As shown in Fig. 1(a), the
power supply voltage for flash memories has been lowered ac-
cording to the reduction trend of the supply voltage for the CPU.
In addition, 3.3-V systems still remain, so that a maximum op-
(b)
erating voltage of 3.6 V is also required. For these reasons, our
target for the supply voltage of NOR flash memory is a wide Fig. 1. Trend of (a) the supply voltage and (b) the capacity for code storage
NOR flash memories.
range of 2.3–3.6 V for using the flash memory in both 2.3–2.7-V
and 2.7–3.6-V systems. Recently, dual-operation flash memo-
ries with read-while-write capability [1] have been standard- column decoders for the independent dual operation, resulting in
ized. By using the dual-operation flash memory, while one bank increased chip size. Considering the balance between the bank
is being programmed or erased, one can simultaneously read flexibility and the chip-size overhead, we developed a NOR flash
data from the other bank. As shown in Fig. 1(b), the capacity of memory with only four banks, namely, two 8-Mb banks and
the code storage flash memory has been required to be 64 Mb two 24-Mb banks. A hierarchical word-line and bit-line scheme
or more for additional data storage. Therefore, our target for the with three metal layers can be utilized even for dual opera-
capacity of code and data storage dual-operation function NOR tion. In addition, we introduced a negative-gate channel-erasing
flash memory is 64 Mb with the world’s highest bit density. NOR flash memory technology [2], [3] along with an aggres-
The conventional dual-operation NOR flash memory is par- sively scaled NAND flash process technology [4]. As a result,
titioned into 16 4-Mb partitions so that users can choose the the 64-Mb flash memory achieves 0.78 chip size using a small
optimal size of the code and data partitions for their applica- memory cell with 0.84 cell size in comparison with those in
tions. However, each 4-Mb partition has to have its own row and [1]. A flexible block redundancy scheme realizes high yield for
channel erasing flash memories and a fast accurate word-line
voltage controller results in a short programming and erasing
Manuscript received March 12, 2002; revised May 11, 2002.
T. Tanzawa, A. Umezawa, T. Taura, H. Shiga, T. Hara, Y. Takano, time. Moreover, in order to meet the demand for fast instruction
K. Watanabe, H. Watanabe, K. Masuda, K. Naruke, H. Kato, and S. Atsumi are transaction for high-performance handheld digital equipment,
with the Toshiba Corporation, Yokohama 247-8585, Japan. the chip has eight-word page-read capability.
T. Miyaba and N. Tokiwa are with the Toshiba Microelectronics Corporation,
Yokohama 247-8585, Japan. The chip arcitecture is described in Section II. Section III
Digital Object Identifier 10.1109/JSSC.2002.802356 explains three features, i.e., flexible block redundancy for
0018-9200/02$17.00 © 2002 IEEE
1486 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002

selected by the main decoder and one of the decoded signals


YMBLK0-7, and connected to the read metal3 data lines, which
are shared by Bank 0 and Bank 1 or Bank 2 and Bank3 using
three metal layers. In program or program verify modes, one of
the global column gates connects 16 global bit lines among 128
global bit lines to 16 metal1 program/verify data lines. Thus,
two neighbor banks, Bank 0, 1 and Bank 2, 3, share the read
data lines with a large bandwidth of 128 b. As a result, the hi-
erarchical word-line and bit-line architecture with the column
decoding scheme can be utilized even for dual operation and
achieve a minimum chip size of 44 mm for 64 Mb capacity.
The next concern for reducing the chip size is the flash cell
technology. Fig. 4 shows the advantage of the channel erase cell
Fig. 2. Tradeoffs between bank flexibility and chip size. over the conventional source erase cell. Source erasure occurs
at the gate–source overlap region. In order to reduce the hot
hole generation rate, source erase cells must have a deep source
high yield, a fast accurate word-line voltage controller for a
region with a depth of about 0.1 m. On the other hand, the
fast erasing time of 0.5 s, and eight-word page-read access
channel erase cell is not required for a deep source region [2],
capability for high read performance of an effective access time
[3]. Therefore, the cell size of the channel erase cell is 15%
of 30 ns at a wide supply voltage range of 2.3–3.6 V. Measured
smaller than that of the source erase cell, resulting in a small
results are presented in Section IV.
cell size of 0.27 m . On the other hand, the process cost for
the channel erase cell is the same as that for the source erase
II. CHIP ARCHITECTURE cell. This is because the double-well process for the memory
Fig. 2 compares the tradeoffs between bank flexibility and cells is shared with that for the high-voltage transistors.
chip size. The conventional chip [1] is partitioned into 16 4-Mb Fig. 5 summarizes our approach for reducing the chip size.
partitions so that users can choose the optimal size of the code Considering the balance between the bank organization and
and data partitions for their applications. However, each 4-Mb chip-size overhead, we divided the 64-Mb flash into four banks
partition must have its own row decoder for the independent dual with irregular ratios of 1 : 3 : 3 : 1, resulting in a 15% smaller
operation. In this bank organization, a hierarchical word-line ar- chip size compared with the conventional bank architecture.
chitecture cannot be utilized even with three metal layers, re- In addition, by introducing the channel erase cell technology,
sulting in an increase in chip size of about 15% in comparison 7% smaller chip size can be achieved. As a result, we realized
with the conventional nondual operation flash memory. Thus, a 22% smaller chip size.
users must pay a high cost for dual-operation flash. Considering
the balance between the bank flexibility and the chip-size over- III. CHIP FEATURES
head, we developed a NOR flash memory with only four banks,
namely, two 8-Mb banks and two 24-Mb banks. This chip can be A. Flexible Block Redundancy
partitioned into four types of combination, that is, 8 Mb and 56 In this subsection, a unique flexible block redundancy scheme
Mb, 16 Mb and 48 Mb, 24 Mb and 40 Mb, and two 32-Mb areas for the channel-erase flash memory is described.
for code and data areas. A hierarchical word-line and bit-line ar- Fig. 6(a) explains the effectiveness of row redundancy for the
chitecture with three metal layers can be utilized even for dual source erase cell. In erase operation, most of the word lines ex-
operation, because of the small number of banks. Therefore, cept for a repaired row are biased at 7 V. The electrons are
users who satisfy the minimum bank size of 8 Mb can cut the ejected from the floating gates to the source regions biased at
flash cost by 15%. 6 V, resulting in erasure. On the other hand, the word line is set
Fig. 3 illustrates the chip architecture. A capacity of 64 Mb to 0 V for a repaired row. Even though the cross failure occurs
is divided into 127 64-kb normal blocks, each of which has 1 k between a word line and a bit line, dc current does not flow in
word lines 512 bit lines, and 8 8 KB boot blocks, each of the erase operation. Therefore, the row redundancy is effective
which has 128 word lines and 512 bit lines. Every eight blocks for source erase cell. Fig. 6(b) shows the ineffectiveness of row
share the global decoder and define the main block. The block redundancy for the channel erase cell. For the channel erase op-
decoder decodes local metal1 bit lines and local WSi word lines eration, the common source and p-well are biased at 10 V. Most
in combination with the global decoder, which decodes global of the word lines except for a repaired row are biased at 7 V.
metal2 word lines and column decoding signal lines. Bank 0 The electrons are ejected from the floating gates to the p-well
has two main blocks, each of Bank 1 and Bank 2 has six main region, resulting in erasure. When the cross failure occurs be-
blocks, and Bank 3 has two main blocks and eight boot blocks. A tween a word line and a bit line, the repaired row is biased at
user can select any sets of 8 Mb from four combinations for code 0 V. However, the bit-line voltage rises up to about 9 V from the
and data storage partitions. Each of four neighbor local bit lines p-well through p-n junction at the bit-line contact. As a result,
is connected to a global metal3 bit line. Thus, 512 local bit lines dc current does flow in the erase operation and the well voltage
in a selected block are decoded to 128 global bit lines, which of 10 V drops. This results in block failure. Thus, row redun-
correspond to one page of eight words. The global bit lines are dancy is ineffective for the channel erase cell. Therefore, block
TANZAWA et al.: 64-Mb FLASH MEMORY WITH FLEXIBLE BLOCK REDUNDANCY AND FAST ACCURATE WORD-LINE VOLTAGE CONTROLLER 1487

Fig. 3. Chip architecture.

Fig. 4. Advantage of the channel erase cell over the conventional source
erase cell.
Fig. 5. Our approach for reducing the chip size.

redundancy has to be introduced for the channel erase cell in-


stead of row redundancy. Table I summarizes repairability for To repair any block, each redundancy block must independently
various short failure modes. The “1’s” and “0’s” represent re- connect the local bit lines to the data lines. If two or more re-
pairable and unrepairable, respectively. In particular, the cross dundancy blocks share the global bit lines, these blocks have to
failure such as word line to bit line short or word line to source have the same bank address. This can lower the redundancy effi-
line short can be replaced only by block redundancy. In addition ciency. Therefore, four redundancy blocks must be located next
to block redundancy, the chip utilizes the conventional column to 128 data lines at the chip center, as shown in Fig. 7. In addi-
redundancy because of its high area efficiency for column fail- tion, each redundancy block must have its own row and column
ures in comparison with the block redundancy. As a result, the decoders and voltage switch in order to operate independently.
channel erase NOR flash can be perfectly replaced by block re- As a result, most of the peripheral circuits are also placed at
dundancy and column redundancy. the chip center. Although the chip has eight-word sense ampli-
In order not to restrict the flexibility of the block redundancy, fiers to simultaneously sense and latch a page data of 128 b, the
each redundancy block should replace any block in any bank. highest bit density of 44 mm for 64-Mb capacity was realized.
1488 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002

TABLE I
REPAIRABLE SHORT MODES IN THE CHANNEL-ERASING NOR FLASH MEMORY

(a)

(b)
Fig. 6. Effectiveness of row redundancy for (a) source erase cell and (b) in-
effectiveness of row redundancy for channel erase cell. Fig. 7. Die photo.

One may have a question; which combination is better, large


source erase cell with small row redundancy or small channel
erase cell with large block redundancy? Fig. 8 compares the en-
tire chip size including redundancy cell area. It is assumed that
one spare per 128 global word lines and 64 bit lines is prepared
for source erase cell and one spare per 32 blocks and 64 bit lines
is prepared for channel erase cell in order to be same yield. As
mentioned above, cell area for channel erase cell is 15% smaller
than that for source erase cell. As a result, the cell area for
channel erase cell occupies 40% of the entire chip, whereas the
cell area for source erase cell is 7% larger than that for channel
erase cell. Although the redundancy area for channel erase cell
is 2.3% larger than that for source erase cell, the entire cell area
for channel erase cell is 4.7% smaller than that for source erase Fig. 8. Comparison of the entire chip size including redundancy cell area
cell. Therefore, the channel erase cell is still cost-effective even between source erase cell and channel erase cell.
with including the redundancy area.
When the repaired block is selected for read, the hit verify and step-up weak programming are repeated for an entire
signal “HITBLKB” deselects the main block address signals block erase [3]. In addition, a programming voltage of 10 V is
“MBLKi” and the bank address “BANKi,” and the redundancy applied to the word lines. Thus, the word line has to be con-
block selection signal “BRDi” selects the repaired cells in the trolled within a wide voltage range of 2–10 V. Furthermore,
redundancy block (see Fig. 3). On the other hand, when the the word-line controller should output various voltage levels of
repaired block is selected for programming or erasing, another about 10 for the operations such as program-, erase-, and over-
control method is required for a word-line voltage controller, erase-verify, and step-up weak-program. Moreover, the word
as explained in the next subsection. line has to be controlled with a fast transient time of less than
1 s for short entire erasing time. Fig. 9 illustrates a voltage reg-
B. Word-Line Voltage Controller ulator using DAC with an R-2R ladder structure, which was pro-
NOR flash should have tight erased threshold voltage distri- posed in [5]. The DAC utilizes summation of binary weighted
bution with short entire erasing time. To realize this, over-erase currents rather than summation of voltages to vary the output
TANZAWA et al.: 64-Mb FLASH MEMORY WITH FLEXIBLE BLOCK REDUNDANCY AND FAST ACCURATE WORD-LINE VOLTAGE CONTROLLER 1489

Fig. 11. Proposed regulator.

Fig. 9. Conventional voltage regulator using DAC with an R-2R ladder struc-
ture proposed in [5].

Fig. 12. Simulated waveforms for word-line voltages.

ranges using the three selection signals E2, E4, and E5. By in-
Fig. 10. Necessary and sufficient condition for the word-line voltage controller putting data of 5 bits, the word-line voltage can be set to one of
used in the NOR flash memory.
32 levels in every operation mode, resulting in 0.25 V resolu-
tion. The number of bits is variable to tighten the range in cur-
voltage. Thus, the output voltage is proportional to the pen- rent flowing through the resistor between Imin and Imax. This
etration current I(DAC). The conventional DAC has a voltage scheme can achieve relatively small parasitic capacitance and
ratio between a maximum voltage and a minimum voltage necessary and sufficient current flowing through the resistor in
of about 2. However, as mentioned above, the word-line the voltage divider, resulting in fast transient speed and small
controller has the voltage ratio of 5 ( 10 V/2 V). power consumption.
When the conventional DAC is applied to the word-line Another problem in the word-line voltage controller is con-
voltage controller used in the NOR flash, the word-line voltage trolling the redundancy block. Each redundancy block is sepa-
controller will have a problem, as illustrated in Fig. 10. In case rated from other blocks and has a small load capacitance, as ex-
I, in order to achieve fast transient time, sufficient penetration plained in Section III-A. In comparison with the normal block,
current through the resister ladder is required at the minimum the load capacitance for the redundancy block is only 15%.
output voltage. However, requirement of a large penetration As a result, if the transient time for the normal block were set
current at the maximum output voltage would increase the to less than 1 s, the word-line voltage would oscillate in the
power consumption and the charge pump circuit area. On the case of selection of the redundancy block because of its light
other hand, in case II, in order to achieve low power and small load, as shown by case 2 in Fig. 12. This would broaden the
charge pump circuit area, the penetration current through the erased threshold voltage distribution and consume much power.
resister ladder at the maximum output voltage is required to In order to match drivability of the word-line voltage controller
be sufficiently small. However, the requirement of a small and load capacitance when a repaired block is selected for pro-
penetration current at the minimum output voltage would gramming or erasing, we developed a scheme, as illustrated in
decrease the response and prolong the program/erase time. Fig. 13. When a normal block is selected for programming or
Thus, the conventional DAC cannot be applied to the word-line erasing, only the voltage switch for the normal block opens.
voltage controller for the NOR flash memory. The voltage controller drives the load capacitance of 1. On the
To realize both low power consumption and fast transient op- other hand, when a redundancy block is selected for program-
eration, a word-line voltage controller was proposed in Fig. 11. ming or erasing, both the voltage switches for the redundancy
The number of bits in the ladder is variable for three voltage and normal blocks open. The voltage controller drives the load
1490 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002

Fig. 13. Control scheme for block redundancy.

TABLE II
KEY FEATURES

(a) (b)
Fig. 14. Measured word-line voltage waveforms in (a) program mode and
(b) weak-program mode.

capacitance of 1.15. By using this block redundancy control


scheme, the load capacitance for the voltage controller is ap-
proximately constant whether or not the redundancy block is
selected, as indicated by case 1, 3 in Fig. 12. As a result, the in-
ternal voltage can be stably controlled with approximately con-
stant transient time.

C. Eight-Word Page-Read Access


In order to meet the demand for fast instruction transaction
for high-performance handheld digital equipment, the chip has
eight-word page-read capability. After random access is fin-
ished within 70 ns, the page mode operation provides a fast page
access of any locations within the page within 25 ns. Address Fig. 15. Measured waveforms for read operation.
transition detection (ATD) achieving internal timing generation
and automatic power-down is an indispensable technique for IV. MEASURED RESULTS
low-power asynchronous flash memories [6]. The access time of The 64-Mb dual operation flash memory was fabricated in a
the flash memory is the sum of the access time without ATD and 0.16- m shallow trench isolation [4], P-substrate, triple-well,
the timing margin of the ATD pulse. The former represents the CMOS, double-polysilicon, triple-metal flash memory tech-
device’s ability without timing, which is given by gate delay, CR nology, as shown in Table II.
of wires, word-line and bit-line delay, sense amp delay and I/O Fig. 14(a) and (b) show the measured word-line waveforms
buffer delay. The latter is the sum of the margins for the pulses at 2.3 V and room temperature. The controller achieves 700
with Vcc-, temperature-, and process-fluctuations. Timing ad- ns accurate word-line voltage transient for each transition such
justment of the ATD pulse is made under the fastest condition as program-to-program verify transition or over erase verify to
without ATD pulse, otherwise a timing mismatch may occur. weak-program transition. As a result, a tight erased threshold
It is essential to minimize the timing margins for high-speed voltage distribution can be obtained with a 0.5-s entire erasing
flash memories. For these reasons, the pulse control circuit uti- time.
lizes the stable delay circuit developed in [7] for a wide supply Fig. 15 shows the measured waveform for read operation
voltage range of 2.3–3.6 V. at 2.3 V and 85 C. An address access time of 58 ns
TANZAWA et al.: 64-Mb FLASH MEMORY WITH FLEXIBLE BLOCK REDUNDANCY AND FAST ACCURATE WORD-LINE VOLTAGE CONTROLLER 1491

REFERENCES
[1] B. Pathak, A. Cabrera, G. Christensen, A. Darwish, M. Goldman, R.
Haque, J. Jorgensen, R. Kajley, T. Ly, F. Marvin, S. Monasa, Q. Nguyen,
D. Pierce, A. Sendrowski, I. Sharif, H. Shimoyoshi, A. Smidt, R. Sun-
daram, M. Taub, W. Tran, R. Trivedi, P. Walimbe, and E. Yu, “A 1.8 V
64 Mb 100 MHz flexible read while write flash memory,” in ISSCC Dig.
Tech. Papers, Feb. 2001, pp. 32–33.
[2] H. Watanabe, S. Yamada, M. Matsui, S. Kitamura, K. Amemiya,
T. Tanzawa, E. Sakagami, M. Kurata, K. Isobe, M. Takebuchi, M.
Kanda, S. Mori, and T. Watanabe, “Novel 0.44 m Ti-Salicided STI
cell technology for high-density NOR flash memories and high per-
formance embedded application,” in IEDM Dig. Tech. Papers, 1998,
pp. 975–978.
[3] S. Atsumi, A. Umezawa, T. Tanzawa, T. Taura, H. Shiga, Y. Takano, T.
Miyaba, M. Matsui, H. Watanabe, K. Isobe, S. Kitamura, S. Yamada, M.
Saito, S. Mori, and T. Watanabe, “A channel-erasing 1.8 V-only 32 Mb
NOR flash EEPROM with a bit-line direct-sensing scheme,” in ISSCC
Fig. 16. Measured random access shmoo plot. Dig. Tech. Papers, Feb. 2000, pp. 276–277.
[4] S. Aritome, “Advanced flash memory technology and trends for file
storage application,” in IEDM Dig. Tech. Papers, Dec. 2000, pp.
and a page access time of 20 ns were realized. Thanks 763–766.
to eight-word page read mode, an effective access time of [5] T. Miyakawa, S. Tanaka, Y. Itoh, Y. Takeuchi, R. Ogiwara, S. Mano
25 ns is available with pin-compatibility with conventional Doumae, H. Takenaka, I. Kunishima, S. Shuto, O. Hidaka, S. Ohtsuki,
and S. Tanaka, “A 0.5 m 3 V 1T1C 1 Mb FRAM with a variable ref-
asynchronous flash memories, that is, no additional pins and erence bitline voltage scheme using a fatigue-free reference capacitor,”
wires for board design. Fig. 16 shows the measured read access in ISSCC 1999 Dig. Tech. Papers, Feb. 1999, pp. 104–105.
shmoo plot at 85 C. Stable read access is realized in a wide [6] D. Hoff, S. Pathak, J. Payne, R. Shrivastava, J. I. Arreola, C. Norris,
S. C. Tsao, B. L. Prickett, and M. Orput, “A 23-ns 256 K EPROM with
voltage range between 2.3 and 3.6 V. The chip has the ability to double-layer metal and address transition detection,” IEEE J. Solid-State
accomplish a read access time of 58 ns at 2.3 V. Circuits, vol. 24, pp. 1250–1258, Oct. 1989.
Chip features are summarized in Table II. Users can choose [7] T. Tanzawa and T. Tanaka, “A stable programming pulse generator for
single power supply flash memories,” IEEE J. Solid-State Circuits, vol.
word or byte mode and four types of bank combination. This 32, pp. 845–851, June 1997.
chip can be stacked with a maximum of four other memories
such as SRAMs and PSRAMs into one package.
Toru Tanzawa received the B.S. degree in physics
V. CONCLUSION from Saitama University, Japan, in 1990, the M.S.
degree in physics from Tohoku University, Japan, in
Considering the balance between chip size and bank flexi- 1992, and the Ph.D. degree in electrical engineering
from the University of Tokyo, Japan, in 2002, respec-
bility, four-bank hierarchical word-line and bit-line architecture tively.
with channel erase cell technology for dual operation NOR flash In 1992, he joined the Toshiba Research and De-
memories was developed. As a result, the chip has the highest velopment Center, Kanagawa, Japan. Since then, he
has been working on the circuit design of high-den-
bit density of 44 mm for 64-Mb dual operation NOR flash sity flash memories. He is now working on the cir-
memory. Also, a flexible block redundancy scheme for channel cuit design of low-voltage low-power flash memories
erase NOR flash memory cell was developed. This combination at the Memory LSI Research and Development Center, Toshiba Corporation,
Yokohama, Japan.
offers a small chip size and high yield for the NOR flash memory.
Moreover, the fast accurate word-line voltage controller was
presented. The controller and block redundancy control scheme Akira Umezawa was born in Tokyo, Japan, on
realized a fast erasing time of 0.5 s. Furthermore, the chip has September 15, 1965. He received the B.S. degree
eight-word page read capability. The random access time of 70 ns in metallurgical engineering from the University of
Tokyo, Tokyo, Japan, in 1989.
and the following page read access time of 25 ns result in 30 ns In 1989, he joined the Toshiba Semiconductor
effective read speed in a wide supply voltage range of 2.3–3.6 V Device Engineering Laboratory, Toshiba Corpora-
for using the flash in both 2.3–2.7 V and 2.7–3.6 V systems. tion, Kawasaki, Japan, where he has designed and
developed such nonvolatile memories as EPROMs
These technologies will be able to realize larger capacity NOR and NOR flash memories. He is now working
flash memory with a high-performance wide-range operation. on the circuit design of low-voltage low-power
flash memories at the Memory LSI Research and
Development Center, Toshiba Corporation, Yokohama, Japan.
ACKNOWLEDGMENT
The authors wish to thank M. Kuriyama, H. Saito, T. Ikeda,
Y. Honda, K. Kinjyo, S. Matsuda, K. Shibayama, S. Tuda, Tadayuki Taura was born in Nagasaki, Japan, on
H. Kobayashi, K. Mitsutake, S. Mori, S. Miyawaki, K. Suzuki, April 9, 1966. He graduated from Shimabara Tech-
nical High School in 1985.
S. Maeda, T. Hirota, T. Shimotori, Y. Bando, A. Uchida, In 1985, he joined the Memory Division, Toshiba
R. Kirisawa, S. Mori, E. Sakagami, K. Narita, M. Momodomi, Corporation, Kawasaki, Japan, where he has been en-
H. Sasaki, M. Asano, Y. Homma, K. Kobayashi, Y. Oowaki, gaged in the circuit design of nonvolatile memories.
Now, he is working on the circuit design and devel-
and J. Miyamoto for discussion on design and integration. The opment of NOR type flash memories.
authors also appreciate the reviewers for their comments and
suggestions.
1492 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002

Hitoshi Shiga was born in Matsuyama, Japan, on Hiroshi Watanabe was born in Fukushima, Japan,
Februay 9, 1971. He received the B.S. and M.S. in 1966. He received the B.E. and M.E. degrees in
degrees in physics from Kyoto University, Kyoto, applied physics from the University of Tokyo, Japan,
Japan in 1994 and 1996, respectively. in 1990 and 1992, respectively.
In 1996, he joined the Microelectronics Engi- In 1992, he joined the Toshiba Research and De-
neering Laboratory, Toshiba Corporation, Yokohama, velopment Center, Kanagawa, Japan. Since then he
Japan, where he has been engaged in the research and has been working on the development of high-den-
development of flash EEPROM’s. He is now working sity flash memories, especially in the devise physics
on the circuit design of nonvolatile memories at the and the fabrication technology of NAND and NOR flash
Memory LSI Research and Development Center, memories. Currently, he is with the Memory Divi-
Toshiba Corporation, Yokohama, Japan. sion, Toshiba Corp., Yokohama, Japan.
Mr. Watanabe is a member of the Japan Society of Applied Physics.

Tokumasa Hara was born in Tokyo, Japan, on Jan-


uary 9, 1972. He received the B.S. degree in electrical
engineering from Waseda University, Tokyo, Japan,
in 1996. Kazunori Masuda was born in Fukuoka, Japan, on
In 1996, he joined the Memory Division, Toshiba February 11, 1970. He graduated from Kokura Tech-
Corporation, Kawasaki, Japan, where he has been en- nical High School, Japan, in 1988.
gaged in the circuit design of nonvolatile memories. He joined the Toshiba Semiconductor Device
Now, he is working on the circuit design and devel- Engineering Laboratory, Kawasaki, Japan, in 1988,
opment of NOR type flash memories. where he had been engaged in the development
of high-density EPROM’s and EEPROMs. He is
now working on the products engineering of flash
memories at the Yokkaichi Operations, Toshiba
Yoshinori Takano was born in Tochigi, Japan, on Corporation, Yokkaichi, Japan.
December 2, 1974. He received the B.S. degree in
material engineering from Waseda University, Tokyo,
Japan in 1997.
In 1997, he joined the Microelectronics Engi-
neering Laboratory, Toshiba Corporation, Yokohama, Kiyomi Naruke was born in Hokkaido, Japan,
Japan, where he has been engaged in the research and on March 5, 1958. He received the B.S. degree
development of flash EEPROMs. He is now working in information and communication engineering
on the circuit design of nonvolatile memories at the from the University of Electro-Communications,
Memory LSI Research and Development Center, Japan, in 1980 and the M.S. degree in electrical
Toshiba Corporation, Yokohama, Japan. and electronics engineering from Tokyo Institute of
Technology, Japan, in 1982, respectively.
In 1982, he joined the Toshiba Semiconductor
Takeshi Miyaba was born in Shizuoka, Japan, on Device Engineering Laboratory, Kanagawa, Japan.
April 19, 1969. He received the B.S. degree in elec- Since then he has been engaged in the research and
trical engineering from the University of Ibaragi, Hi- development of byte- and embedded-EEPROMs
tachi, Japan, in 1993. and flash EEPROMs. He is now working on the device integration of flash
In 1993, he joined the Toshiba Microelectronics memories at the Memory Division, Toshiba Corporation, Yokohama, Japan.
Corporation, Kawasaki, Japan, where he has been en-
gaged in the research and development of Flash EEP-
ROMs. Now, he is working on the circuit design and
development of a wireless LAN system LSI.
Hideo Kato was born in Kanagawa, Japan, on
September 19, 1960. He received the B.S. and
M.S. degrees in electrical engineering from Keio
Naoya Tokiwa was born in Kanagawa, Japan, on Au- University, Kanagawa, Japan, in 1983 and 1985,
gust 2, 1971. He received the B.S. and M.S. degrees in respectively.
applied chemistry from Keio University, Yokohama, In 1985, he joined the Memory Division, Toshiba
Japan, in 1994 and 1996, respectively. Corporation, Kawasaki, Japan. He has designed and
In 1996, he joined the Toshiba Microelectronics developed such nonvolatile memories as EPROMs
Corporation, Kawasaki, Japan, where he has and NOR flash memories. He is now working on the
been engaged in the research and development of circuit design of nonvolatile memories.
FeRAMs. Currently, he is working on the circuit
design of NOR-type flash memories.

Shigeru Atsumi was born in Tokyo, Japan, on Au-


Kentaro Watanabe was born in Niigata, Japan, on gust 27, 1957. He received the B.S. degree in applied
Februay 18, 1974. He received the B.S. and M.S. de- physics from the University of Tokyo, Tokyo, Japan,
grees in physical electronics engineering from Tokyo in 1981.
Institute of Technology, Tokyo, Japan in 1996 and In 1981, he joined the Toshiba Semiconductor
1998, respectively. Device Engineering Laboratory, Kawasaki, Japan,
In 1998, he joined the System SLI Division, where he had been engaged in the research and
Toshiba Corporation, Kawasaki, Japan, where he has development of EPROMs. Since 1991, he has been
been engaged in LSI process optimization by using working on the circuit design of NOR type flash mem-
TCAD. Recently, he has also been engaged in SPICE ories. Now, he is responsible for the design of next
models extraction and design kit configuration generation NOR type flash memories at the Memory
support. LSI Research and Development Center, Toshiba Corporation, Yokohama, Japan.