IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO.
4, JULY 2004
Paralleled DSP-Based Soft Switching-Mode
Rectifiers With Robust Voltage Regulation Control
Sheng-Hua Li and Chang-Ming Liaw, Member, IEEE
Abstract—This paper presents the current sharing and robust
voltage regulation controls for paralleled digital signal processor-
based soft switching-mode rectifiers (SSMRs). First, the design and
implementation of single-module SSMRs are made. In dealing with
the current control loop design of each SSMR module, the small-
signal model is derived and used to design the current-controlled
pulse-width modulation (PWM) scheme. As to the common voltage
control loop, its dynamic model is estimated from measurements.
Then, a quantitative design procedure is developed to find the pa-
rameters of the voltage controller according to the prescribed con-
trol specifications. As the changes of parallel number and oper-
ating condition occur, the robust control is added to reduce the
voltage regulation control performance degradation.
The proposed multimodule operation control scheme consists of
a master controller and N slave controllers. The former further
consists of a common voltage controller and a current distribu-
tion unit, and the latter are the current-controlled PWM schemes
of all SSMRs. Each slave controller receives the weighted sinu-
soidal current command from the master controller and regulates
the feedback current of SSMR. The results confirm that the de-
signed parallel SSMR system possesses good line drawn current
power quality, module current sharing and voltage regulation con-
trol performances.
Index Terms—Digital signal processor (DSP)-based digital con-
trol, model estimation, parallel operation, quantitative controller
design, robust control, soft-switching-mode rectifier.
I. INTRODUCTION
T HE SWITCHING-mode rectifier (SMR) can be used to
build up dc-link voltage from utility grid for the followed
power converter stage. By applying power factor correction
(PFC) control, the SMR can be controlled to have good line
drawn current power quality and well-regulated dc output
voltage. Among the existing SMRs [1], the boost-type one is
the easiest to perform line current waveform shaping control.
By applying soft-switching techniques [2]–[4], the switching
stresses, switching losses and electromagnetic interference
(EMI) yielded by the SMR can be significantly reduced.
As generally recognized, sophisticated current and voltage
controls are indispensable for yielding satisfactory power
conditioning control performance for a SMR. Although analog
control [1]–[6] is simple and fast, its flexibility in control law
adaptation is low. Digital control possesses many advantages,
such as without offset and drift effects, having high flexibility
in changing controller structure and parameters, and easy to
Manuscript received December 3, 2002; revised September 9, 2003. This
work was supported by Delta Electronics, Inc., Chungli, Taiwan, R.O.C. Rec-
ommended by Associate Editor P. K. Jain.
The authors are with the Department of Electrical Engineering, National
Tsing Hua University, Hsinchu 30043, Taiwan, R.O.C.
Digital Object Identifier 10.1109/TPEL.2004.830095
0885-8993/04$20.00 © 2004 IEEE
937
perform the adaptive and compensation controls. Due to the
great progress made in microcontrollers, digital control has
been gradually employed in power supplies [7], [8] and SMRs
[9]–[11]. Recently, some specifically designed digital signal
processors (DSPs), which are embedded with pulse-width mod-
ulation (PWM) modulator [12], can further facilitate the digital
realization of controllers. However, proper considerations in
performing digital control should be made to yield performance
being comparable to those of analog controllers [7].
Multimodule operation of converters possesses many advan-
tages, such as
1) the converters can be designed in modular fashion, and
thus the system power capacity can be enlarged more
easily;
2) the system reliability is greatly increased;
3) with proper operation control management, the overall
power conversion efficiency and the life of converter
module can be increased.
During the past decades, a lot of researches concerning the par-
allel operation control of various kinds of converters have been
made by many authors [13]–[19], and a detailed survey can be
referred to [16]. Basically, the parallel current sharing control
can be categorized into two groups, namely the droop method
and the active current sharing method. And according to the con-
troller structure and current-programming approach, the latter
can further be classified into many configurations, each one
has its merits and limitations. As generally recognized, the in-
dividual converter with current-mode control is easier to per-
form current sharing control in parallel operation [14]. As far
as the control scheme realization issue is concerned, it can be
performed via analog, hybrid or fully digital fashion.
Although some parallel operation control methods of SMRs
have been made [17], [19], the dynamic modeling, quantita-
tive and robust controller design and fully digital control using
DSP for parallel SSMRs are still seldom performed till now.
In this paper, the digital parallel operation control with quan-
titative and robust control performance of multimodule paral-
leled single-phase SSMR system is studied. The proposed par-
allel operation control scheme consists of a master controller
and n slave controllers. The former further consists of a common
voltage control loop and a current distribution unit (CDU), and
the n slave controllers are basically the current-controlled PWM
schemes of the SSMRs to be parallel connected.
In this paper, the single-module SSMRs and their switching
schemes are first designed and implemented. For each module,
the dynamic model of its current-loop is derived, and then the
frequency response method is used to design the current-con-
trolled PWM scheme. As to the design of common voltage
938 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 4, JULY 2004

Fig. 1. System configuration of the proposed DSP-based paralleled SSMRs.

controller, the dynamic model is estimated from measurements

[20]. Then the governing equations relating to the controller
parameters and control specifications are derived, and they are
employed to find the controller parameters systematically and
quantitatively. As the changes of paralleled module number and
system parameters occur, a simple robust controller is further
added to reduce the performance degradation. The voltage
controller and the current-controlled PWM schemes are all
realized in an ADMC401 DSP-based control environment,
wherein the PWM switching signals are generated directly
from the DSP.

II. DSP-BASED PARALLELED SSMR SYSTEM

Configuration of the proposed DSP-based paralleled SSMR
system is shown in Fig. 1, the power circuits of all SSMRs
are connected in parallel with the features of common input
ac source and common load bus. The control system is cas-
cade arrangement with all its constituted parts being realized
using the ADMC401 DSP manufactured by Analog Devices
Company. Due to the close current tracking control possessed
by the individual SSMR, good current sharing control perfor-
mance under well-regulated output voltage can be yielded by the
system shown in Fig. 1, which is briefly described as follows.
A. Master Controller
The master controller consists of a common voltage control
loop and a current distribution unit. The voltage controller yields
a current magnitude command through regulating the voltage
tracking error. Then by multiplying with a unit sine wave
, which is synchronized with the utility voltage source ,
a total current command is generated.
In the CDU, the current command for SSMR module
is generated according to [14]
(1)
where denotes the current sharing weighting factor of
module, and is the number of parallel modules. Through
Fig. 2. ZVT SSMR module: (a) power circuit and (b) ZVT soft-switching
current-controlled PWM scheme.
properly arranging the values of , , ac-
cording to the ratings of SSMR modules, the parallel operation
of SSMRs with different ratings becomes possible.
B. Slave Controllers
Thanks to the great progress made in the DSP development
in the past years, the computation and signal processing capa-
bilities of an DSP have been significantly improved. Moreover,
some specifically designed DSPs are equipped with embedded
PWM modulators. These significantly facilitate the fully digital
realization of control system. Accordingly, the slave controllers
of the proposed parallel control scheme contain the current
controllers and the soft-switching signal generating schemes
of all SSMR modules. In each slave controller, its line input
current is regulated to closely follow its command . Then
the switching signals and for the SSMR are generated
and directly outputted from the PWM modulator embedded in
the DSP.
The power circuit and its current-controlled PWM scheme
with ZVT soft-switching of each SSMR module are shown in
Fig. 2(a) and (b), respectively. For concision, the subscripts of
all variables in Fig. 2(a) and (b) for identifying the number of
module are neglected. Detailed description about the design of
LI AND LIAW: PARALLELED DSP-BASED SOFT SWITCHING-MODE RECTIFIERS 939

power circuit and control schemes will be given in the following

sections.
The digital control law design approaches can be roughly
classified into the redesign and direct digital design. For a DSP-
based digital control system, its response behavior will be very
close to those yielded by analog control due to high sampling
rate. And moreover, the derivations in making the controller
analysis and design are easier to do in continuous domain. If fol-
lows that the redesign approach is employed here to perform the
controller design. The bilinear transformation method is applied
to perform the model transformation, and the sampling rates for
the current and voltage control loops are chosen to be 30 kHz
and 300 Hz, respectively.

III. DSP-BASED SSMR MODULE

The developed DSP-based SSMR shown in Fig. 2(a) consists
of a boost-type SMR and an auxiliary branch (including ,
, , , ). The soft switching of the main switch is ob-
tained by employing the zero voltage transition (ZVT) technique
[2]. This is achieved by slightly delaying the turn-on instant of
the PWM switching signal for the main switch. The generation
of switching signals for the main and auxiliary switches of the
single-module SSMR is illustrated in Fig. 2(b).
According to the inherent features of the boost-type SMR, the
following specifications are given.
Input voltage: V, 60 Hz.
Power factor improved: .
Maximum output power: W.
Output dc-link voltage: V.
Switching frequency: kHz.
Efficiency: .
In the research made in this paper, the constant voltage of Fig. 3. Some key switching waveforms of the ZVT SSMR within one
V is assumed. The design and implementation of the cir- switching period.
cuit and control scheme of this SSMR are briefly described as
followed.
According to (3) and (4), the boosting inductance is obtained
A. Boost Converter as

1) Boosting Inductance: The boost converter is design to

operate in continuous conduction mode owing to its many ad- mH (5)
vantages, and the ramp-comparison current-controlled PWM
scheme is employed. In performing the design, it is assumed that The measured inductance of the designed boosting inductor is
the line current is regulated to be sinusoidal and kept in phase 1.2 mH at 30 kHz.
with the input voltage. Accordingly, the maximum amplitude of 2) Output Capacitor: The output dc capacitance is deter-
the input current can be found from the given specifi- mined according to the hold-up time . Assume that
cations as and V, then

A
(2)
F (6)
Let the current ripple be

A (3) Pick F V.
3) Power Semiconductor Devices: Based on the above anal-
Since V and the minimum peak value of (or )
ysis, the maximum current flowing through the main switch
is 140 V, the maximum duty ratio can be found by neglecting
and the diode is A, and their
the diode voltage drop to be
maximum voltage is 300 V. Accordingly, the power MOSFET
IRFP460 and the fast diode RURP3060 are chosen for the main
(4) switch and the diode , respectively.
940 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 4, JULY 2004

equal to , the diode is naturally turned off. The time

interval of this mode can be found to be

(7)

Mode 2:
As shown in Fig. 4(c), the resonant inductance and
the resonant capacitor form a resonant tank. The current
is increased from , while the voltage across the
main switch is decreased from . The solutions of and
can be derived to be

(8)

where

(9)

This mode is terminated as becomes zero, and the in-

terval is found from (8) and (9) to be

(10)

The maximum value of can be found as

(11)

Mode 3:
As the voltage across the resonant capacitor becomes
slightly negative, the diode in parallel with the main
Fig. 4. (a)–(g) Circuit configurations and current paths of mode 0 to mode 6.
switch conducts. The current path of this mode is shown
in Fig. 4(d). If the main switch is turned on during this
B. Auxiliary Resonant Branch interval, the ZVT soft switching can be achieved. The key
variables in this case are
1) Circuit Operation: The operation of this SSMR can be
divided into seven modes [2]. The typical current and voltage
(12)
waveforms are sketched in Fig. 3, and the circuit configurations
of all modes are shown in Fig. 4(a)–(g). As shown in Fig. 3, the
turn-on instant of the main switch PWM switching is delayed Observations:
by a short time interval , and within which the switching of From Fig. 3, it is obvious that to achieve the ZVT
auxiliary switch is inserted. In performing the analysis, the fol- switching of main switch, the delay time should satisfy
lowing assumptions are given: the following condition:
1) the input current and the output voltage
are constant within a short switching cycle; (13)
2) all the voltage drops of switches and diodes are neglected;
3) the resonant capacitance is the sum of the parasitic To satisfy (13) under any condition, the peak value of at
capacitance of the main switch and the externally added rated load denoted by should be used, and a small
capacitance. time margin is used to set the delay time
Mode 0:
As shown in Fig. 4(a), the main and auxiliary switches (14)
are both off. The input current flows to the load through
the diode D. In this case, and . Mode 4:
Mode 1: At , and are forced to turn on and turn off, respec-
As illustrated in Fig. 3 and Fig. 4(b), the auxiliary switch tively. The energy stored in is demagnetized and ener-
is switched on before the main switch at , the reso- gizes the load through the diode , and meanwhile the
nant inductance current is linearly increased. As is voltage across the auxiliary switch is held constant at
LI AND LIAW: PARALLELED DSP-BASED SOFT SWITCHING-MODE RECTIFIERS 941

. Circuit configuration of this mode is drawn in Fig. 4(e).

One can find that , and the current is

(15)

During the interval between and , the current is

linearly decreased from the value of to zero,
and meanwhile the current is linearly rised from
to . At the end of this mode, the voltage
jumps from to zero. By letting the current listed
in (15) be zero, the following time interval is found

(16)

Mode 5:
As the current reduces to zero at , the diode is
naturally turned off, the resulted current path is plotted in
Fig. 4(f).
Mode 6:
As shown in Fig. 4(g), the main switch is turned off at
causing the input current to charge linearly. As the
voltage reaches to , the diode D is naturally turned
on, , proceeding to mode 0.
2) Circuit Design:
a) Resonant branch components and delay time: It
should be noted that during mode 3 the current Fig. 5. Simulated voltage and current waveforms of the ZVT SSMR within
flowing through the anti-paralleled diode of the main one switching period (I = 10:083 A, V = 300 V, and P = 600 W).
switch is . Thus this current must also be
considered in determining the resonant branch components. By
waveforms are not shown here. Fig. 5 shows some measured
neglecting the high-frequency components, the maximum input
waveforms of the main switch and auxiliary switch of the
occurs at the minimum of the input voltage ,
designed SSMR. The results indicate that they are very close to
and it can be obtained from (2). It follows from (12), (13) and
the predicted ones.
the previous analysis that the determination of and can
be made according to the following conditions:
IV. CONTROL SCHEME
(17) A. Current Loop of Individual SSMR Module
1) Dynamic Modeling: The following assumptions are rea-
(18) sonably made in performing the modeling:
1) the switching behavior of the auxiliary switch is neglected
where A from (2). The parasitic capacitance owing to its relatively much small operating time com-
of the adopted power device for main switch is 0.48 nFnF at pared with those of main switch;
30 kHz. Thus nF for without adding external reso- 2) since the line frequency is much lower than the switching
nant capacitance. By giving H and s, one can frequency, the input voltage can also be regarded as con-
find s, s, and A, stant over a switching time period.
which all meet the requirements. Accordingly, by applying the state-space averaging approach,
b) Power semiconductor components: Based on the the transfer function block diagram of current control loop is
above analysis, the maximum current and voltage of and derived and shown in Fig. 6, wherein the key parameters and
are A and 300 V, respectively. variables are listed as follows:
Accordingly, the power MOSFET IRFP 460 and the fast diode input voltage variation;
RURP 3060 are also chosen for and , respectively. duty ratio of PWM;
current sensing factor;
C. Simulated and Measured Results load transfer function;
Before performing the implementation, the Pspice simulation load resistance;
has been made to check the validity of the designed SSMR. The transfer ratio of the PWM
waveforms and the key values of the simulated variables are all modulator;
close to those by derivation. For saving the space, the simulated where V/A and are set.
942 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 4, JULY 2004

Fig. 6. Current loop control system block diagram of the SSMR.

Fig. 7. Current loop Bode plots.

The transfer function from to in s-domain can be

derived from Fig. 6 to be

(19)
2) Current Controller Design: For the ramp-comparison
current-controlled PWM scheme, the condition for normal
switching operation is that the time derivative of the control
Fig. 8. (a) Control system block diagram of voltage control loop, (b) the
signal should be smaller than the slope of triangular proposed control scheme, and (c) an equivalent block diagram of (b).
wave. However, the derivation is rather difficult to make in this
design methodology. To solve this problem, the simple rule of
thumb is employed as an alternative in performing B. Common Voltage Control Loop
the controller design, where denotes the corner frequency of 1) Dynamic Modeling and Parameter Estimation: The
the closed-loop gain of the current loop shown in Fig. 6. The voltage loop dynamic behavior of the parallel SSMR system
loop gain of the current loop can be derived from Fig. 6 to be shown in Fig. 1 can be reasonably represented by the control
system block diagram drawn in Fig. 8(a). In Fig. 8(a), is
a voltage sensing factor ( is set here), is the
(20) disturbance transfer ratio, denotes
the system transfer function. The variables with overhead bar
The operating condition is chosen at load resistance denote nominal values, and are uncertain error
and duty ratio . The closed-loop corner fre- transfer functions caused by the variations of module number,
quency is chosen as kHz kHz , and operating condition and system parameters. In making the PI
the integral gain is first set as . Then by letting feedback controller design
and through the help of computer-aided analysis,
the Bode plots of magnitude for different values of are
(21)
shown in Fig. 7. According to the results, the proportional gain
is found to be . Various simulations indicate that the
corner frequency is almost unchanged for the normal ranges of are assumed. and are chosen as the transfer func-
and . tions at nominal operation condition at which all N modules
LI AND LIAW: PARALLELED DSP-BASED SOFT SWITCHING-MODE RECTIFIERS 943

1P = 116 W
! 786 W, V = 300 V): (a) simulation and (b) measured.
Fig. 10. Output voltage responses due to the step change of
(670 W

Fig. 9. The measured v for making model estimation: (a) step tracking
response and (b) step load regulation response. For the ease of design and implementation, the feedback
voltage controller is chosen as the proportional plus integral
are normally operated. And furthermore, for the convenience of type
derivation, the first-order transfer function of is assumed.
Since the transfer functions are difficult to derive, they will be (23)
obtained via estimation from measurements [20].
Model estimation: By neglecting the uncertain models in Fig. 8(a), one can derive
the following closed-loop transfer function from to
1) Let be the proportional type with
, and the paralleled N SSMR modules (
here) be normally operated at the chosen operating
point ( V, W). (24)
2) By applying a small step command ( V, Following the design approach presented in [4], the parame-
V V), the response of is recorded ters of can be systematically found to be
and plotted in Fig. 9(a).
3) At the same operating point, a step load ( (25)
W, W) is applied and the
steady-state value of the response of is measured The simulated and measured output voltage responses due to the
and plotted in Fig. 9(b). step load power change of W (670 W 786 W)
Using the measured tracking and regulation responses, at V are shown in Fig. 10(a) and (b), respectively. In
through careful derivation from the block diagram shown in realization, the designed continuous PI controller is transformed
Fig. 8(a), the following estimated dynamic model parameters into digital control algorithm using bilinear transformation. The
are obtained results show that they are very close to each other and meet the
prescribed requirements.
(22) 3) Design of Robust Control Scheme: The proposed robust
control scheme is drawn in Fig. 8(b), wherein an inverse nom-
2) Design of Feedback Controller: The following control inal plant model is employed to extract an equiv-
requirements for the response of due to the step load power alent disturbance signal , and a compensation control effort
change are specified: is yielded to reduce the effects of plant uncertain models
1) ; and load disturbance on the voltage control performance. The
2) ; extent of compensation is determined by the weighting factor
3) The maximum voltage dip due to a step load power . From Fig. 8(b), one can find the composite
change W is V, i.e., control effort
V/W.
4) The restore time is , which is defined as the (26)
time at which .
944 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19, NO. 4, JULY 2004

1v and 1I^ with different values of W due to the step

1 = 116 W (670 W ! 786 W, V = 300 V): (a) 1v and
Fig. 11. Simulated
change of P
1^
(b) I .

1^
!
Fig. 13. Measured v and I of the single-modules SSMR system with
1 = 116
different values of W due to the step change of P
1^
W (670 W
786 W, V = 300 1
V): (a) v and (b) I .

and the resulted voltage response becomes

(27)

If the ideal control can be obtained by utilizing the proposed

robust control, then is yielded, otherwise it
is assumed that

(28)

where is resulted due to the imperfect robust compensation.

Using (28), (27) can be rewritten as

(29)

The equivalent block diagram corresponding to (29) is drawn

in Fig. 8(c), from which some facts can be deduced as follows.
Comments:
1^ 1) By utilizing the robust control, the effects of
!
Fig. 12. Measured v and I of the two-modules SSMR system with
1 = 116
different values of W due to the step change of P and have been reduced by a factor of
1^
W (670 W
786 W, V = 300 1
V): (a) v and (b) I . .
LI AND LIAW: PARALLELED DSP-BASED SOFT SWITCHING-MODE RECTIFIERS 945

Fig. 14. Measured module inductor currents i , i and line input voltage and current: (a) one module is restarted its parallel operation (P = 670 W); (b) one
module is terminated its parallel operation (P = 670 W); (c) two-modules due to the step load change (P = 670 W ! 1340 W); (d) measured line input
voltage and current (P = 670 W).

2) The ideal compensation control can be obtained by letting 2) the voltage response variation of the robust controller is
. In that case, is found from much smaller than those by the PI controller.
(26). And obviously, it is also found that and b) Current sharing and line current responses: The mea-
. sured inductor currents when one module is restarted and ter-
3) The larger value of is chosen, the better control perfor- minated its parallel operation are shown in Fig. 14(a) and (b).
mance is obtained, but it is easier to yield instability due to The measured inductor currents of two-modules due to the step
the system nonlinearities. Thus suitable compromise be- load change W W are shown in Fig. 14(c).
tween control performance and operating stability should The current sharing differences are also plotted in
be made [13]. Fig. 14(a)–(c). Good current sharing control performance is ob-
4) Results: served from the results. Under the condition of ( V,
a) Voltage responses.: Hz, V, W), the measured line input
Simulation results: The simulated output voltage re- voltage and current are shown in Fig. 14(d). One can find
sponses and current commands with (without that the line drawn current has been regulated to be lowly dis-
robust control), and due to step load power torted with power factor and total harmonic distor-
change of W (670 W 786 W, V) are tion . The conversion efficiency of the two-mod-
shown in Fig. 11(a) and (b). The phenomena observed from the ules paralleled SSMR system is at W,
results meet the comments made above. and the system with only one module is at
Measured results: Let the two paralleled SSMR modules W.
be normally operated with current sharing weighting factors
, the measured and due to the
step load power change of W (670 W 786 W, V. CONCLUSION
V) are plotted in Fig. 12(a) and (b). The results show The current sharing and robust voltage regulation control
that they are very close to those via simulations. Now, let only for a DSP-based paralleled ZVT SSMR system have been
one module be operated, the measured and at the same presented. Having analyzed the operation and derived the gov-
conditions of Fig. 12 are shown in Fig. 13(a) and (b). The com- erning equations of the single SSMR module, the quantitative
parison between Figs. 12 and 13 indicates that: design of its circuit components and the implementation are
1) the larger value of is set, the smaller voltage dip is performed. Then the fully digital control of the paralleled
yielded; SSMR system is made. For the current-controlled PWM
946
scheme of each module, the small-signal model of current
loop is obtained using state-space averaging method and the
current controller parameters are found based on frequency
response approach. The current command of each module is
generated from a common command being multiplied by a
current sharing weighting factor, which is set by the current
distribution unit. As to the common voltage loop controller
design, its dynamic model is first estimated from step response
measurements, and the voltage controller parameters are found
systematically according to the given specifications. A robust
control is further added to improve the voltage regulation
performance. The simulation and experimental results have
confirmed that good current sharing control performance is
obtained under well-regulated output voltage, and the line
drawn current is also regulated to be with good power quality.
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Sheng-Hua Li was born in Taipei, Taiwan, R.O.C.,
on December 24, 1971. He received the B.S. degree
in electrical engineering from National Taiwan Insti-
tute of Technology, Taipei, in 1995 and is currently
pursuing the Ph.D. degree at National Tsing Hua Uni-
versity, Hsinchu, Taiwan.
His fields of interest are power electronics and
electric machine control.
Chang-Ming Liaw (S’88–M’89) was born in
Taichung, Taiwan, R.O.C., on June 19, 1951. He
received the B.S. degree in electronic engineering
from Tamkang College of Arts and Sciences, Taipei,
Taiwan, in 1979, and the M.S. and Ph.D. degrees
in electrical engineering from National Tsing Hua
University, Hsinchu, Taiwan, in 1981 and 1988,
respectively.
In 1988, he joined the faculty of National Tsing
Hua University as an Associate Professor in electrical
engineering. Since 1993, he has been a Professor in
the Department of Electrical Engineering. His areas of research interest are
power electronics, motor drives, and electric machine control.
Dr. Liaw is a Life Member of the CIEE.