IEEE Std P1532

A New Standard for 1149.1-based In System Configuration

Neil G. Jacobson, Chair

9/23/1999

IEEE Std P1532

Historical Perspective
n

ISP (In System Programming) first developed in 1993 using proprietary bus & protocol Simultaneous demand for boundaryscan and ISP leads to general adoption of 1149.1 bus & protocol Similar but different implementations result in custom tool environment
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Historical Perspective
n

Inaugural meeting April, 1996

Attended by semiconductor manufacturers, tool developers, ATE manufacturers and system designers

n n n

E-mail reflector established Meetings held quarterly Draft developed for review
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Mission

To define, document and promote the use of a standardized process and methodology for implementing programming capabilitiesutilizing (and compatible with) the 1149.1 communication protocol.

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Benefits
n n

Serve as development model for new devices Build on existing, well-supported and understood standard (1149.1, BSDL) Standardize tool, development system, test and manufacturing interfaces to provide instant device support Facilitate innovation and the development of new application areas Enable concurrent programming capabilities
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P1532 Application Space

n

It is the intention of P1532 to be applicable, usable and practical for:

FPGAs CPLDs PROMs I.E., ANY PROGRAMMABLE DEVICE

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Progress so far...
n

Description of silicon implementation requirements completed and proceeding to ballot. Description of BSDL extensions continuing to be filed as a supplement to the standard.

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1149.1 System Modal States

n n

System Mode Test Mode

Any non-test instruction loaded Any test Instruction Loaded Any test instruction loaded

System Mode

Any non-test instruction loaded

Test Mode

Power Up

Test-Logic-Reset

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P1532 System Modal States

n n n n

Unprogrammed Mode ISC Accessed Mode ISC Complete Mode Operational Mode

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P1532 System Modes

Any non-test instruction but ISC_ENABLE executed ISC_ENABLE executed Any non-test instruction but ISC_DISABLE executed Unprogrammed (0,0) TLR and ISC_Done is clear ISC Accessed (1,X)
d execute ISABLE ISC_D

ISC_Done is clear Power Up ISC_Done is set

t d an se R e is TL on _D ISC

Test Mode

Operational (0,1)

LE AB EN ted _ ISC xecu e

An bu y non t an ISC_ -test dI SC Disa instr _D ble uct io on e i loade n sc lea d r

ISC_DISABLE loaded ISC Complete (0,X)

Any non-test instruction but ISC_ENABLE executed

Any non-test instruction but ISC_Disable loaded and ISC_Done is set

Signals: (ISC_Enabled, ISC_Done)

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P1532 System Modes

Unprogrammed
An y

ISC Accessed
te

An y an non d -t on an ISC est ins d IS _En tr C_ a uc Do ble tio ne d is n lo is c a cle lea ded ar r

st loa ins de tru d cti

Test Mode

d de loa t n e tio s A uc d is tr e ins bl st Ena te n- C_ no d IS y An an

ti uc str in st ed te oad l ny

on

Operational

d de loa ar An n e yt tio cl An es uc d is set t str le is in ab e Any test instruction loa instr t n n s de uc loaded d tio -te _E Do n on SC C_ n I IS ny nd nd A a a

ct ru st in d st e te load y

io

ISC Complete

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P1532 Instruction Set

n

Support Basic ISC Functionality

Concurrent Operations Well-defined System Behaviour
Mandatory Instructions
ISC_ENABLE ISC_PROGRAM ISC_DISABLE ISC_NOOP

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P1532 Instruction Set

n

Support Additional Access Mechanisms

ISC_DISCHARGE ISC_SETUP ISC_PROGRAM_DONE ISC_ERASE_DONE ISC_DATA_SHIFT ISC_ADDRESS_SHIFT ISC_INCREMENT

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P1532 Memory Model Basic Structure

Address Data

Memory Array (some areas unused)

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P1532 Memory Model Variation 1

ISC_PData/ISC_RData TDI Address Data TDO

Memory Array

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P1532 Memory Model Variation 2

ISC_Address

TDI

ISC_PData/ISC_RData

TDO

Memory Array

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P1532 Memory Model Variation 3

Address Gen

ISC_Address

TDI

ISC_PData/ISC_RData

TDO

Memory Array

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P1532 Memory Model Variation 4

Next Address Control

Address

TDI

ISC_PData/ISC_RData

TDO

Memory Array

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P1532 Memory Model Variation 5

Address Gen ISC_Address

TDI ISC_Config

ISC_PData/ISC_RData

TDO

1 bit

n-1 bits

Non-volatile Memory Array #1 Addr(n) = 0

Volatile Memory Array #2 Addr(n) = 1

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P1532 Memory Model Variation 6

Address Gen

ISC_Address

TDI

ISC_PData/ISC_RData

TDO

Memory Array #1 Addr(n) = 0

Memory Array #2 Addr(n) = 1

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P1532 Instruction Set

n

Support Advanced ISC Functionality

ISC_ERASE ISC_READ ISC_READ_INFO ISC_PROGRAM_SECURITY ISC_PROGRAM_START ISC_PROGRAM_STOP

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P1532 Optional Status Mechanism

Optional Programming-In-Progress Flag Optional Status Subcodes Error Code N

...

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P1532 Optional Security Mechanism

ISC_Disable_Read ISC_Disable_Program ISC_Disable_Erase Internal Protection Control Register

N-Bit Key

All 0's

Transfer of N+3 bits occurs on the completion of ISC_PROGRAM_SECURITY IF (All 0's OR Equal) AND Not All 1's

All 1's N

Equal N

TDI

ISC_PData

TDO

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P1532 BSDL
n n

Supported through BSDL EXTENSION Description sufficient to indicate:

Device ISC Capabilities Allowable Mode Transitions Operational Flows

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Joining the Ballot Group

n n

You must be a member of the IEEE-SA. You must be committed to reading, understanding and returning the ballot document. Submit your contact information to me now!

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Joining the Working Group

n

Meetings are scheduled at least 4 weeks in advance They are 2 days in length and generally in the San Jose area To become a voting member, you must:
Attend two consecutive meetings. Express an interest in joining.

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Information Sources
n

Executive Committee
Neil Jacobson, Chair
neil.jacobson@xilinx.com

Dave Bonnett, Vice Chair

dbonnett@asset-intertech.com

Ted Eaton, Secretary

ted_eaton@sun.com

Ken Parker, Technical Editor

parker@lvld.hp.com

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Information Sources
n

Invitation to Ballot Group

Contact Neil Jacobson
neil.jacobson@xilinx.com

E-mail Reflector
stds-1532-wg@ieee.org
Contact Neil Jacobson to join

Web Page
http://grouper.ieee.org/groups/1532/index.html

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