SymmetrixInternalsArchitectureOverview1

SymmetrixInternals

Module1:SymmetrixArchitectureOverview

2008EMCCorporation.Allrightsreserved.

WelcometothefirstmoduleoftheSymmetrixInternalscourse.Someofthismaybeareviewoftheprerequisitematerials, butitiscriticalthatwehaveasolidunderstandingofthearchitecturalconceptsandtermsasthiswillbethefoundationfor theremainderofthisclass.

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SymmetrixInternalsArchitectureOverview2

Module1SymmetrixArchitectureOverview
Aftercompletingthismodule,youwillbeableto: DiagramthebasicarchitectureofaSymmetrixanddefine thefollowingterms:
Frontend Backend Cache

DescribethedifferencebetweenPhysicalDiskand LogicalVolume Explainthedataflowforreadandwriteoperation includingthefollowingterms

Readhit,readmiss Fastwrite Delayedfastwrite
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SymmetrixInternalsArchitectureOverview3

SymmetrixEvolution
Symmetrix4 Symmetrix2
Symmetrix4400 4MbDRAM 256MBCache Board 5.25HDA Symmetrix 4800

Symmetrix6 Symmetrix4.8
3630/5630 3830/5830 3900/5900

Symmetrix3
Symmetrix55003 16MbDRAM 1GBCacheBoard

3330/5330 3430/5430 3700/5700

DMX
DMX800 DMX1000 DMX2000

Symmetrix 3000* HyperVolume Extension 3.5HDA SymmetrixESP SDMS EOS EDM

DMSP SystemCalls UltraSCSI SAFailover PowerPath FibreChannel SDDF

Symmetrix5
8130 8430 8730

Symmetrix6.5 DMX2

DMX4

90 91

92

93 94

95

96

97

98

99
>4GBCache SymmOptimizer FileSMMF NewTFSplits SwitchSRDFR1/R2 FCFabricSupport

00 01 02 03 04 05 06 07

Symmetrix 4200 Dynamic Sparing Non Disruptive Microcode Load

Symmetrix52304 InfoMover Symmetrix51009 Celerra RAIDS FDRSOS FWDSCSI SRDFExtDist SRDFHostComp SymmetrixManager(ECC) DataReach MPLF TimeFinder 3380/3390Intermix 3GB/9GBIntermix

Symmetrix5.5
8230 8530 8830

Symmetrix7 DMX3 DMX3 950

DMX1500 DMX2500 DMX3500 DMX4500

Symmetrix 55009 52003 52009 SRDF PDSAssist SDS HDC

2008EMCCorporation.Allrightsreserved.

TheSymmetrixrepresents17yearsofdevelopmentandrefinement. Asweseeinthechartabove,eachgenerationhas addedperformance,connectivity,andusabilityfeatures.

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SymmetrixInternalsArchitectureOverview4

EMCStoragePlatformPortfolio

Customer Requirements

DMX3/DMX4

DMX/DMX2

CLARiiON CXSeries

Customer Investment
2008EMCCorporation.Allrightsreserved.

AtthehighendwehavetheSymmetrixDMX3andtheDMX4.Atthemidtier,wewillcontinuetoofferandexpandour CLARiiONfamilyofproducts. AlthoughthispresentationisintendedforEngineeringitisimportanttonotethattheSymmetrixDMXseriesDirectMatrix ArchitectureandEnginuityoffersuncompromisingperformanceinbothsustainedandburstIOenvironments.

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SymmetrixInternalsArchitectureOverview5

SymmetrixDMX9506slotSpecifications
EXPANSION

Disk Adapters Drive channels Number of disks (min/ max) Max. TB (raw) Max. TB (protected) Memory Directors Max. Useable Global Memory Useable connectivity (Combinations may be limited or restricted)
2008EMCCorporation.Allrightsreserved.

1 DA Pair 8 32 180 90 78 2 32GB

2 DA Pairs 16 64 360 180 157 2 64GB

8xFibreChannel
only

16xFibreChannel 8xGigEremote
replication

10xGigabit
EthernetiSCSI

AlloftheDMXseriescontaina19 rackmountedsystem.IntheDMX/DMX2seriesthiswastheDMX800.Inthe DMX3andDMX4seriesthisistheDMX950.Therearetwoconfigurationsforthe950,eitherasinglesystembywith upto180disksorasystembayandastoragebaywithupto360disks.Thesesystemsprovidethecapabilitiesastheother DMXmodels,butatalowerdiskcountandlowerpricepoint.

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SymmetrixInternalsArchitectureOverview6

Symmetrix1500450024slotSpecifications
INCREMENTALSCALABILITY

Disk Adapters Drive channels Number of disks (min/ max) Max. TB (raw) Max. TB (protected) Memory Directors Max. Global Memory Useable connectivity (Combinations may be limited or restricted)

1 DA pair DMX 1500 16 96240 119 102 28 64GB

2 DA pairs DMX 2500 32 192960 479 301 28 144GB

3 DA pairs DMX 3500 48 3601,440 719 435 48 216GB

4 DA pairs DMX 4500 64 4802,400 1,053 526 48 256GB

48xFibreChannel 24xFICON 48xESCON 8xGigEremote

replication

64xFibreChannel 48xFICON 64xESCON 8xGigEremote

replication

64xFibreChannel 40xFICON 64xESCON 8xGigEremote

replication

64xFibreChannel 32xFICON 64xESCON 8xGigEremote

replication

24xGigEiSCSI
2008EMCCorporation.Allrightsreserved.

48xGigEiSCSI

40xGigEiSCSI

32xGigEiSCSI

Thisslideshowstheminimumandmaximumdrivecounts,directorcount,andmaximumcachesizesoftheDMX3and DMX4seriesmachines.Frontviewofa1SystemBayand4MohawkStorageBays.DMX3andDMX4supports configurationsofupto1920drives(2400viaRPQ)11Baysincluding10MohawkStorageBaysand1SystemBay.Each MohawkStorageBaymaycontainupto16 DAEs withupto15driveseachforatotalof240drivesperMohawkStorage Bay,2400drivesintotal.

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SymmetrixInternalsArchitectureOverview7

FlexibleHostConnectivity
EnterpriseStoragePlatform SameStorageSystemcan SupportbothMainframeand OpenSystems MainframeCKDdevices
ESCON(EA) FICON(EF)

OpenSystemsFBA devices
FibreChannel(FA) iSCSI(SE)
2008EMCCorporation.Allrightsreserved.

TheSymmetrixisanEnterpriseStoragePlatformandcanemulate bothmainframeCountKeyDevices(CKD)andopen systemsFixedBlockArchitecture(FBA)deviceswithinthesamestoragesystems.Mainframehostsconnectusingeither ESCONorFICONfrontenddirectorsandopensystemshostconnectusingSCSIoverFibreChannelandiSCSIprotocols usingFibreChannelandISCSIfrontenddirectors.Hundredsofhostscanbeconnectedtothesamearrayandthereforethe SymmetrixcanbetherepositoryforalldatainanEnterprise. Foramorespecificlistoftheplatformsandspecificdetails, refertotheOpenSystemsSupportmatrixandtheeLab Navigator.

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SymmetrixInternalsArchitectureOverview8

SymmetrixArchitecture

Frontend Channel Director

Shared Global Memory Cache

Backend DiskDirector

AllSymmetrixshareasimilarbasicarchitecture
2008EMCCorporation.Allrightsreserved.

AllmembersoftheSymmetrixfamilysharethesamefundamentalarchitecture.Themodularhardwareframeworkallows rapidintegrationofnewstoragetechnology,whilesupportingexistingconfigurations. Therearethreefunctionalareas:

SharedGlobalMemory providescachememory Frontend theSymmetrixconnectstothehostssystemsusingChannelAdaptera.k.a ChannelDirectors.Each directorincludesmultipleindependentprocessorsonthesamecircuitboard,andaninterfacespecificadapterboard. Backend ishowtheSymmetrixcontrolsandmanagesitsphysicaldiskdrives,referredtoasDiskAdaptersorDisk Directors.Likefrontenddirectors,eachdirectorincludesmultipleindependentprocessorsonthesamecircuitboard.

Whatdifferentiatesthedifferentgenerationsandmodelsisthe number,type,andspeedofthevariousprocessors,andthe technologyusedtointerconnectthefrontendandbackendwithcache.

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SymmetrixInternalsArchitectureOverview9

FrontendandBackend
Physicallythefrontendisnotinthefrontandthe backendisnotintheback!
Frontendandbackendarelogicalconceptsandhasnothingto dowiththephysicalplacementofthecomponentsinthesystem
PO WER T O T ER M IN ATI O N SW C 2 SW D 2 SW E2 SW F2 TER M PO WER PO SIT IO N = PO WER F O R T ER M IN ATI O N C O M ESF R O M C ABL E VC C PO SIT IO N = PO WER F O R T ER M IN ATI O N C O M ESF R O M BAC KPL AN E

TER M IN ATO R SSW C 1 SW D 1 SW E1 SW F1 EN ABL E IN U PPO SIT IO N L ED U N D ER SW IT C H I SO N D ISABL E IN D N PO SIT IO N L ED U N D ER SW IT C H I SO FF

SYMM4

Frontendconnects hoststothesystem
Director Adapter

M ot orola 68060

TE R M P O W E R

SW C 2
V C C E N A B L E

SW C 1
D IS A B L E

TE R M P O W E R

SW D 2
V C C E N A B L E

SW D 1
TE R M P O W E R D IS A B L E

SW E2
V C C

ToHosts

E N A B L E

SW E1
TE R M P O W E R D IS A B L E

SW F 2
V C C

E N A B L E

SW F 1

D IS A B L E

M ot orola 68060

S C S I H O S T A D A P TE R E M C C O R P O R A TI O N
TH STORA E AR H TE TS E G CI C C PYR G H O I T1995 H PKI N O TON, M A

PO WER T O T ER M IN ATI O N SW C 2 SW D 2 SW E2 SW F2 TER M PO WER PO SIT IO N = PO WER F O R T ER M IN ATI O N C O M ESF R O M C ABL E VC C PO SIT IO N = PO WER F O R T ER M IN ATI O N C O M ESF R O M BAC KPL AN E

TER M IN ATO R SSW C 1 SW D 1 SW E1 SW F1 EN ABL E IN U PPO SIT IO N L ED U N D ER SW IT C H I SO N D ISABL E IN D N PO SIT IO N L ED U N D ER SW IT C H I SO FF

SYMM4

Backendconnects thephysicaldrives
Director Adapter Physicaldrives
2008EMCCorporation.Allrightsreserved.

M ot orola 68060

TE R M P O W E R

SW C 2
V C C E N A B L E

SW C 1
D IS A B L E

TE R M P O W E R

SW D 2
V C C E N A B L E

SW D 1
TE R M P O W E R D IS A B L E

SW E2
V C C

E N A B L E

SW E1
TE R M P O W E R D IS A B L E

SW F 2
V C C

E N A B L E

SW F 1

D IS A B L E

M ot orola 68060

S C S I H O S T A D A P TE R E M C C O R P O R A TI O N
TH STORA E AR H TE TS E G CI C C PYR G H O I T1995 H PKI N O TON, M A

Whenwerefertothefrontendandbackendwearereferringtothelogicalconfigurationandnotthephysical. Thefrontendincludesthehostdirectorsandtheassociatedadapters.ThepairisoftenreferredtoasChannelAdapters (CAs)orHostAdapters(HAs).Todayeachfrontenddirectorhasfourindependentprocessorsorslices.Eachprocessor cansupportadifferentprotocol.Frontenddirectorsconnectthroughthemidplanetoadapterboardswhichcontainthe interfacespecificprotocolsandhardware.ForexampleaHostAdaptermayrunFibreChannelprotocolontwoofthe processorsandiSCSIontheothertwo.Mezzaninecardareusedonthedirectorstohandletheappropriateinterface. ThebackendincludestheDiskAdapters,associatedadapterandthephysicaldiskdrives.TheDiskAdaptersarethesame universaldirectorsastheusedforthefrontendbutwithdifferentmicrocode,mezzaninecards,andbackendadapters.The physicaldrivesaredualportedFibreChanneldisksprovidingredundantconnectionstopairsofDiskAdapters.Todaywe supportavarietyof73,146,and300GBdrivesfromanumberofdifferentvendors. Rememberalldataflowsfromthefrontendtothebackendandviseversathroughcachememory.

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SymmetrixInternalsArchitectureOverview10

SymmetrixDMXArchitecture
Frontend
ChannelDirector
CACHESLOTS Processord
PowerPC1.3GHz

Shared Global Memory

Backend
DiskDirector
Processord
PowerPC1.3Ghz

Processorc
PowerPC1.3Ghz

Processorc
PowerPC1.3Ghz

Cache
Processorb
PowerPC1.3Ghz

Processorb
PowerPC1.3GHz

TrackTable Processora
PowerPC1.3Ghz

Statusand Communications MAILBOXES

Processora
PowerPC1.3GHz

DirectMatrix
EachDirectorhasapointtopointconnectiontoeachCacheBoard
2008EMCCorporation.Allrightsreserved.

TraditionallytheSymmetrixhasbeenabusarchitecture,howevertheDMXchangedthiswithitsDirectMatrix(DMX) architecturewhereeachdirectorhasadirectconnectiontoeachmemoryboard.Theresultisevengreaterperformance, availabilityandscalability. Performance Insharedbusarchitecture,thereisoftencontentionforthebuswhichlimitsperformance.TheDirect MatrixArchitectureprovidesperformanceforabroadrangeofdemandingtransactional,decisionsupport,and consolidatedapplicationsandprovidestheuniqueabilitytoreacttoburstsofunexpectedactivity,whilecontinuingto deliverhighservicelevels. Availability TheSymmetrixDMXsetsanewstandardinavailabilitybytheeliminationofbusesandswitches.Allpower andcoolingisredundantandtheDMXsupportsonlinecomponentreplacementandonlinesoftwareupgradesand reconfiguration. Scalability Asadditionalmemoryboardsanddirectorsareaddedtothesystem,thenumberofconnectionsincrease linearlyallowingnearlyinfinitescalability.

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SymmetrixInternalsArchitectureOverview11

DirectMatrixArchitecture

64GB Memory

64GB Memory

64GB Memory

64GB Memory

64GB Memory

64GB Memory

64GB Memory

64GB Memory

2008EMCCorporation.Allrightsreserved.

TherealadvantageofDirectMemoryArchitecturecannotbeappreciateduntilyouvisualizeitasinthepictureabove.The GlobalMemorytechnologysupportsmultipleregionsand16connectionsoneachglobalmemorydirector.Inafully configuredSymmetrixsystem,eachofthesixteendirectorsconnectstooneofthesixteenmemoryportsoneachofthe eightglobalmemorydirectors.These128individualpointtopointconnectionsfacilitateupto128concurrentglobal memoryoperationsinthesystem. CurrentDMXsystemsusesM9memoryarchitecture.Eachmemoryboardhassixteenportswithoneconnectiontoeach director.Eachregiononaboardcansustainadatarateof500MBread,and500MBwrite.With4regionsperboard,a theoreticalmaximumof4GBpermemorycardispossible.(500MB Read+500MBwrite)X4Regions=4GB Thereforeafullconfigurationwith8memoryboardswouldhavea maximuminternalsystemthroughputof128GB. Eachfrontendandbackenddirectorhasdirectconnectionstomemoryallowingeachdirectortoconnecttoeachmemory board.Eachofthefourprocessorsonadirectorcanconnectconcurrentlytodifferentmemoryboards. Internallythecommunicationsprotocolbetweenthedirectorsand memoryisfibrechannelovercopperbasedphysical differentialdataconnections.

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SymmetrixInternalsArchitectureOverview12

InterDirectorCommunications

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IntheDirectMatrixArchitecture,contentionisalsominimizedbecausecontrolinformationandcommandsaretransferred acrossaseparateanddedicatedmessagematrix.Thisenablescommunicationbetweenthedirectors,withoutconsuming cachebandwidth.Theadvantageofthisbecomesmoreapparentaswetalkaboutreadandwriteoperationsandthe informationflowthroughthesystemlaterinthismodule.

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SymmetrixInternalsArchitectureOverview13

SymmetrixCacheManagement
SymmetrixCachemanagementisbaseduponthe followingprinciples:
Ifdatacomesfromcache,theaccesstimeisatmemoryspeeds Ifdatacomesfromdisk,theaccesstimewillbethemechanical speedofphysicaldisks
LocalityofReference
vIfadatablockhasbeenrecentlyused,adjacentdatawill beneededsoon vPrefetchalgorithmdetectssequentialdataaccesspatterns andsubsequenttracksarestageddatafromdisktocache

CACHESLOTS

Datareuse
vAccessedDatawillprobablybeusedagain

Leastrecentlyuseddataisflushedfrom cachefirst
vOnlykeepactivedatainthecache vFreeupcacheslotsthatareinactivetomakeroomformoreactivedata
2008EMCCorporation.Allrightsreserved.

TheperformanceprinciplesforaSymmetrixarenotunlikethose usedinhostoperatingsystems.Thegoalistodoservice allI/Ooperationsfromcache.Thiswaytheresponsetimewillbeatmemoryspeedsratherthanthemechanicalspeedsof physicaldisks. Whensequentialaccessisdetected,prefetchisturnedonforthatlogicalvolume.Prefetchisinitiatedby2sequential accessestoavolume.Onceturnedon,foreverysequentialaccess,theSymmetrixwillstagethenexttwosuccessivetracks intocache.After100sequentialaccessestothatvolume,thenextsequentialaccesswillinitiatetheprefetchingofthenext5 tracksonthatvolume.Afterthenext100sequentialaccessestothatvolume,theprefetchtrackvalueisincreasedto8.Any nonsequentialaccessestothatvolumewillturntheprefetchoff. Whiletodaywehavecachessizesaslargeas256GB,cacheisnotaninfiniteresourceandoneoftheprimaryprinciplesfor performanceistomaintainonlythemostactivedataincache.Asdataisplacedintocacheoraccessedwithincache,itis aged.Thisallowsthesystemtomaintainonlythemostfrequentlyaccesseddatatoremainincachememory.Thedata residingincacheisorderedthroughanAgeLinkChain.Asdataistouched(readoperationforexample),itmovestothe topoftheAgeLinkChain.

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SymmetrixInternalsArchitectureOverview14

ReadOperationCacheHit
Frontend
Host Adapter 4. 1.
Processor

Shared Global Memory

CACHE SLOTS

Backend
Disk Adapter

3.

2.
Track Table Status and Communications

1. 2.

Hostsends READrequest HostAdapter(HA)checksTrackTable

3. 4.

Requesteddatalocatedincache Cache Hit! HAretrievesdataandsendstohost

Readoperationcompletedatmemoryspeed!
2008EMCCorporation.Allrightsreserved.

1) Tothehost,theSymmetrixappearsasaphysicaldrive.Thehostsendsreadrequesttoachanneladdress. 2) TheHostAdapterusesconfigurationinformationtomaptheaddresstoalogicalvolumeandscansthetracktableto discoveriftherequestedblocksarealreadyresidentincacheandifsowhere. 3) InthisthiscasetherequestedblocksarealreadyincacheandwegetaCacheHit. 4) TheHostAdapterreadsthedatafromcacheandpassesitbackto thehost Atthispoint,theAgeLinkChainisupdatedtoreflecttherecentaccessandthetrackismovedtotopofLeastRecently Used(LRU)queueasitisnowthemostrecentlyused. WithaCachehit,thetotalI/Oresponsetimewouldbesomething ontheorderof1millisecondorless.

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SymmetrixInternalsArchitectureOverview15

ReadOperationCacheMiss
Frontend
Host Adapter

Shared Global Memory

CACHE SLOTS

Backend
Disk Adapter

6.
1.
Processor

3.

2.

4.

Track Table Status and Communications Processor

5. 1. 2. 3. Hostsends READrequest HAchecksTrackTable Data Not in Cache HAnotifiesDAusingMessageMatrix 4. 5. 6.

DAretrievesdatafromdisk(updatestracktable) HAisnotifiedthatdataisincache HAretrievesdataandsendstohost

2008EMCCorporation.Allrightsreserved.

1) Againthehostsendsareadrequest. 2) TheHostAdapterchecksthetracktabletoseeifthedataisincache.InthiscaseitisnotandwegetaCacheMiss.If thedatabeingrequestedisnotintheprocessofprefetch,the ChannelDirectorwilldisconnectfromthechannel(known aslongmiss).Thisenablesthehosttoperformotheroperations.Iftherequesteddataisintheprocessofprefetch (knownas shortmiss),theChannelDirectorwillnotdisconnectfromthechannel. 3) TheHostAdapternotifiestheDiskAdapterthroughthecommunicationmatrixtogettherequesteddataandplaceitin anavailablelocationincache.Inearlierarchitectures,thecommunicationbetweendirectorsusedmailboxes. Basically,alldirectorsmonitorthemailboxareaincachetoseeifthereisworkforit.Thecommunicationmatrixinthe DMXeliminatestheaddedoverheadoncacheofcontinuouslypollingthemailbox. 4) TheDiskAdapterretrievesdatafromphysicaldiskandplacesit inanavailablecacheslot. 5) TheHostAdapterisnotifiedbytheDiskAdapter,againviathe communicationmatrix,thatthedataisnowincache. 6) TheHostAdaptercheckthetracktabletolocatethedataincacheandfromthispoint,theoperationthatoccursis exactlythesameasareadcachehit.IftheChannelDirectorhasdisconnectedfromthechannel,itmustnowreconnect thechannel.

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SymmetrixInternalsArchitectureOverview16

WriteOperationFastWrite
Frontend
HostAdapter 3. 1.
Processor

Shared Global Memory

CACHESLOTS

Backend
DiskAdapter

4.
Processor

2.

Track Table Status and Communications

1. 2. 3.

HostsendsWRITErequesttoHA WriteCompletesenttohost

4.

CDplacesdatainanavailablecacheslot

TracksmarkedasWritePendingDAwill destageatearliestconvenience Dataremainsincacheuntilreplacedby LRUalgorithm

2008EMCCorporation.Allrightsreserved.

1) HostsendswriterequesttoChannelDirector 2) ChannelDirectorlocatesanavailablecacheslotandplacesdata incache.Ifthetrack(s)alreadyexistsincacheaswrite pending(waitingtobewrittentodisk),theChannelDirectorwillwritethedatatotheexistingslotincache.For example,I/O#1consistsofawritetothelastblockonthefirsttrackonthefirstcylinderofLogicalVolume001.I/O# 2thenconsistsofawritetothefirstblockonthatsametrack.WhentheChannelDirectorchecksthetracktableforan availableslotincache,itwillseethatthetrackinquestionisalreadyflaggedasawritepending.Therefore,theChannel Directorwillwritethefirstblock(I/O#2)tothesameslotincachewherethelastblock(I/O#1)onthattrackisalready residing. 3) Hostisnotifiedthatwriteiscomplete. 4) AssoonastheDiskAdapter(s)thataremanagingthephysicalcopy(ies)ofthedataareavailable,thedatawillberead fromcacheandwrittentothephysicaldisk. Note:Evenifthehostonlywrites/updatesoneblock,theentiretrackismarkedaswritepending.Whenthetrackis markedaswritepending,allcopiesaremarkedaswritependingforthattrack. Rememberthatthedataremainsincacheuntil1)itiscommitted todisk,and2)itbecomestheLeastRecentlyUsed dataincache.WritependingtracksarenotsubjecttotheLRU algorithm.Whenthedataisdestaged todisk(removal ofwritependingflag),itthenenterstheLRUAgeLinkChainasthemostrecentlyuseddata.Ifthedataisfrequently accessed,itwillremaintowardsthefrontoftheChain.Ifthedataisnotaccessed,itwillmovetotheendoftheChain andsubsequentlycycleoutofcachemakingtheslotavailableforotheruse. Theeffectofawritecachehitisthatthehostisimmediately getsanI/Ocompleteassoonasthewriteisreceivedin cache.Thisgreatlyenhancestheperformanceofthehostitself.FewerCPUcyclesarespentwaitingforthephysical I/Otocomplete.

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SymmetrixInternalsArchitectureOverview17

DelayedFastWrite
OccurswhentheWritePendingCeilingisreached
WritePendingCeilingfor:
LogicalVolumeLevel SymmetrixSystemLevel
Atmost80%ofSymmetrixcacheslotscancontainwritependingdata

Cachealgorithmsoptimizecacheutilizationandfairness

2008EMCCorporation.Allrightsreserved.

Itisimportanttorememberthattherewillalwaysbecacheresourcesavailableforreads.Bydefault,the80%fastwrite ceilingensuresthatatleast20%ofcacheresourceswillbefreefornewrequests. Managingeachindividualvolumeswriteactivity(viathedynamicfastwriteceiling)enablesEnginuity totypicallyprevent systemwidedelayedwritesituations.

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SymmetrixInternalsArchitectureOverview18

FastWriteCeiling
Cachealgorithmsoptimizecacheutilizationandfairness Cacheallocationdynamicallyadjustedbasedoncurrent usage
DMX2andbelow
MaximumnumberofwritependingslotsperSymmetrixLogicalVolume baseduponconfiguration
vKnownasFastWriteCeilingorWritePendingCeiling

FastWriteCeilingcandynamicallyincreaseby3X

DMX3andabove
Eachlogicalvolumeisallowed4%oftotalavailablecache (5%oftheSystemWritePendinglimit(80%))

2008EMCCorporation.Allrightsreserved.

DMX3andabove: WhentheSymmetrixis IMPLed(InitialMicrocodeProgramLoad),thetotaluseravailablecacheisdetermined.The systemwillsetamupperlimitof4%ofthetotaluseravailable cacheasthelogicalvolumewritependinglimit.Thisisa fixedlimit. DMX2andbelow: WhenaSymmetrixisIMPLed,thetotaluseravailablecacheisdetermined.Themaximumnumberofslotseachlogical volumemayuseforwrites(DeviceWritePendingLimit)isbaseduponthenumberoflogicalvolumesandthesizeofthe useravailablecache.Thisisoftenreferredtotheconfigurationvalue.Ifalogicalvolumeisveryactivewithwrites, Enginuity willdynamicallyincreasethedevicewritependinglimitupto threetimestheconfigurationvalue.TheDevice WritePendinglimitisdynamicallyadjustedfromtheconfigurationvalueuptothreetimestheconfigurationvalueandthen backdown,baseduponthewriteactivityofeachlogicalvolume. Itisimportanttorememberthattherewillalwaysbecacheresourcesavailableforreads.Bydefault,the80%fastwrite ceilingensuresthatatleast20%ofcacheresourceswillbefreefornewrequests.Managingeachindividualvolumeswrite activity(viathedynamicfastwriteceiling)enablesEnginuity totypicallypreventsystemwidedelayedwritesituations.

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SymmetrixInternalsArchitectureOverview19

WriteOperationDelayedFastWrite
Frontend 6.
1. HostAdapter

Shared Global Memory

CACHESLOTS

Backend
DiskAdapter 3.

Processor

2.

5.

Processor

-
Track Table Status and Communications

4.

1. 2. 3.

Hostsends WRITE requesttoHA HAcannotlocatefreecacheslotandsignals DAtodestage DAwilldoaforceddestageofWritePendings tofreecacheslots

4. 5. 6.

DAsignalsHAofavailableslots HAplacesdatainanavailablecacheslot Writecompletesenttohost

2008EMCCorporation.Allrightsreserved.

1) HostSendsWriterequest 2) TheHostAdapterdoesnotfindavailablecacheslotsforwriting,becausethevolumehasreacheditsFastWriteCeiling ortheentireSymmhas80%ofitscacheslotscontaining writependings.WhentheVolumeFastWriteceilingis reached,onlythatvolumesperformanceisimpacted.WhentheSymmSystemFastWriteCeilingisreached,theentire Symmsperformanceisimpacted. 3) DiskAdapterfreesupcacheslots. 4) TheDiskAdaptersignalstheChannelDirectorthroughtheCommunicationMatrix. 5) TheHostAdapterprocessesthewriteinasimilarmannerasafastwrite. 6) HostreceivesaI/OComplete Again,thisoperationtakessignificantlylongerthanafastwritebutensuresthattheI/Oflowsthroughcache.Itislikely thatinformationjustwrittenbyahostwillbereadinthenearfuture.Ifcachewerebypassedandthedatawritten directlytodisk,thedatawouldnotthenbeavailabledirectly fromcacheforthenextrequest.

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SymmetrixInternalsArchitectureOverview20

OpenSystemsConnectivityOptions
FibreChannelDirectors(FA)
EightPorts Supportsupto4Gb/secspeedsperport Singlemodeandmultimodeconfigurations

iSCSI(SE)
FourPorts 1Gb/sec LowcostconnectivityusingexistingIPnetworkinfrastructure

2008EMCCorporation.Allrightsreserved.

Today,networkedstorage(SANorNAS)isthepreferredmethodto connectOpenSystemshostswithstorage.ForSAN connectivity,FibreChannelistheinterfaceofchoice.LegacyopensystemsoftenuseparallelSCSI,andSCSIFrontend directorsaresupportedonlyinlegacynonDMXsystems. DMX3usesUnifiedDirectorswhichusesthesamehardwaretosupportmultipleprotocols.TheUnifiedDirectorcontains fourprocessors. FibreChannelTheDMXsupportsaneightportfourprocessorFibreChannelDirector.Thestandardfibrechannel connectionusesShortwaveLaseropticsandmultimodefiberopticalcablesfordistancesofupto500Metersovera50 microncable.TheoptionalLongwavelaseruses9micronsingle modeopticsfordistancesof10Kandgreater.Both switchedfabricsandarbitratedloopSANsaresupported. iSCSIallowsblocklevelaccessoverIPnetworks.ItissupportedontheDMXusingthenewMultiProtocolChannel Director.ThisdirectorcanbeconfiguredtosupportFICON,1Gb EthernetforSRDFattach,and1GbEthernetforiSCSI hostattach.iSCSIisidealforstorageandserverconsolidationenvironmentsthatrequirelowcostconnectivitythat leveragesexistingIPnetworks.

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SymmetrixInternalsArchitectureOverview21

MainframeConnectivityOptions
ESCON(EA)
EightPorts Supportsdatatransferratesupto17MB/secperport Singlemodeandmultimodeconfigurations

FICON(EF)
FourPorts Datatransferratesofupto4Gb/secperport DirectConnect SwitchedFabric

2008EMCCorporation.Allrightsreserved.

MainframeconnectivityisthrougheitherESCONorFICONserialchannels.Theoriginalmainframeconnectivitywas throughparallelinterfaceswithbusandtagcables.Exceptforafewlegacysystems,thisbusandtaghasbeenreplaced withESCONbecauseofincreasedspeedandflexibility.ESCONusesmultimodefiberopticsandsupportsdistancesofup to3kilometers.Greaterdistancesaresupportedusingmediaconverters. FICONisFibreChannelformainframes.Itofferssuperiorperformanceandextendeddistanceascomparedtoits predecessor,ESCON.Assuch,mostmainframecustomerswilladoptFICONastheirprimarymainframechannel connectivityoverthenextfewyears.FICONusesmultimodefiberopticsandsupportsdistancesofupto500meters. FICONmayalsousesinglemodefiberopticsfordistancesofupto10KMandbeyond.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview22

HostDirectorandAdapterPairs
FrontenddirectorsalsocalledHost Adapters(HA)orChannelAdapters(CA)
ESCONEA FICONEF FibreChannelFA iSCSISE

Director

Host

Unified(Universal)Directorprovides commonhardware
Emulationcodeprovidessupportforspecific protocols Mezzaninecardsprovideinterfacespecific hardware

Adapterprovidesphysicalconnection Eachdirectorhasfourprocessors
Processorabottom Processordtop

CardsareFieldReplaceableUnits(FRUs) andhotswappable
2008EMCCorporation.Allrightsreserved.

Adapter

Normally,ChannelDirectorsareinstalledinpairs,providingredundancyandcontinuousavailabilityintheeventofrepair orreplacementtoanyoneChannelDirector.EachChannelDirectorhasmultiplemicroprocessorsandsupportsmultiple independentdatapathstotheglobalmemorytoandfromthehostsystem. TodaytheDMXsupportsUnifiedorUniversaldirectors.Theseprovideacommondirectorboardthatsupportsall interfaces.Protocolspecificrequirementsareprovidedbysoftwareorfirmwarethatisloadedintothedirectorduring IMPL,Mezzaninecards,andadapters.OntheDMX3,four1.3GHzPowerPCdualprocessorsareusedoneachdirector board. Minimumof2directorspersystemforredundancyandamaximumof4,6or8directorsdependingonmodeland configuration.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview23

DiskDirectorandAdaptersPair
Interfacetophysicaldiskdrives
Processor d Processor c Processor b Processor a

0 1 0 1 0 1 0 1

4GbdualportedFibreChanneldrives ArbitratedLoopconfiguration

DiskAdapterisresponsiblefor:
Stagingreadinformationintocache fromthephysicaldisk Flushingwritependingstodiskfor writeoperations Diskandcachescrubbing Datarebuildingintheeventofdrive failure Invokingdynamicsparesas necessary

EightindependentportsperDA
Primarypathtodrives Alternatepathforavailability

2008EMCCorporation.Allrightsreserved.

DiskAdaptersarealsocalledDiskAdaptersorDAs.Theyareresponsibleforstagingreadinformationincachefromthe physicaldiskandflushingwritependingstodiskforwriteoperations. Whenitisnotstagingdataincacheordestagingdatatodisk, theDiskAdapterisresponsibleforproactivemonitoringof physicaldrivesandcachememory.Thisisreferredtoasdiskandcachescrubbing. TheDAalsoinvokesdynamicsparing(iftheDynamicSparingoptionisenabled).Thisfeaturemaximizesdataavailability bydiagnosingmarginalmediaerrorsbeforedatabecomesunreadable. DAsareinstalledinpairsoninthecardcageandprovideprimarypathtosomedrivesandalternatepathtoothers.DAare FieldReplaceableUnits(FRUs)andhotswappable.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview24

ShadowPartnerFailover
Processor d Processor c Processor b Processor a

0 1 0 1 0 1 0 1
0 1 2 3 4 5
Diskdrivesaredualported Eachprocessor/portonlyseesevery otherdriveontheloopundernormal operation Intheeventofprocessorfailure,the Shadowpartnerdirectortakesover thefunctionalityforalldisksonthat loop ShadowPartnerPairing:
Dir1&16 Dir2&15 Dir5&12 Dir6&11

0 1 0 1 0 1 0 1

Processor d Processor c Processor b Processor a

2008EMCCorporation.Allrightsreserved.

Thephysicaldrivesaredualported2GB fibre channeldrives.DiskAdaptersarealwaysinstalledinpairsandduring normaloperationeachprocessor/portonlyseeseveryotherdrive.Intheeventofprocessorfailure,the shadowpartner directortakesoverthemanagementofalldisksontheloop. Whilenotshowninthediagramabove,thephysicaldrivesarehousedinDiskArrayEnclosuresthatincluderedundant powersuppliesandLinkControlCardsthatprovidebypasscapabilitymakingitpossibletohotswapdriveswithout impactingtheintegrityofthearbitratedloop. Thenumberofdrivesperlooparemodelandconfigurationspecific.WiththelatestDMX,therecouldbeupto15direct connecteddrivesandastheconfigurationgrows,anadditional15morecanbedaisychainedtogether.Withtheearlier DMX,theconfigurationswerereferredtoa9diskand18diskperloopconfigurationsdependingonthenumberofDAsin thesystem.Again,rememberasingledirectornormallyonlyserviceseveryotherdrive.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview25

SymmetrixDisk
EMCspecifieslargebufferandXORcapabledrives Foursizedrivesarecurrentlysupported
73Gigabyte 146Gigabyte 300Gigabyte 500Gigabyte 500GigabyteSATAII(DMX4Only)

7,200,10,000RPMand15,000RPM Providedbyanumberofmanufacturers
Seagate Fujitsu Hitachi/IBM
2008EMCCorporation.Allrightsreserved.

Thephysicaldrivesaredualported2GBfibrechanneldrivesthatEMCOEMsfromseveralvendorsincludingIBM, Seagate,Hitachi,andFujitsu.Theyareavailablein73,146, 300and500GBcapacitiesandwith10Kand15KRPM speeds.AlldrivesaremanufacturedtomeetEMCsqualitystandardsanduniqueproductspecifications.These specificationsinclude,dedicatedXORcapablemicroprocessors,andlargeonboardbuffermemory(4MB 32MB). Note:MarketingdefinesaGBas1000X1000X1000,whileEngineeringdefinesaGBas1024X1024X1024.

500GB BL500LP

300GB Cheet300LPX FR300LFX T300155

146GB Cheet146LPX IBM146FX FU146LFX Cheet146LDX Cheet146X15 FU146LDX HIT146FX15 HIT146LDX

73GB Cheet73LPFX Cheet73LDFX Cheet73FX15 IBM73LDFX Cheet73LDDX Cheet73DX15 FU73LDDFX HIT73LDX15 HIT73LDDFX

L/LP=LowProfile F=Fibre

15=15KRPM D=Depopulated

X=XORCapable DD=DoubleDepopulated

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview26

SymmetrixGlobalCacheDirectors
Memoryboardsarereferredtoas GlobalCacheDirectorsandcontain sharedmemory Maximumof8CacheDirectors
8GB 16GB 32GB 64GB

StartingwiththeDMX3,cacheis mirroredandthereforealwaysinstalled inpairs Boardsarecomprisedofmemorychips anddividedintofouraddressable regions MemoryboardsareFieldReplaceable Units(FRUs)andhotswappable

2008EMCCorporation.Allrightsreserved.

CacheboardsaredesignedforeachfamilyofSymmetrix.ThelatestDMXsystemsuseM9architecture.Becausethese boardshavedifferentdesigns,theycannotbeswappedbetweenfamilies. HotswappablemeansthataCustomerEngineer,followingscripted procedure,canremoveandreplacetheboardwithout poweringdownthesystem.TheCEprocedureincludesdestaging alldataontheeffectedcacheboardandfencingoffthe boardinordertopreventlossofdata. IntelligentglobalmemoryconfigurationsallowSymmetrixDMXsystemstotransferdataatelectronicmemoryspeedsthat aremuchfasterthanphysicaldiskspeeds.Symmetrixsystemsare basedontheprinciplethattheworkingsetofdataatany giventimeisrelativelysmallwhencomparedtothetotalsubsystemstoragecapacity.Whenthisworkingsetofdataisin cachememory,thereisasignificantimprovementinperformance.Theperformanceimprovementachieveddependson bothofthefollowingprinciples:

LocalityofReferenceIfagivenpieceofinformationisused,thereisahighprobabilitythatanearbypieceof informationwillbeusedshortlythereafter. DataReuseIfagivenpieceofinformationisused,thereisahighprobabilitythatitwillbereusedshortly thereafter.

Thesecachememoryprincipleshavebeenusedforyearsinhostaswellasstoragesystems.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview27

RedundantGlobalMemory
DMX3introducedtheuseofaSymmetrixmirrored memoryarchitecture Datawrittentoprimaryboardthentosecondaryboardof thememorypair Allreadsarefromprimaryregionofamemoryboard Ifeithertheprimaryorsecondaryboardfails,alldirectors dropthefailedboard,andswitchtononmirroredwrite modeandonlyusethegoodboardofthefailedmemory pair Dataisstripedbetweenmemoryboards
2008EMCCorporation.Allrightsreserved.

MirroredmemoryisanewarchitecturalchangewithDMX3 Allwritesareinitiallydonetotheprimaryregion.Writesare thencarriedouttothesecondaryregion. Whilethereisprimaryandsecondarymemory,thesearealternatedacrossallmemoryboards,soforexamplememoryin slot0and1willhavealternatingPrimaryandSecondaryregions,algorithmsinEnginuitywillenabletheDirectorstotake fulladvantageofallmemorycardspresentwhenreadingandwriting.Anyfailureconditionofamemoryboardcausesall directorstodropthefailedboardandswitchtoanormalwrite modetothesurvivingboard.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview28

SymmetrixSharedGlobalMemory
SharedGlobalMemorycontains threetypesofinformation
CacheSlots:temporaryrepositoryfor frequentlyaccesseddata(stagingarea betweenhostandphysicaldrive) TrackTable:directoryofthedata residingincacheandofthe location/conditionofthedataresiding onSymmetrixphysicaldisk(s) Communicationsandstatus:contains performanceanddiagnosticinformation concerningSymmetrixandallows independentfrontendandbackendto communicate DMXusesamessagematrixforcontrol andcommunications
2008EMCCorporation.Allrightsreserved.

CACHESLOTS

TrackTable StatusandCommunications

Theactualsizerequirementsforcachedependsontheconfiguration.Thegeneralrulethatmoreisbetter alsoappliesto cache,butagain,theactualrequirementsisafunctionoftheconfigurationandapplicationaccesspatterns.TheCQSsystem providessizingguidelinesandtheconfigurationverificationduringthecreationofabinfilewillalsoprovide configurationspecificrequirements. Theprimaryuseforcacheisforstagingand destaging databetweenthehostandthediskdrives.Cacheisallocatedin tracksandisreferredtoascacheslots,whichare32Kbytesforopensystemsand57Kbytesformainframes.Ifthe Symmis supportingbothFBAandCKDemulationwithinthesameframe,the cacheslotswillbethesizeofthelargesttracksize, 57Ktracksize.WithDMX3,allcacheslotsare64Kbytesforbothopensystemsandmainframe. TheTrackTableisusedtokeeptrackofthestatusofeachtrackofeachlogicalvolume.Approximately16Bytesofcache spaceisusedforeachtrack.So,a2GBvolumewoulduseapproximately1MBofcachefortracktablespace.Youcansee thatcacherequirementsdependontheactualconfiguration. Globalmemoryisalsousedtomaintainalldiagnosticandshorttermperformanceinformation.TheSymmetrixmaintains diagnosticinformationforeverycomponentwithinthearchitecture.PerformancedataincludesI/Ospersecond,cachehit rateandread/writepercentagefortheentiresystem,individual directors,andindividualdevices(logicalvolumes).This informationisaccumulatedandstoredaspartofnormaloperations.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview29

EnginuityOverview
OperatingEnvironmentforSymmetrix
Enginuityistheemulationcode,serviceprocessorcodeandother softwareusedbyaSymmetrixtoimplementcorefunctions Eachprocessorineachdirectorisloadedwithspecificemulation code DownloadedfromserviceprocessortodirectorsoverinternalLAN
ZippedcodeloadedfromEEPROMtoSDRAM(controlstoreofdirector)

Enginuityiswhatallowstheindependentdirectorprocessorstoact asoneIntegratedCachedDiskArray
AlsoprovidessupportforadvancedfunctionalitylikeSRDF,TimeFinder, andotheroptionalsoftwareproducts

2008EMCCorporation.Allrightsreserved.

EnginuityOperatingEnvironmentisthebrandnamegiventotheoperatingsystemthatrunsintheSymmetrix.Itisalso knowasthemicrocode.Enginuitywillbediscussedindetaillaterinthiscourse.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview30

ContinuousDataAvailability
SinglebiterrorcorrectionforCache Proactivediskandcachescrubbing NonDisruptiveEnginuityupgrades Onlineconfigurationchanges FullsystembatterybackupintheeventofanACPowerfailure
EntireSymmetrixSubsystemwillrunonbatteryifACPowerforupto5 minutes Allowsthedestagingthecontentsofcache
VaultingwasintroducedwiththeDMX3

ContinuousOperationeveniffailuresoccurtoanymajor component:
Automaticfencingoffailedcomponents Redundancybuiltintomostmajorsubsystems Hotcomponentreplacement
2008EMCCorporation.Allrightsreserved.

TheSymmetrixisdesignedforcontinuousoperationthroughplannedandunplannedevents.Proactivemonitoringallows earlydetectionoffailingcomponents.Examplesofproactivemonitoringare: DiskScrubbingorDiskErrorCorrectionandErrorVerification: TheDiskAdaptersuseidletimetoreaddataand checkthepolynomialcorrectionbitsforvalidity.Ifadiskreaderroroccurs,theDiskAdapterreadsalldataonthattrackto Symmetrixcachememory.TheDiskAdapterwritesseveralworstcasepatternstothattracksearchingformediaerrors. Whenthetestcompletes,theDiskAdapterrewritesthedatafromcachetothediskdevice,verifyingthewriteoperation. Thediskmicroprocessormapsaroundanybadblock(orblocks)detectedduringtheworstcasewriteoperation,thus skippingdefectsinthemedia.Tofurthersafeguardthedata,eachdiskdevicehasseveralsparecylindersavailable.Ifthe numberofbadblockspertrackexceeds32blocks,theDiskAdapterrewritesthedatatoanavailablesparecylinder.This entireprocessiscallederrorverification. TheDiskAdapterincrementsasofterrorcounterwitheachbadblockdetected. Whentheinternalsofterrorthresholdisreached,theSymmetrix serviceprocessorautomaticallydialstheEMCCustomer SupportCenterandnotifiesthehostsystemoferrorsviasense data. CacheScrubbing orCacheErrorCorrectionandErrorVerification:TheDiskAdaptersuseidletimetoperiodically readcache,correcterrors,andwritethecorrecteddatabackto cache.Thisprocessiscallederrorverificationor scrubbing. Whenthedirectorsdetectanuncorrectableerrorincache,Symmetrixreadsthedatafromdiskandtakesthe defectivecachememoryblockofflineuntilanEMCCustomerEngineercanrepairit.Errorverificationmaximizesdata availabilitybysignificantlyreducingtheprobabilityofencounteringanuncorrectableerrorbypreventingbiterrorsfrom accumulatingincache.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview31

Vaulting
Intheeventofapowerfailure,theobjectiveistoquickly destagethecontentsofcachetoapersistentlocationto preventdataloss DatavaultingisaSymmetrixfeaturethatbecame availablewithDMX3
CurrentDMXdestagealgorithmisnondeterministic Ascachesize,disksizeandpowerrequirementsincrease,thetime requiredtodestagedataincreases Timetovaultcontentsofcacheispredictable

UnderwritersLaboratoriesInc.requiresshutdownwithin 5minutesofpoweroff
Vaultingensurethecontentsofcachecanbesavedwellwithinthis limit
2008EMCCorporation.Allrightsreserved.

DatavaultingisafeatureintroducedwiththeDMX3.Ascachesize,disksizeandpowerrequirementsincrease,the time requiredtodestagedataincreases.Powervaultwasdesignedto limitthetimenecessarytopowerofftheboxonbattery power.PowerVaultwillsaveglobalmemorytospecificvaultdevicesonpowerdown,thenonpowerupthedatawillbe loadedtocachesothatitmaybedestagedtothecorrectlocation.

Copyright2008EMCCorporation.AllRightsReserved.

SymmetrixInternalsArchitectureOverview32

ModuleSummary
ThemajorcomponentsofaSymmetrixare:
Frontenddirectorsthatconnecttohost Backenddirectorsthatconnecttophysicaldisks Globalmemorywhichisusedtostageanddestagedata

DirectMatrixArchitectureprovidesdirectconnectionsbetweeneachdirector andeachmemoryboard TheSymmetrixemulatesadiskdriveandpresentsvolumestoattachedhosts

CountKeyDevices(CKD)forMainframe FixedBlockArchitecture(FBA)forOpenSystems

Ahostreadrequestisprocessedbythefrontenddirector
Iftherequesteddataisalreadyincache
Cachehit

Ifnot,thebackenddirectorwillgetitandputitintocache
Cachemiss

Ahostwriterequestisalsoprocessedbythefrontenddirector
Ifaslotisavailable,thewriteisprocessedimmediatelyFastWrite Ifnot,thebackenddirectormustfirstdestagewritependingstofreeupcacheslots
DelayedWrite
2008EMCCorporation.Allrightsreserved.

Copyright2008EMCCorporation.AllRightsReserved.