Create, compile and simulate the D Flip Flop code USE work.resources.

all; ENTITY dff is GENERIC(tprop : delay := 8 ns; tsu : delay := 2 ns); PORT(d : IN level; clk : IN level; enable : IN level; q : OUT level; qn : OUT level); END dff; ARCHITECTURE behav OF dff IS BEGIN one : PROCESS (clk) BEGIN IF ((clk = '1' AND clk'LAST_VALUE = '0') AND -- rising clock edge enable = '1') THEN -- ff enabled IF (d'STABLE(tsu)) THEN -- check setup IF (d = '0') THEN -- check valid input data q <= '0' AFTER tprop; qn <= '1' AFTER tprop; ELSIF (d = '1') THEN q <= '1' AFTER tprop; qn <= '0' AFTER tprop; ELSE -- else invalid date q <= 'X'; qn <= 'X'; END IF; ELSE -- else no setup q <= 'X'; qn <= 'X'; END IF; END IF; END PROCESS one; END behav;

Asynchronous reset D- FF

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// Design Name : dff_async_reset // File Name : dff_async_reset.v // Function : D flip-flop async reset // Coder : Deepak Kumar Tala //----------------------------------------------------module dff_async_reset ( data , // Data Input clk , // Clock Input reset , // Reset input q // Q output ); //-----------Input Ports--------------input data, clk, reset ; //-----------Output Ports--------------output q; //------------Internal Variables-------reg q; //-------------Code Starts Here--------always @ ( posedge clk or negedge reset) if (~reset) begin q <= 1'b0; end else begin q <= data; end endmodule //End Of Module dff_async_reset could download file dff_async_reset.v here

Synchronous reset D- FF

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//----------------------------------------------------// Design Name : dff_sync_reset // File Name : dff_sync_reset.v // Function : D flip-flop sync reset // Coder : Deepak Kumar Tala //----------------------------------------------------module dff_sync_reset ( data , // Data Input clk , // Clock Input reset , // Reset input q // Q output ); //-----------Input Ports--------------input data, clk, reset ; //-----------Output Ports--------------output q; //------------Internal Variables-------reg q; //-------------Code Starts Here---------

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always @ ( posedge clk) if (~reset) begin q <= 1'b0; end else begin q <= data; end endmodule //End Of Module dff_sync_reset

VHDL CODE LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ffD IS PORT(D,CLK,RESET:IN BIT; Q,QINV:OUT BIT); END ffD; ARCHITECTURE behav OF ffD IS BEGIN PROCESS BEGIN WAIT UNTIL CLK='1' AND CLK 'EVENT; IF(RESET='1') THEN Q<='0';QINV<='1'; ELSIF D='1' THEN Q<='1';QINV<='0'; ELSE Q<='0';QINV<='1'; END IF; END PROCESS; END behav; VHDL CODE LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ffT IS PORT(T,CLK,RESET:IN BIT; Q,QINV:OUT BIT); END ffT; ARCHITECTURE behav OF ffT IS SIGNAL S:BIT; BEGIN PROCESS BEGIN WAIT UNTIL CLK='1' AND CLK 'EVENT; IF(RESET='1')THEN S<='0'; ELSIF T='1' THEN S<=NOT S; END IF; END PROCESS; Q<=S; QINV<=NOT S; END behav; VHDL Code: library ieee; use ieee.std_logic_1164.all;//standard library packages entity bit4audcounter is port(s,clk:in std_logic;q:inout std_logic_vector(3 downto 0));//i/p and o/p decl aration end bit4audcounter; architecture struc of bit4audcounter is component mux21//declaration of basic components used

port(a,b,s:in std_logic;y:out std_logic); end component; component fft port(t,clk,reset:in std_logic;q,q_inv:inout std_logic); end component; signal m:std_logic_vector(2 downto 0); signal q_inv:std_logic_vector(3 downto 0); begin //mapping t0:fft port map('1',clk,'0',q(0),q_inv(0)); m0:mux21 port map(q(0),q_inv(0),s,m(0)); t1:fft port map('1',m(0),'0',q(1),q_inv(1)); m1:mux21 port map(q(1),q_inv(1),s,m(1)); t2:fft port map('1',m(1),'0',q(2),q_inv(2)); m2:mux21 port map(q(2),q_inv(2),s,m(2)); t3:fft port map('1',m(2),'0',q(3),q_inv(3)); end struc; 4-bit SYNCHRONOUS UP-DOWN COUNTER VHDL Code: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;//standard library packages ENTITY counter4uds IS PORT(CLK,S:IN BIT; M:OUT BIT_VECTOR(3 DOWNTO 0));//i/p and o/p declaration END counter4uds; ARCHITECTURE struc OF counter4uds IS COMPONENT ffta //declaration of basic components PORT (T,CLK,RESET:IN BIT;Q,QINV:OUT BIT); END COMPONENT; COMPONENT mux21 IS PORT(A,B,S:IN BIT;Q:OUT BIT); END COMPONENT; COMPONENT and2bit PORT(A,B:IN BIT;C:OUT BIT); END COMPONENT; SIGNAL Q_INV,Q:BIT_VECTOR(3 DOWNTO 0); SIGNAL A:BIT_VECTOR(2 DOWNTO 0); BEGIN//mapping T0:ffta PORT MAP('1',CLK,'0',Q(0),Q_INV(0)); A0:and2bit PORT MAP('1',Q(0),A(0)); T1:ffta PORT MAP(A(0),CLK,'0',Q(1),Q_INV(1)); A1:and2bit PORT MAP(A(0),Q(1),A(1)); T2:ffta PORT MAP(A(1),CLK,'0',Q(2),Q_INV(2)); A2:and2bit PORT MAP(A(1),Q(2),A(2)); T3:ffta PORT MAP(A(2),CLK,'0',Q(3),Q_INV(3)); MO:mux21 PORT MAP(Q(0),Q_INV(0),S,M(0)); M1:mux21 PORT MAP(Q(1),Q_INV(1),S,M(1)); M2:mux21 PORT MAP(Q(2),Q_INV(2),S,M(2)); M3:mux21 PORT MAP(Q(3),Q_INV(3),S,M(3)); END struc; counter library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is

port( clk: in std_logic; reset: in std_logic; enable: in std_logic; count: out std_logic_vector(3 downto 0) ); end counter; architecture behav of counter is signal pre_count: std_logic_vector(3 downto 0); begin process(clk, enable, reset) begin if reset = '1' then pre_count <= "0000"; elsif (clk='1' and clk'event) then if enable = '1' then pre_count <= pre_count + "1"; end if; end if; end process; count <= pre_count; end behav; counter test bench library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; use std.textio.all; entity counter_tb is end; architecture counter_tb of counter_tb is COMPONENT counter PORT ( count : OUT std_logic_vector(3 downto 0); clk : IN std_logic; enable: IN std_logic; reset : IN std_logic); END COMPONENT ; SIGNAL SIGNAL SIGNAL SIGNAL begin dut : counter PORT MAP ( count => count, clk => clk, enable=> enable, reset => reset ); clock : PROCESS begin clk reset enable count : : : : std_logic := '0'; std_logic := '0'; std_logic := '0'; std_logic_vector(3 downto 0);

wait for 1 ns; clk <= not clk; end PROCESS clock; stimulus : PROCESS begin wait for 5 ns; reset <= '1'; wait for 4 ns; reset <= '0'; wait for 4 ns; enable <= '1'; wait; end PROCESS stimulus; monitor : PROCESS (clk) variable c_str : line; begin if (clk = '1' and clk'event) then write(c_str,count); assert false report time'image(now) & ": Current Count Value : " & c_str.all severity note; deallocate(c_str); end if; end PROCESS monitor; end counter_tb; bcd_counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd_16 is port( clk, reset : in std_logic; count : buffer std_logic_vector (15 downto 0) ); end bcd_16; architecture counter of bcd_16 is begin bcd_counting: process (clk, reset) begin -- process bcd_counting if reset = '1' then -- asynchronous reset (active high) count <= ( others => '0'); elsif clk'event and clk = '1' then -- rising clock edge if count ( 3 downto 0) = "1001" then count(3 downto 0) <= "0000"; if count ( 7 downto 4) = "1001" then count(7 downto 4) <= "0000"; if count ( 11 downto 8 ) = "1001" then count(11 downto 8 ) <= "0000"; if count ( 15 downto 12) = "1001" then count(15 downto 12) <= "0000"; else count(15 downto 12) <= count(15 downto 12) + '1'; end if; else count(11 downto 8 ) <= count(11 downto 8 ) + '1'; end if; else count(11 downto 8 ) <= count(11 downto 8 ) + '1';

end if; else count(3 downto 0 ) <= count(3 downto 0 ) + '1'; end if; end if; end process bcd_counting; end counter;