BAI TAP VHDL

1. Cho cac nh ngha kieu va khai bao tn hieu sau:

Cac phep gan nao sau ay la hp le va khong hp le:

Giang vien: Nguyen Quang Minh

BT-VHDL-1/9

2. Cho cac khai bao tn hieu sau:

a) Hay ien vao cho trong:

b) Cac thao tac nao sau ay la hp le va khong hp le:

Giang vien: Nguyen Quang Minh

BT-VHDL-2/9

3. Cho mo ta VHDL sau:

Cau truc mach tong hp cua Y1 va Y2 co khac nhau khong ? Giai thch. 4. Viet ma VHDL mo ta cac mach sau:

Giang vien: Nguyen Quang Minh

BT-VHDL-3/9

(a) 5. Viet ma VHDL mo ta bang chan tr sau:

Hnh P4

(b)

Hnh P5 6. Viet mo ta VHDL cho mach don kenh tong quat sau:

Hnh P6 7. Dung cac phat bieu song song, viet ma VHDL cho bo cong 8-bit khong dau sau:

Hnh P7

Giang vien: Nguyen Quang Minh

BT-VHDL-4/9

8. Viet mo ta VHDL cho ALU sau dung cac phat bieu song song:

Hnh P8 9. Xay dng mach so sanh 2 vector 8-bit, a va b vi mot ngo vao chon sel xac nh so sanh so co dau (sel = 1) hay khong dau (sel = 0). Mach co 3 ngo ra x1, x2 va x3 tng ng vi a>b, a=b va a<b.

Hnh P9 Sa lai ma tren e tong quat hoa cho trng hp N-bit. 10. Viet mo ta VHDL thc hien mach chuyen oi t ma nh phan sang ma Gray 4-bit. 11. Thiet ke mach em cac bit 0 phan au cua mot vector nh phan, bat au t MSB. 12. Viet ma VHDL mo ta mach em so bit 1 trong vector nh phan ngo vao. 13. Viet ma VHDL mo ta mach cong tong quat 8-bit dung vong lap for. Tong quat hoa cho trng hp N-bit.

Giang vien: Nguyen Quang Minh

BT-VHDL-5/9

Hnh P13 14. Tm s o logic ng vi mo ta VHDL sau:

15. Thiet ke JK-FLIP-FLOP hoat ong theo canh len cua xung clock: a) Bnh thng vi 2 ngo ra q va q_n b) Co ngo vao reset bat ong bo c) Co ngo vao reset va preset bat ong bo 16. Hay viet ma VHDL e mo ta thanh ghi dch tong quat N-bit co ngo vao RST la reset bat ong bo tch cc mc 1, ngo vao LOAD = 1 se nap d lieu N-bit t ngo vao DATA vao thanh ghi dch (ong bo theo canh len xung CLK), khi RST = LOAD = 0 vaco canh len cua xung CLK th: - Dch trai ngo vao khi bit chon LR = 0. - Dch phai ngo vao khi bit chon LR = 1. D lieu vao noi tiep la SERIN. 17. Hay viet ma VHDL mo ta bo em len/xuong 4-bit, hoat ong theo canh len cua xung CLK: - Ngo vao chon UD = 0: em len, UD = 1: em xuong. - Ngo vao LOAD = 0 se nap d lieu 4-bit t ngo vao DATA vao bo em (ong bo theo canh len xung CLK). - Tn hieu cho phep bo em EN se ngng hoat ong em khi EN = 0, nhng van cho phep nap d lieu. - Ngo ra CO se bang 1 khi em len va bo em vong ve gia tr nho nhat (MIN_VAL, mac nh la 0000) hay em xuong va bo em vong ve gia tr ln nhat (MAX_VAL, mac nh la 1111). Gi y: Nen at MIN_VAL va MAX_VAL la hang so e de chnh sa ma khi can thiet. Giang vien: Nguyen Quang Minh
BT-VHDL-6/9

18. Viet ma VHDL mo ta mach em 2-digit (00 99 00) co mot ngo vao reset bat ong bo va ngo ra la 2-digit BCD. Mach hoat ong theo canh len cua xung CLK. 19. Tm s o logic ng vi mo ta VHDL sau:

20. Viet ma VHDL mo ta mach Full-Adder 1-bit, sau o dung no nh mot component e xay dng bo cong tong quat N-bit. 21. S dung JK-FF bai 15 nh component e thiet ke: - Bo em bat ong bo 4-bit. - Bo em BCD bat ong bo (gia s co san component AND2).

Giang vien: Nguyen Quang Minh

BT-VHDL-7/9

22. Viet ma VHDL mo ta mach tao tre d lieu lap trnh c nh tren hnh P22. Ngo vao d va ngo ra q la cac vector 4-bit. Phu thuoc vao ngo vao chon sel, ngo ra q se tre 1, 2, 3 hay 4 chu k xung clk so vi ngo vao d.

Hnh P22 23. Hnh P23 minh hoa cau truc cua mot thiet ke phan cap. Hai component, counter va register, c dung e xay dng mot mach mc cao hn lastop_watch. Counter se em len lien tiep moi khi co xung canh len cua clk va se reset moi khi tn hieu stop c kch hoat (mc 1). Trang thai cua counter phai c lu vao register ngay trc khi xay ra reset ngo ra. Khi stop tr ve 0, counter bat au em lai t 0, trong khi o register gi gia tr em trc o. Thiet ke hai component counter va register, sau o khi tao chung trong ma chnh xay dng mach stop_watch hoan chnh.

Hnh P23 24. Viet ma VHDL mo ta FSM sau:

Hnh P24

Giang vien: Nguyen Quang Minh

BT-VHDL-8/9

25. Viet ma VHDL mo ta cac FSM sau: - Ngo vao: Red, Green va Blue (theo th t tren hnh). - Ngo ra: NewColor. - He co mot ngo vao reset bat ong bo, tch cc mc 0 e at trang thai au la WhiteState.

Mealy

Moore

Hnh P25 26. Viet ma VHDL mo ta FSM vi ngo ra gom ca hai loai Mealy va Moore nh sau: - Ngo vao: A, Hold - Ngo ra: Y_Mo, Y_Me (ngo ra tren hnh ch ghi tai cac v tr tch cc (mc 1)).

Hnh P26

Giang vien: Nguyen Quang Minh

BT-VHDL-9/9