FUZZY LOGIC DESIGN USING VHDL ON FPGA

SHAM SAGARIA A/L MARISINAPEN

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING UNIVERSITI MALAYSIA PERLIS 2008

FUZZY LOGIC DESIGN USING VHDL ON FPGA

by

SHAM SAGARIA A/L MARISINAPEN

Report submitted in partial fulfilment of the requirements for the degree of Bachelor of Engineering

APRIL 2008

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ACK OWLEDGEME T

First and foremost I want to thank my God Almighty for allowing me to perform this project smoothly even though I face some obstacles throughout my project. I would like to express my gratitude to all those who gave me the possibility to complete this Final Year Project. I want to thank my Supervisor, En. Najmuddin B. Mohd Hassan for providing me his assistance and encouragement to go ahead with my project and for requesting approval to use laboratory tools and equipments required to perform my project. I have furthermore to thanks my School of Computer and Communication Engineering to provide me adequate tool and equipments to carry out my project.

I am very grateful for Cik. Shida, a postgraduate student from Mechatronic Cluster, UniMAP and my friend Edwin Sagayaraj, undergraduate student from School of Electrical System, UniMAP, whose help, stimulating suggestions and ideas on Fuzzy Logic based on their experience and project they are doing currently.

My special thanks all my family for supporting me through their prayers and words of encouragement to complete this project. Last but not least, thanks to my girlfriend for giving emotional support and forcing me to finish my project from time to time.

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APPROVAL A D DECLARATIO SHEET

This project report titled Fuzzy Logic Design using VHDL on FPGA was prepared and submitted by Sham Sagaria a/l Marisinapen (Matrix umber: 051020668) and has been found satisfactory in terms of scope, quality and presentation as partial fulfillment of the requirement for the Bachelor of Engineering ( Computer Engineering ) in Universiti Malaysia Perlis (UniMAP).

Checked and Approved by

_______________________ (E . AJMUDDI B. HASSA ) Project Supervisor

School of Computer and Communication Engineering Universiti Malaysia Perlis

April 2008

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REKABE TUK FUZZY LOGIC ME GGU AKA VHDL PADA FPGA

ABSTRAK

Rekabentuk fuzzy logic adalah untuk menghasilkan 3 keluaran daripada 7-input. Ketujuh input tersebut, yang setiapnya bersaiz 3-bit, dihasilkan daripada keluaran analog pengesan indung madu yang terdiri daripada 7 pengesan keterangan cahaya untuk mengenalpasti lokasi yang mempunyai keterangan cahaya yang paling tinggi. Signal analog ini ditukarkan signal digital, dan sinilah mulanya fungsi rekabentuk fuzzy logic ini. Rekabentuk ini menerima input digital dari pengesan indung madu yang membekalkan maklumat mengenai lokasi yang mempunyai keterangan cahaya yang paling tinggi. Dari input ini, rekabentuk fuzzy logic ini akan berfungsi untuk memilih keadaan yang sesuai untuk menghasilkan 3 keluaran untuk mengawal pergerakan tiga motor (mendatar, vertikal dan condong) yang memutarkan kepingan besi mengarah kepada lokasi yang mempunyai keterangan cahaya yang paling tinggi. Rekabentuk fuzzy logic ini akan menghasilkan 3 keluaran yang setiapnya bersaiz 3-bit, untuk setiap jenis pergerakan di mana bit MSBnya mewakili arah putaran kepingan besi tersebut and baki bitnya berfungsi untuk memberikan isyarat darjah putaran kepingan besi tersebut. Rekabentuk tersebut juga harus mampu untuk menyimpan posisi terkini kepingan besi untuk mengelakkan kesilapan pada system yang menggunakan output rekabentuk tersebut. Fungsi keseluruhan projek adalah untuk membolehkan penerimaan maksimum cahaya matahari untuk menjanakan kuasa elektrik mengunakan sistem solar.

ABSTRACT

This fuzzy logic design is to produce 3 outputs from a 7 input. The 7 digital input (3-bits each) is produced from the analogue output of the 7-input honeycomb sensor. The honeycomb sensor receives input from seven sensors which sense light ambient and produces analogue signal to acknowledge the location which receives the highest light ambient. This analogue signal is converted to digital signal and this where the fuzzy logic designs comes. The fuzzy logic receive 7 digital input which provide information on which location the light ambient is high. From this digital input, the fuzzy logic will choose the best behaviour to produce 3 outputs to control the movement of three motors (horizontal, vertical and tilt) which rotates a plate facing the location with the highest light ambient. The fuzzy logic design will produce a 2 output of 3-bits each and 1 output of 4-bits, for each type of movements which its MSB represent the direction of the plate rotation and the remaining bits is to indicate the plate rotation degree. The design also should be able to store the current position of the plate to prevent system error on the downstream when it uses the output of this design to rotate the motors. The overall function of this project is to enable reception of maximum sunlight to generate electrical power using solar system.

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TABLE OF CO TE TS

ACK OWLEDGEME TS APPROVAL A D DECLARATIO SHEET ABSTRAK ABSTRACT TABLE OF CO TE TS LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS, ABBREVIATIO S OR OME CLATURE

Page ii iii iv v vi ix x xi

CHAPTER 1 I TRODUCTIO 1.1 1.2 1.3 1.4 Background of the project Project Objective Project Scope Problem Statement

1 1 2 2 3

CHAPTER 2 LITERATURE REVIEW 2.1 Fuzzy Logic 2.1.1 2.1.2 2.1.3 History of Fuzzy Logic Fuzzy Logic? 5

4 4 4

Fuzzy Sets, Membership Functions and Logical Operators

5 8
10 11 14

2.1.4 Linguistic Variable and Rules Bases 2.1.5 Fuzzy Logic Models
2.1.6 2.1.7 Mamdani Modelling Sugeno Modelling

vii 2.1.8 2.2 Usage of Fuzzy Logic 15 16 16 16 17 18 19 20

Field Programmable Gate Array (FPGA) 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 History of FPGA What is FPGA FPGA Advantage Language Used in FPGA FPGA Used (Altera Cyclone EP1C6Q240C8) UP3 Educational Kit

CHAPTER 3 METHODOLOGY 3.1 3.2 Choosing Best Fuzzy Logic Method Fuzzification 3.2.1 3.2.2 3.2.3 3.3 3.4 3.5 Inputs Outputs Fuzzification

22 22 22 23 24 26 27 28 29

Rule Evaluation Defuzzification Display Result

CHAPTER 4 RESULTS A D DISCUSSIO 4.1 Result 4.1.1 4.1.2 4.2 Fuzzy Logic Design Output Motor Controller Output

30 30 30 31 33

Discussion

CHAPTER 5 CO CLUSIO 5.1 5.2 5.3 Summary Recommendation for Future Project Commercialization Potential

34 34 35 35

viii REFERE CES 37

APPE DICES Appendix A Appendix A(i) Appendix A(ii) Appendix A(iii) Appendix B

38 39 40 42 51 56

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LIST OF TABLES

Tables o.

Page

2.0 3.0

Truth tables for OR and NOT Operators Output Bits and its Representations

7 25

LIST OF FIGURES

Figures o.

Page

2.0

Example Fuzzy Set. S, small; MS, medium small; M, medium, ML, medium large; L, large.

2.1 2.2 2.3 2.4 2.5

2.6 2.7 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10

Sample three part Gaussian shaped MF Example of two valued and multi-valued logical operation Application of rules for lecture attendance example Mapping of input space to output space
Mamdani Fuzzy Control System [4] Diagram showing aggregation and defuzzification Implementation of Sugeno Model Location of the 7 Input Input Membership Functions Input Membership Function in VHDL Output Membership Function Output Membership Function in VHDL Programme to Obtain Degree of Membership Function Minimum Function Maximum Function Rules Evaluation Defuzzification VHDL Code

7 8 9 10 12 13 14 23 23 24 25 26 26 27 28 29 29 29 30 31 32 32 33

LCD Initialization in VHDL Fuzzy Logic Design Output Waveform LCD Initialization LCD Display During Motor Movements LCD Display After Motor Movements Output for Input F0h

4.0 4.1 4.2 4.3 4.4

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LIST OF SYMBOLS, ABBREVIATIO S OR OME CLATURE

VHDL VHSIC FPGA LCD CPLD ASIC PSL SVA PCB CAD VL L ML M MH H VH

VHSIC Hardware Description Language Very High Speed Integrated Circuit Field Programmable Gate Array Liquid Crystal Display Complex Programmable Logic Device Application Specific Integrated Circuit Property Specification Language System Verilog Assertions Printed Circuit Board Computer-Aided Design Very Low Low Medium Low Medium Medium High High Very High Degree of Membership Function Register Select Read / Write Enable Signal Liquid Crystal Display

RS R/W EN LCD

CHAPTER 1

I TRODUCTIO

1.1

Project Background This project is 2nd stage of a main big project; consist of 3 stages, which its

purpose is to obtain maximum sun exposure to allow maximum electricity generation using solar energy. The 1st stage is a honeycomb sensor which consists from 7 ambient sensor to detect the location with the highest ambient. The 2nd stage is to receive the input from the honeycomb sensor, decide the location with the highest ambient and provide appropriate input to the final stage of the project. The final stage is to rotate the plate (horizontally, vertically and tilt), which consist from material to convert solar energy to electrical energy such as solar cell, according the output given. This is done by rotating 3 motors which control each movement type.

This project, 7-Input 3-Output Fuzzy Logic Design using VHDL on FPGA, functions as a decision maker to define the location with the highest ambient and provide appropriate input to the downstream. This decision making is done using fuzzy logic algorithm which chooses the best behaviour from the input given to provide the best output to next stage after this project. The design will produce two, 3-bit outputs and one, 4-bit output by selecting the best behaviour from the seven, 3-bit input. Each output represents each movement and for the bits, its MSB represent the direction of the plate rotation and the remaining bits are to indicate the plate rotation degree. The design also should be able to store the current position of the plate to prevent system error on the downstream when it uses the output of this design to rotate the motors.

The algorithm, fuzzy logic used should be translated to a language understandable by FPGA. This is done by converting the fuzzy rules into VHDL

2 programming code. The program should consist of steps of the Fuzzy Logic process which depends on the model used to obtain the best result. The VHDL language can be compiled into FPGA using various type of software but for this project, Altera Quartus II is used, since it is easy to use and available for free for educational purpose. The program can be loaded to FPGA and tested using extra interface by availability of UP3 Educational Kit. Extra interface such as LCD Display, LEDs and switches can be used to display the result.

1.2

Project Objective

1. To produce 3 outputs using Fuzzy logic by providing the best behaviour based on the 7 inputs given. 2. To be able to use the digital output from the honeycomb sensor and provide an output that can be used for the controller unit. 3. To be able design a 3-Input 7-Output Fuzzy Logic using VHDL.. 4. Able to upload the VHDL code and run the program in UP3 board successfully. 5. To provide information on the current position of the motor.

1.3

Project Scope

1. At the end of this project, the 7 input 3 outputs fuzzy logic system should be able to create 3 digital outputs that suitable for Control Unit based on the 7 digital inputs from the honeycomb sensor. 2. This fuzzy logic design is designed using VHDL source code and will be executed using UP3 board. 3. The source code should be able error free and run without any problem using the UP3 board.

3 1.4 Problem Statement

1. Need to understand fully about Fuzzy Logic before the project can be started. 2. Since this project uses VHDL fully, it requires high knowledge on writing the VHDL source code. So knowledge on writing VHDL has to be improvised in a short period. 3. The knowledge level on the UP3 board used is low; have to gain extra knowledge on using the board. 4. This project is a part of the one large project so understanding how to use the input received from the upstream application to produce output required by downstream application is a must.

CHAPTER 2

LITERATURE REVIEW

2.1

Fuzzy Logic

2.1.1

History of Fuzzy Logic

Fuzzy logic was first proposed by Lotfi A. Zadeh of the University of California at Berkeley in a 1965 paper. He elaborated on his ideas in a 1973 paper that introduced the concept of "linguistic variables", which in this article equates to a variable defined as a fuzzy set. Other research followed, with the first industrial application, a cement kiln built in Denmark, coming on line in 1975. Fuzzy systems were largely ignored in the US because they were associated with artificial intelligence, a field that periodically oversells itself and which did so in a big way in the mid-1980s, resulting in a lack of credibility in the commercial domain.

The Japanese did not have this prejudice. Interest in fuzzy systems was sparked by Seiji Yasunobu and Soji Miyamoto of Hitachi, who in 1985 provided simulations that, demonstrated the superiority of fuzzy control systems for the Sendai railway. Their ideas were adopted, and fuzzy systems were used to control accelerating, braking, and stopping when the line opened in 1987. Another event in 1987 helped promote interest in fuzzy systems. During a international meeting of fuzzy researchers in Tokyo that year, Takeshi Yamakawa demonstrated the use of fuzzy control, through a set of simple dedicated fuzzy logic chips, in an "inverted pendulum" experiment. This is a classic control problem, in which a vehicle tries to keep a pole mounted on its top by a hinge upright by moving back and forth.

5 Observers were impressed with this demonstration, as well as later experiments by Yamakawa in which he mounted a wine glass containing water or even a live mouse to the top of the pendulum. The system maintained stability in both cases. Yamakawa eventually went on to organize his own fuzzy-systems research lab to help exploit his patents in the field. Following such demonstrations, the Japanese became infatuated with fuzzy systems, developing them for both industrial and consumer applications. In 1988 they established the Laboratory for International Fuzzy Engineering (LIFE), a cooperative arrangement between 48 companies to pursue fuzzy research. Japanese companies developed a wide range of products using fuzzy logic, ranging from washing machines to auto-focus cameras and industrial air conditioners.

Some work was also performed on fuzzy logic systems in the US and Europe, and a number of products were developed using fuzzy logic controllers. However, little has been said about the technology in recent years, which implies that it has either become such an ordinary tool that it is no longer worth much comment, or it turned out to be an industrial fad that has now generally died out.

2.1.2

Fuzzy Logic?

The primary objective of fuzzy logic is to map an input space to an output space. The way of controlling this mapping is to use if-then statements known as rules [2]. The order these rules are carried out in is insignificant since all rules run concurrently. The following sections will present and develop ideas such as sets, membership functions, logical operators, linguistic variables and rule bases.

2.1.3 Fuzzy Sets, Membership Functions and Logical Operators

Fuzzy sets are sets without clear or crisp boundaries. The elements they contain may only have a partial degree of membership. They are therefore not the same as

6 classical sets in the sense that the sets are not closed. Some examples of vague fuzzy sets and their respective units include the following. Loud noises (sound intensity) Ambient (brightness) High speeds (velocity) Desirable actions (decision of control space)

Fuzzy sets can be combined through fuzzy rules to represent specific actions/behaviour and it is this property of fuzzy logic that will be utilised when implementing a fuzzy logic controller in subsequent chapters. A membership function (MF) is a curve that defines how each point in the input space is mapped to the set of all real numbers from 0 to 1. This is really the only stringent condition brought to bear on a MF. A classical set may be for example written as: A = {x | x > 3}

Now if X is the universe of discourse with elements x then a fuzzy set A in X is defined as a set of ordered pairs: A = {x, A (x) | x X}

Note that in the above expression A (x) may be called the membership function of x in A and that each element of X is mapped to a membership value between 0 and 1. Typical membership function shapes include triangular, trapezoidal and Gaussian functions. The shape is chosen on the basis of how well it describes the set it represents. Below in Figure 2.1 some example fuzzy sets can be observed.

Figure 2.0: Example Fuzzy Set. S, small; MS, medium small; M, medium, ML, medium large; L, large.

Figure 2.1: Sample three part Gaussian shaped MF

Fuzzy logic reasoning is a superset of standard Boolean logic yet it still needs to use logical operators such as AND, OR and NOT. Firstly note that fuzzy logic differs from Boolean yes/no logic in that although TRUE is given a numerical value 1 and FALSE numerical values 0, other intermediate values are also allowed. For example the values 0.2 and 0.8 can represent both not-quite-false and not-quite-true respectively. It will be necessary to do logical operations on these values that lie in the [0,1] set, but two-valued logic operations like AND, OR and NOT are incapable of doing this. For this functionality, the functions min, max and additive complement will have to be used. The following examples are for the OR and NOT logical operations shown in Table 2.1 and Figure 2.3 show how this works.

Table 2.0: Truth tables for OR and NOT Operators

Figure 2.2: Example of two valued and multi-valued logical operation

2.1.4

Linguistic Variable and Rules Bases

Linguistic variables are values defined by fuzzy sets. A linguistic variable such as High Speed for example could consist of numbers that are equal to or between 50km/h and 80km/h. The conditional statements that make up the rules that govern fuzzy logic behaviour use these linguistic variables and have an if-then syntax. These ifthen rules are what make up fuzzy rule bases. A sample if-then rule where A and B represent linguistic variables could be: if x is A then y is B (2.0)

The statement is understood to have both a premise, if x is A, and a conclusion, then y is B. The premise also known as the antecedent returns a single number between 0 and 1 whereas the conclusion also known as the consequent assigns the fuzzy set B to the output variable y. Another way of writing this rule using the symbols of assignment = and equivalence == is: if x == A then y = B An if-then rule can contain multiple premises or antecedents. For example, if velocity is high and road is wet and brakes are poor then. Similarly, the consequent of a rule may contain multiple parts. If temperature is very hot then fan is on and throughput is reduced Interpreting these rules involves a number of distinct steps. (2.1)

9 1. Firstly, the inputs must be fuzzified. To do this all fuzzy statements in the premise are resolved to a degree of membership between 0 and 1. This can be thought of as the degree of support for the rule. At a working level this means that if the antecedent is true to some degree of membership, then the consequent is also true to that same degree. 2. Secondly, fuzzy operators are applied for antecedents with multiple parts to yield a single number between 0 and 1. Again this is the degree of support for the rule. 3. Thirdly, the result is applied to the consequent. This step is also known as implication. The degree of support for the entire rule is used to shape the output fuzzy set. The outputs of fuzzy sets from each rule are aggregated into a single output fuzzy set. This final set is evaluated (or defuzzified) to yield a single number.

The following example in Figure 2.4 shows how these steps are applied in practice. Consider the two rules for a fuzzy model that evaluates lecture attendance: 1. If (Lecture Quality) is Good) and (Interest Of Material is Interesting) then (Attendance is High) 2. If (Lecture Quality is Poor) or (Interest Of Material is Boring) then (Attendance is Low)

Figure 2.3: Application of rules for lecture attendance example`

10 The fuzzy AND operator is applied in rule one and since the premise of the rule is true to a high degree then the consequent is also going to be true to a high degree. In this example both the fuzzy AND operator and the implication operator use the min function, hence for an input of 50% for Lecture Quality and 80% for Interest Of Material, the defuzzified attendance percentage works out to be 75% (The details of implication and defuzzification are explained below in Section 2.3.6). This comes from
min( LectureQuality , InterestOfMaterial ) = min(1.0,0.75) = 0.75 (2.2)

Immediate advantages of this approach become apparent. Fuzzy sets can be combined using fuzzy rules to define system behaviour and thus complex non-linear systems can be expressed linguistically. In fact, as will be shown later, rule tables can represent fuzzy controllers. The process of fuzzifying a single crisp input, applying fuzzy operators and then defuzzifying to produce a single crisp output is known as fuzzy inference. This progression of modelling is discussed in detail in the next section.

2.1.5

Fuzzy Logic Models

Standard control techniques use numerical data to relate input and output signals. Fuzzy logic systems can use both numerical information and linguistic information to perform a mapping of an input to an output space. Consider the following diagram in Figure 2.5.

Figure 2.4: Mapping of input space to output space

11 Many different control mechanisms could reside within the black box but in this case the mechanism will be confined to a fuzzy logic system. Since the objective is to map inputs to outputs it becomes possible to model non-linear systems, even complex ones. This is one of fuzzy logics greatest advantages. Put differently, fuzzy logic systems are tolerant of imprecise data. When considered this suits many real-world applications well because as real-world systems become increasingly complex often the need for highly precise data decreases. The rules that govern this mapping can be acquired through two methods. The first is a method called the direct approach and the second is by using system identification.

The direct approach involves the manual formulation of linguistic rules by a human expert. These rules are then converted into a formal fuzzy system model. The problem with this approach is that unless the human expert knows the system well it is very difficult to design a fuzzy rule base and inference system that is workable, let alone efficient. For complex systems (non-linear for example) tuning these membership functions would require the adjustment of many parameters simultaneously. Understandably no human expert could accomplish this.

Fuzzy models that are designed using system identification are based on the use of input/output data. System identification was introduced to overcome the difficulties involved in the direct approach of choosing the fuzzy sets membership functions using a search/optimisation technique to aid the selection. The system identification method is covered in Chapter four. All of the previous elements of fuzzy logic that have been discussed up to this point are put together to form a fuzzy inference system (FIS). Two main types of fuzzy inference system exist the Mamdani and Sugeno type. They are both introduced in the following sections

2.1.6

Mamdani Modelling

Owing its name to Ebrahim Mamdani the Mamdani model was the first efficient fuzzy logic controller designed and was introduced in 1975 [1]. The controller consists

12 of a fuzzifier, fuzzy rule base, an inference engine and a defuzzifier. It is shown in the Figure 2.6 below.

Figure 2.5: Mamdani Fuzzy Control System [4]

Conventional control systems require crisp outputs to result from crisp inputs. The above representation shows how a crisp input in R can be operated on by a fuzzy logic system to yield a crisp output in Q. This Mamdani controller is realised using the following steps.

1. Fuzzification of Inputs
The fuzzifier maps crisp input numbers into fuzzy sets. The value between 0 and 1 each input is given represents the degree of membership that input has within these output fuzzy sets. Fuzzification can be implemented using lookup tables or as in this report, using membership functions.

2. Application of Fuzzy Operators

In the case where multiple statements are used in the antecedent of a rule, it is necessary to apply the correct fuzzy operators as explained in 2.2.2. This allows the antecedent to be resolved to a single number that represents the strength of that rule.

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3. Application of Implication Method

This part of the Mamdani system involves defining the consequence as an output fuzzy set. This can only be achieved after each rule has been evaluated and is allowed contribute its weight in determining the output fuzzy set.

4. Aggregation of all Outputs

The fuzzy outputs of each rule need to be combined in a meaningful way to be of any use. Aggregation is the method used to perform this by combining each output set into a single output fuzzy set. The order of rules in the aggregation operation is unimportant as all rules are considered. The three methods of aggregation available for use include sum (sum of each rules output set), max (maximum value of each rule output set) and the probabilistic OR method (the algebraic sum of each rules output set). An example of the aggregation process using the max operator can be seen in Figure 2.7 below.

5. Defuzzification of Aggregated Output

The aggregated fuzzy set found in the previous step is the input to the defuzzifier. As indicated in the model shown in Figure 2.6 this aggregated fuzzy set in Q is mapped to a crisp output point in Q. This crisp output is a single number that can usefully be applied in controlling the system. A number of methods of defuzzification are possible and these include the mean of maximum, largest of maximum, smallest of maximum and centroid (centre of area) methods. The centroid method is the most widely used and can be seen in Figure 2.7 below.

Figure 2.6: Diagram showing aggregation and defuzzification

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2.1.7

Sugeno Modelling

The Sugeno fuzzy model or more fully the Takagi-Sugeno-Kang method of fuzzy inference was first introduced in 1985 [2]. In many respects it is identical to the Mamdani method except that the output membership functions for the Sugeno method are always linear or constant. The output membership functions can be thought of as singleton spikes that undergo a simple aggregation instead of other aggregation methods such as max, probor or sum.

Figure 2.7: Implementation of Sugeno Model

Figure 2.8 shows the application of three basic rules for a Sugeno model. All three rules have been written using the OR connector. For example: if input1 is x or input2 is y then output1 is z

The method of defuzzification is the weighted average (as marked by the thin line in the bottom right corner of the figure). The output is always a single number and in this case having the inputs [0.5 input1, 0.8 input2] and the output is [6.64 output1]. The

Sugeno system is computationally efficient and its ability to interpolate multiple linear models makes it particularly suited to modelling non-linear systems.

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2.1.8

Usage of Fuzzy Logic

Today, computers have a good capacity for decision making for processes. However this is limited to systems which have a mathematical interpretation with the lack of human reasoning. Computers use binary logic and hence can only allow for values 1 for true and 0 for false. Statements like this car is not fast enough or this person is quite smart are rather vague statements which cannot be interpreted by the classical logic.

To handle this vagueness, fuzzy logic provides an extension from the classical logic. Fuzzy logic starts with and builds on a set of user-supplied human language rules. The fuzzy systems convert these rules to their mathematical equivalents. This simplifies the job of the system designer and the computer, and results are in much more accurate representations of the way systems behave in the real world.

Additional benefits of fuzzy logic include its simplicity and its flexibility. Fuzzy logic can handle problems with imprecise and incomplete data, and it can model nonlinear functions of arbitrary complexity.

A fuzzy system can be created to match any set of input-output combination. The rule inference system of the fuzzy model consists of a number of conditional "ifthen" rules. For the designer who understands the system, these rules are easy to write, and as many rules as necessary can be supplied to describe the system adequately.

Professor Lofti Zadeh at the University of California formalized Fuzzy Set Theory in 1965. What Zadeh proposed has been more influential than its initial acceptance in the Far East. Its success in many control applications has ensured its adoption around the world. Fuzzy logic has been applied in many areas, gaining wide acceptance in Japan and many other countries like USA. Household appliances such as dishwashers and washing machines use fuzzy logic to determine the optimal amount of soap and the correct water pressure for dishes and clothes. Fuzzy logic is even used in self-focusing cameras.

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2.2

Field Programmable Gate Array (FPGA)

2.2.1

History of FPGA

The historical roots of FPGAs are in complex programmable logic devices (CPLDs) of the early to mid 1980s. A Xilinx co-founder invented the field programmable gate array in 1984. CPLDs and FPGAs include a relatively large number of programmable logic elements. CPLD logic gate densities range from the equivalent of several thousand to tens of thousands of logic gates, while FPGAs typically range from tens of thousands to several million.

The primary differences between CPLDs and FPGAs are architectural. A CPLD has a somewhat restrictive structure consisting of one or more programmable sum-ofproducts logic arrays feeding a relatively small number of clocked registers. The result of this is less flexibility, with the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand, are dominated by interconnect. This makes them far more flexible (in terms of the range of designs that are practical for implementation within them) but also far more complex to design for.

Another notable difference between CPLDs and FPGAs is the presence in most FPGAs of higher-level embedded functions (such as adders and multipliers) and embedded memories. Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running.

2.2.2

FPGA

FPGA is device that contains a matrix of reconfigurable gate array logic circuitry. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR and NOT or more complete combinational functions such as decoders or simple mathematical functions. Most FPGA includes memory elements in these programmable logic components which

17 consist of simple flip-flops or more complete blocks of memory. When FPGA is configured, the internal circuitry is connected in a way which creates a hardware implementation of the software application. Unlike processors, FPGAs uses dedicated hardware for processing logic and doesnt require an operating system.

The performance of an application is not affected when additional process added to the FPGA since is parallel in nature and do not have to compete to use the same resource. FPGA can enforce critical interlock logic and can be designed to prevent I/O forcing by an operator. Unlike hardwired printed circuit board (PCB) designs, which have fixed and limited hardware resources, FPGA based system can literally rewire its internal circuitry to allow reconfiguration after the control system is deployed to the field. FPFA devices deliver more performance and reliability of dedicated hardware circuitry. Thousands of discrete components can be replaced by using a single FPGA which incorporate millions of logic gates in a single integrated circuit. The internal resources of an FPGA chip consists of a matrix of configurable blocks (CLB) connected to periphery of I/O blocks. Signal are routed within FPGA matrix by programmable interconnect switched and wire routes.

2.2.3

FPGA Advantage

FPGA have many advantages. One of that many advantage of FPGA is the only unified flow that allows you to design for any silicon, vendor as well as language. The various silicones are PLD, Platform FPGA, structured ASIC, ASIC Prototypes, ASICs and SOCs. There are also many vendors available such as Altera, Xilinx, Actel, Atmel, ChipExpress, Lattice and etc. There are many languages that can be used to program a FPGA such as VHDL, Verilog, System Verilog, C, C++, PSL and SVA.

FPGA is good used for large designs and it is also reconfigurable. When creating designs, we can use simple VHDL or verilog commands to design a complex FPGA design. Moreover, by using FPGA, it is able to deliver the technical edge such as optimizing FPGA time closure with Precision Synthesis, advanced timing analysis and optimizing timing closure with I/O optimization and PCB integration. FPGA is also able

18 to optimize the design process by reducing by half the design time with rapid development process [6].

2.2.4

Language Used in FPGA

To define the behaviour of the FPGA the user provides a hardware description language (HDL) or a schematic design. Common HDLs are VHDL and Verilog. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA Companys proprietary place-androute software. The VHSIC Hardware Description Language (VHDL) has been under development for the past five years. The language definition is now stable and tools are starting to become available. This paper summarizes the development of VHDL, describes the current status of the language and related tool development efforts, and discusses the future of the language. The main motivation for the development of VHDL technology has been the need for a standard medium of communication for transmitting hardware design data from one organization to another. Such communication is necessary for a variety of reasons. First, from the viewpoint of the hardware component vendor, it allows formal specification of the behaviour of that component. Second, from the viewpoint of a component user, it allows formal specification of the functionality required of that component for procurement purposes. Third, from the viewpoint of the hardware design engineer, it provides a standard for sharing information within a design team, even among designers working at different levels of abstraction. Finally, from the viewpoint of the CAD tool developer, it provides a wider user-base for tools, thereby creating a better return on investment. In response to the above requirements, VHDL has been designed to be the standard medium for communicating hardware design data, thus meeting the needs of vendors, users, designers, and CAD tool developers. Furthermore, a core set of tools is being developed in order to support the language [5].

19

2.2.5

FPGA Used (Altera Cyclone EP1C6Q240C8)

The Cyclone field programmable gate array family is based on a 1.5-V, 0.13m, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66 MHz and 33MHz, 64-bit and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices [7]. Below are the features for the Cyclone FPGA: 2,910 to 20,060 LEs, Up to 294,912 RAM bits (36,864 bytes) Supports configuration through low-cost serial configuration device Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards Support for 66 MHz and 33 MHz, 64-bit and 32-bit PCI standard High-speed (640 Mbps) LVDS I/O support Low-speed (311 Mbps) LVDS I/O support 311-Mbps RSDS I/O support Up to two PLLs per device provide clock multiplication and phase shifting Up to eight global clock lines with six clock resources available per logic array block (LAB) row Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

20

2.2.6

UP3 Educational Kit

The UP3 Education Kit provides a powerful educational support and also a lowcost solution for prototyping and rapidly developing products. The board serves as an excellent means for system prototyping, emulation and hardware as well as software development. The board comes with a powerful Altera Cyclone FPGA. It gives scope to a hardware design engineer to design, prototype and test IP cores or any hardware design using HDLs like Verilog or VHDL. The entire environment helps to quickly implement any processor as well as any real time operating system on the kit. Along with that one can simulate and test C or assembly code also. The board has industry standard interconnections, Memory Subsystem, Multiple clocks for system design, JTAG Configuration, expansion headers for greater flexibility and capacity and additional user interface features. The board can be used for DSP applications by interfacing directly to a DSP processor or implementing DSP functions inside the FPGA. In short, it is a dual-purpose kit, which can be used for prototyping and developing VLSI designs as well as designing and developing microprocessor based embedded system designs [8]. The following are some of the features of the UP3 Education Kit: Features an Altera EP1C6Q240 Device and EPCS1 configuration devices Supports intellectual property based(IP-Based) design both with and without a microprocessor USB 1.1 (Full speed & Low speed) RS 232 Port (Full Modem) Parallel port (IEEE1284) PS/2 Port VGA port IDE (Integrated Drive Electronics) 128KBytes of SRAM (64K X 16) 2MBytes of FLASH (1M X 16) 8MByte SDRAM (4M X 16) 2KBytes of I2C PROM (Expandable) Supports multiple clocks like PCI clock, USB clock, IOAPIC, clock and CPU clock.

21 JTAG and Active Serial download capability 5V Santa Cruz long Expansion Card Header provides 72 I/O for the development of additional boards providing various functionalities One user definable 4-bit switch block Four user definable push button switches, and one global reset switch Four user definable LEDs One 16X2 character display LCD Module I2C Real Time Clock

22

CHAPTER 3

METHODOLOGY

3.1

Choosing Best Fuzzy Logic Method

The widely used method for Fuzzy Logic is Mamdani Style because of its simplicity and its compatibility with human made decision. Although Mamdani Style is widely used, it is not suitable for this project implementation. This is because the Mamdani method requires finding the centroid of a two-dimensional shape by integrating across a continuously varying function [10]. This method is not computationally efficient. It is also not suitable because its output use triangle or trapezoidal membership function to describe the output and its defuzzification calculation is complicated to be done in VHDL despite the results are not necessary effective or better. Sugeno style is much more suitable to be used in this project. This is because, the output of this method, uses a single spike, singletons to describe the outputs where there is a unity at single particular point and zero elsewhere. This causes all the output of each fuzzy rule to be constant [11].

3.2

Fuzzification

Before fuzzification is done, the input membership function and the output membership function have to be defined. For this project, it has 7 inputs of 3 bits each, 2 output of 3 bits each and 1 output of 4 bits. The 7 input defines the location which receives the highest light ambient and 3 outputs define the direction of motor rotation to obtains the maximum amount of sun exposure.

23 3.2.1 Inputs

The are total of 7 Inputs which each of the represents a location and the Fuzzy Logic Design should be able to detect the location with the highest light ambient. The location of the each input is shown in Figure 3.0 below.

7 6

2 3 4

Figure 3.0: Location of the 7 Input`

Each of inputs is represented by 7 membership functions, which are VL (Very Low), L (Low), ML (Medium Low), M (Medium), MH (Medium High), H (High) and VH (Very High). All the membership functions are represented by trapezoidal and triangular membership function. The membership function of this input is shown in Figure 3.1

Figure 3.1: Input Membership Functions

24 Each of the membership functions are defined by two points and two slopes. The slope is calculated by the Equation 3.0.
( y 2 y1) ( x 2 x1) (3.0)

For an example, the 1st point for the membership function VL is 00h and the 2nd point is 24h. The 1st slope for membership function VL is FFh since the 1st slope is a straight line and the 2nd slope is calculated using the Equation 3.0. The equation 3.1 is an example of the calculations. 2nd Slope for Membership function, VL, => ( FFh 00h) FFh = = 07 h (48h 24h) 24h (3.1)

VHDL code to declare the input membership function is shown in Figure 3.2.

Figure 3.2: Input Membership Function in VHDL

3.2.2

Outputs

There is total of 3 outputs which two of them are 3-bit in size and one of them is 4-bit in size. The 3-bit output is to control the horizontal and vertical motor movement and the 4-bit output is tilt motor movement. Each of the bits represents the degree and the direction of the rotation. There are total number of 17 movement is designed for the output which each of the represented by the output bit. If all the output bits are 0, it represents the home position (Position 1) or the reset position which indicates the original position of the motor. The bit and the movement it represents are shown is the Table 3.0 below

25

Motor Type

Tilt

Vertical

Horizontal

Table 3.0: Output Bits and its Representations Direction of Degree of Bit Representation Position Rotation Rotation 0 4 1 1 1 Top Right 30 1 5 1 1 0 Top Right 60 0 0 1 1 Bottom Right 8 30 1 9 0 1 0 Bottom Right 60 0 12 0 0 1 Bottom Left 30 1 13 0 0 0 Bottom Left 60 0 14 1 0 1 Top Left 30 1 15 1 0 0 Top Left 60 0 1 1 Top 2 30 1 3 1 0 Top 60 0 10 0 1 Bottom 30 1 0 0 Bottom 11 60 0 6 1 1 Right 30 1 7 1 0 Right 60 0 0 1 Left 16 30 1 17 0 0 Left 60

Hex Code 2Dh 3Ch 69h 78h A5h B4h C3h D2h 0Fh 1Eh 87h 96h 4Bh 5Ah E1h F0h

Each of the position of the output is represented by a singleton membership function. Each of the singleton membership function is shown in the Figure 3.3 and the VHDL code to declare the output of singleton membership function is shown in Figure 3.4.

Figure 3.3: Output Membership Function

26

Figure 3.4: Output Membership Function in VHDL

3.2.3

Fuzzification

In fuzzification, the degree of input membership function is determined. This is done by locating the location of the input in the membership function and determines the degree of the membership function. The degree of the membership function is from 0 to 1 where in this project, it is represent by 00h and FFh. The calculation of the degree of the membership function, can be divided into three categories, which are: Before point1: = 0. After point1 but before point 2: = (input po int 1 ) slope1 After point2: = FF (input po int 1) slope 2 (3.2) (3.3) (3.4)

These equations are used in VHDL to obtain the degree of membership function. The calculation to obtain the degree of membership function written in VHDL is shown in Figure 3.5. The number 7 represents the number of membership function and the variable u represents the degree of membership function.

Figure 3.5: Programme to Obtain Degree of Membership Function

27

3.3

Rule Evaluation

The degree of membership is determined in the fuzzification stage. The next step is to create rules to decide what action should be taken in response to the given set of degree of membership function. There standard fuzzy operator which can be used to define a rule are AND, OR and NOT. The AND and OR fuzzy operators are best used for rules with multiple antecedents. The fuzzy operator, OR is used to evaluate the disjunction of the rules antecedents and AND is used to evaluate the conjunction of the rules antecedents. AND fuzzy operator is since it is required to evaluate the conjunction of the rules antecedents. Since AND is the minimum operation between multiple antecedents, the minimum function is used. The OR fuzzy operator also can be used when more than one rules involved with the same output. Below is the example of implementation of rules and the minimum and maximum. For OR => For AND => C = maximum (A,B) C = minimum (A,B)

For rules with same output => C = maximum (minimum (A1,B1), minimum (A2,B2)) The minimum and maximum function used to obtain the result from the each rules evaluation between multiple antecedents is shown in Figure 3.6, Figure 3.7 and Figure 3.8.

Figure 3.6: Minimum Function

28

Figure 3.7: Maximum Function

Figure 3.8: Rules Evaluation

A total number rules that should be produced to describe the complete fuzzy control strategy can be calculated by multiplying the input membership function with the output membership function. Although there millions of possible rules, most of them can be discarded as long as the design is able to determine how the fuzzy control system should be operated.

3.4

Defuzzification

After the output for the each rule has been identified, the next step is to combine all the output into a single value that can used to control the motors. This process is done through defuzzification. The defuzzification technique used in Sugeno method is weighted average. This is done by multiplying fuzzy output obtained from the rules evaluation with its corresponding singleton value, then sum of this value is divided by the sum of all fuzzy output obtained from the rules evaluation. The result from this calculation is the final single output which can be used to control the motor movements. The VHDL code of the defuzzification function is shown in Figure 3.9

29

Figure 3.9: Defuzzification VHDL Code

3.5

Display Result

The output of the result is displayed using LCD. The LCD is used to show the current position of the motor. To allow the result to be displayed to the LCD, it had to be initialized first. This initialization is done by setting the interface data length, numbers of lines, character fonts, turning on the LCD and setting the Entry Mode. When initializing or sending commands to the LCD, the Register Select, RS pin and the Read/Write, R/W pin should be set to 0 while for writing characters to the LCD RS pin should be set to 0 and R/W remain 0. Each time a data is sent to LCD, the signal 1 should be sent to LCDs Enable Signal, EN pin to enable the LCD to display data or process commands.

Figure 3.10: LCD Initialization in VHDL

30

CHAPTER 4

RESULT & DISCUSSIO

4.1

Result

4.1.1

Fuzzy Logic Design Output

The waveform shown in the Figure 4.0 is the output of the fuzzy logic design in VHDL. Since there is no division symbol supported by Quartus II Compiler, a divider circuit have to be designed to perform defuzzification. The input in the waveform below is set to the condition to provide output for all seventeen positions of the motor. Each position is represented by hexadecimal number which used as an input to the motor controller. The hexadecimal number for the each position is indicated in Table 3.0. From the graph, the result obtained is as required by the projects objective. The next step is to simulate this output to control the rotations of the motor.

Figure 4.0: Fuzzy Logic Design Output Waveform

31 4.1.2 Motor Controller Output

This is where the output from the fuzzy logic design is used to control the motor so it can be rotated to the position required and displays the current position of the motor. Figure 4.1 is the output waveform for initializing LCD. From the figure, the Register Select, RS signal is set to 0. In this condition, the data received by the LCD is read as commands. Then Enable Signal, EN should be enabled when sending data to LCD. The LCD will not read characters or commands if it is not enabled. The H, T and V Output are the output bits send by the controller to control the motor.

Figure 4.1: LCD Initialization

The following figure, Figure 4.2, is the data displayed once an input is received. This output is to display PLEASE WAIT*** characters on the LCD while the motor rotation is in process. The feedback for the motor signal can be removed if it is not

32 requires. It is just as safe precaution to prevent new data sent to the motor before it finished its current movements.

Figure 4.2: LCD Display During Motor Movements

The Figure 4.3 is the Display on the LCD after the motor movement. In this waveform, all the result displayed is 00 since the input value refers to Position 1, which is the reset position (home position).

Figure 4.3: LCD Display After Motor Movements

33 The EN signal has to be set to 0 to prevent the data received after the data being displayed is read as characters or as commands. The following figures is to show the output signal when other input is provided.

Figure 4.4: Output for Input F0h

Figure 4.5: Output for Input 5Ah

4.2

Discussion

The project is achieved its most of the objective which is mainly to provide best behaviour to control the motors based of the input given. It has proved that the fuzzy logic implementation in creating this design in VHDL is highly effective. One of objective has yet to achieved since all the programmes has not yet successfully loaded

34 into the UP3 board due of time constraint. However, by studying the waveform, it indicates the output required for this project to function properly is obtained. The design was able to provide best output based on the input provided. However there is a probability that this design might unable to give it best output for certain condition but this error can be solved by providing different conditions to the design to make sure it is able to provide output for all types of conditions. If there is certain condition that are not met its requirement, it can easily solved just by adding relevant rules.

34

CHAPTER 5

CO CLUSIO

5.1

Summary

Described fuzzy controller uses linguistic descriptions to define the relationship between the input information and the output action. For designing a rule base of a controller, a high- level modelling approach in VHDL have to be used. The advantages of this are reducing the design time, evaluation of the design functionality in a short time and quickly exploring of different design choices.

Once the basic design of the fuzzy logic control system has been defined, the implementation of the fuzzy logic controller is very straight forward by coding each component of the fuzzy inference system in VHDL according to the design specifications. The availability of different synthesis tools for the programmable logic devices such as FPGA and CPLD have made it easier for the designers to experiment their design capabilities. By simply changing some parameters in the codes and design constraint on the specific synthesis tool, one can experiment with different design circuitry to get the best result in order to satisfy the system requirement.

Fuzzy Logic provides a different way to approach a control or classification problem. This method focuses on what the system should do rather than trying to model how it works. One can concentrate on solving the problem rather than trying to model the system mathematically, if that is even possible. On the other hand the fuzzy approach requires a sufficient expert knowledge for the formulation of the rule base, the combination of the sets and the defuzzification. In General, the employment of fuzzy logic might be helpful, for very complex processes, when there is no simple

35 mathematical model, for highly nonlinear processes or if the processing of expert knowledge is to be performed. According to literature the employment of fuzzy logic is not recommendable, if the conventional approach yields a satisfying result, an easily solvable and adequate mathematical model already exists, or the problem is not solvable.

5.2

Recommendation for Future Project

The project is basically just based on normal LCD display with simple push buttons but itll much easier if can be control by a user-friendly interface. The interface can be improved by providing user-friendly software to control and to view the movement and the condition of the motor. This enables the users to control the design from location far from motor and the light ambient sensor locations. This project also can be improved by adding more rules to enable it to function in various conditions. Since the fuzzy logic implementation is effective in this project, input with higher variance can be added and more rules can be added to make is more functional and effective.

5.3

Commercialization Potential

This product is to obtain the maximum sun exposure for providing maximum solar energy to generate electricity. By using this, electricity cost can be saved. This is because the sun position didnt remain same at all times. It changes from time to time. This prevents maximum sun exposure obtained during certain periods of the day. During this period, the solar cell unable to obtain sun exposure because of the position of sun it not exposed fully on the plate. By using this project material, the maximum sun exposure can be obtained and larger energy can be reserved. However, this method is not suitable for small solar energy users such as normal usage at home, shops and etc because of the power required is not much but the power used to control this product is

36 higher. By using this, big industries can use solar energy as their main power source by obtaining maximum sun exposure at the same time reserve high amount of solar energy.

37

REFERE CE

[1]

Goldberg, David E., (1989). Genetic Algorithms in Search, Optimization and Machine Learning. Addison Wesley. USA. Mathlab Fuzzy Logic Toolbox Manual. Mathworks Michael Negnevitsky, (2005). Artificial Intelligence A Guide to Intelligent Systems. Addison Wesley. USA. Dadios, Elmer P. and Williams, David J., (1996). A Fuzzy-Genetic Controller for the Flexible Pole-Cart Balancing Problem. Proceeding of IEEE International Conference on Evolutionary Computation. Moe Shahdad, (2001). An Overview of VHDL Language and Technology, pp. 320-236. How to Choose CLPD and FPGA http://www.velocityreviews.com/forums/t56130-where-to-use-cpld-amp-whereto-use-fpga.html, 23 Feb 2008 Altera Corporation, (2007). Cyclone Device Handbook Volume 1, San Jose, California. Altera Corporation, (2004). UP3 Educational Kit Reference Manual, Cyclone Edition, Morgan Hill, California. Timothy J. Ross, (2004). Fuzzy Logic with Engineering Applications. 2nd Edition, John Wiley & Sons, Ltd. USA. Andrew Kusiak (2004), Fuzzy Logic, The University of Iowa, Iowa City

[2] [3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

Philip T. Vuong, Asad M. Madni and Jim B. Vuong. VHDL Implementation for a Fuzzy Logic Controller. BEI Technologies Inc., California, USA.

38

APPE DICES

39

APPE DIX A

40 Appendix A(i): Input Program

41

42 Appendix A(ii): Fuzzy Logic Design in VHDL

43

44

45

46

47

48

49

50

51 Appendix A(iii): Output Program

52

53

54

55

56

APPE DIX B