CMOS FABRICATION & LAYOUTS

SCHEMATIC CROSS SECTION OF MOSFET

1. Gate Oxide and Field oxide layer: Gate oxide is the layer below which channel is formed and Field oxide is for isolation of devices. They are formed by using thermal oxidation: Provides highest quality oxides using lowest interface trap densities.
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2. Dielectric layers: For insulation between conducting layers and diffusion and ion implantation masks, for capping doped films to prevent loss of dopants, for passivation to protect devices from impurities, heat, moisture and contamination and scratches. : CVD techniques
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3. Poly silicon: For gate electrode and contact material of shallow junctions etc. : CVD techniques. 4. Metallization: For interconnections, ohmic contacts, etc. 5 :PVD techniques.

Summary of Conventional Microfabrication Modules Basic Process Modules: growth, wafer fabrication Semiconductor manufacturing, wafer cleaning and gettering Lithography Thermal Oxidation Etching (Chemical , Plasma) Ion Implantation Diffusion Physical Vapor Deposition PVD Chemical Vapor Deposition CVD & Epitaxial Growth Chemical Mechanical Polishing CMP
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Crystal

Ge

1950s Narrow BG (0.66 eV) High junction leakage currents Operate up to 100C Intrinsic resistivity 47 Ohm-cm. Hence, HV rectifying devices not possible. Germanium Oxide unsuitable for device applications EGG more costly Difficult to grow high quality oxide

GaAs

One element oxidizes faster to other, leaving a metallic phase at the interface Difficult to dope Difficult to get high crystal perfection and large diameters Wide BG (1.1 eV)

Si

Less junction leakage currents Operate up to 150C Intrinsic resistivity = 2,30,000 Ohm-cm. Hence, High voltage rectifying devices are possible. Si dioxide suitable for device applications (more planar) EGS Cheap
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Polysilicon Crystal structure

Si Crystal Structure

Create N-well (for PMOS devices) & Channel Stop Regions

Impurity Implant Into The Substrate.

Grow Field & Gate Oxide

Thick Around The nMOS And pMOS Active Regions And Thin Respectively Through Thermal Oxidation.

Deposit & Pattern Poly Layer

Implant S, D & Substrate Contacts

Creation Of n+ And p+ Regions.

Create Contact Windows Deposit & Pattern Metal Layer

Metallization

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PHOTOLITHOGRAPHY IC Is Set Of Patterned Layers Of Doped Silicon, Polysilicon, Metal And SiO2. All Areas Are To Be Defined By Proper Masks. A Layer Must Be Patterned Before Another Is Applied On The Chip. Every Layer Will Undergo Lithography With Different Mask.
SiO2

SiO2 layer by thermal oxidation

SiO2

Si Substrate

Si Substrate

Unpatterned Structure

Photolithography

Patterned Structure

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Chemical or Dry Etch Hardened Photoresist Si Substrate Si Substrate

Si Substrate

1mm SiO2 layer by thermal oxidation

Hardened Photoresist SiO2 Window reaching down to Si Substrate Si substrate

Si Substrate

Light Sensitive, Acid Resistant Organic Polymer = Photoresist

Hardened photoresist removed by stripping solvents.

Si Substrate UV Light Glass Mask Insoluble Photoresist Si Substrate

Obtained Patterned SiO2 feature on the Si Substrate

Soluble Photoresistv

For High Density Patterns Required In Sub Micron Devices, E-beam Lithography Is Used Instead Of Optical Lithography.
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a) Positive photoresist

b) Negative photoresist
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PHOTORESISTS Positive :

(not sensitive to > 0.5 microns)

Exposed regions become more soluble. Hence , easily removed in the developing process. Patterns formed are same as that of masks. Consists of photosensitive compound, a base resin, and an organic solvent. Initially photosensitive compound is insoluble in the developer solution. After exposure, its chemical structure changes due to absorption of the radiations. After development, exposed areas are removed.
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Negative : Exposed regions become less soluble. Hence , cant be removed in the developing process. Patterns are mirror images of the mask patterns. It consists of polymers combined with photosensitive compound . Initially less insoluble in the developer solution. After exposure, its chemical structure changes due to absorption of the radiations. Optical energy is converted into chemical one which initiates a polymer cross linking reaction. Cross linked polymers have more molecular weight and they become more insoluble in the developer solution. After development, unexposed areas are removed. Developer solution is absorbed here and there is 16 swelling of the resist mass. Hence limited resolution.

Fabrication of nMOS: Basic steps

Si Substrate
OXIDATION

Si Substrate
Deposition of polysilicon

Thin high quality Oxide Layer (gate oxide)

(gate + interconnect medium) Thick Oxide layer (field oxide)

Si Substrate
SELECTIVE ETCHING FOR DEFINING ACTIVE AREA ON WHICH MOSFET WILL BE FABRICATED

Si Substrate
Patterned and etched
polysilicon

oxide

gate oxide

Si Substrate

Si Substrate
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Fabrication of nMOS: Basic steps

Patterned and etched
polysilicon oxide

Insulating oxide
gate oxide n+ n+

Si Substrate

Bare Si surface to form S & D

Patterned and etched

Doping : Diffusion or ion implantation (high concentration of impurity atoms)
polysilicon oxide n+ n+ 19 n+ gate oxide n+

Contact windows for D&S

Fabrication of nMOS: Basic steps

Evaporated Aluminum
n+ n+

Patterned and etched Metal contacts

n+

n+

By creating another insulating oxide layer, cutting contact holes (via), depositing and patterning metal, two more layers of metallic interconnects can also be added on the top of this structure.
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CHALLENGES:
Electrical isolation on a single chip containing many devices is necessary To prevent undesired conducting paths; To avoid creation of inversion layers outside the channels; To reduce leakage currents.

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DEVICE ISOLATION TECHNIQUES:

I) ETCHED FIELD OXIDE ISOLATION: Devices are created in dedicated regions called active areas. Each active area is surrounded by thick oxide barrier called field oxide. Thick oxide is grown on complete surface of the chip and then selectively etched to define active areas. Straight forward method. Thickness of oxide leads to large oxide steps at the boundaries of active areas and isolation regions. May lead to chip failure due to cracking of deposited layers due to large height difference at the boundaries.

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DEVICE ISOLATION TECHNIQUES: II Local oxidation of silicon

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LOCOS technique is based on the principle of selectively growing the field oxide in certain regions , instead of selectively etching away active areas after oxide growth. For selective growth of oxide, active areas are covered with Silicon nitride.
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DEVICE ISOLATION TECHNIQUES:LOCOS

Thin PAD OXIDE (stress relief oxide)
Si Substrate

Protects Si surface from stress caused by nitride during subsequent process steps. Si3N4

(Patterned and etched)

Si Substrate

(Doping of exposed Si surface with p type impurity) Si3N4

p+ p+

Si3N4
p+

Isolation Regions (Channel stop implants)

Si Substrate

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Si3N4

Si3N4

Thick Field Oxide which partially recesses into Si substrate

p+

p+

p+

Si Substrate

Birds beak ** Reduces active area

Lateral extension under nitride layer

(Patterned and etched)

THE ACTIVE AREAS

LOCOS is popular : More planar surface topology

p+

p+

p+

Birds beak encroachment can be reduced up to some limit by device scaling

Si Substrate

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DEVICE ISOLATION TECHNIQUES:

III) MULTILEVEL INTERCONNECTS & METALLIZATION: 4 to 8 metal layers are used to create interconnections between the transistors and for routing the power supply, signal lines and clock lines on the chip surface. Allows higher integration densities. Adds to the third dimension. Electrical connections between the layers are made by vias. Each via is formed by creating an opening in isolation oxide before every metallization step and filling it with a special metal plug (Tungsten). After creation of via, new metal layer is deposited and subsequent patterning is done.
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SOME FACTS: Due to various process steps chip surface is highly nonplanar. It may inhibit local thinning and discontinuities at uneven surface edges. Deposition of multiple metal interconnect lines is not desirable on such irregular topography. They will lead to hills and valleys on the chip surface. Hence surface is usually planarised before every new metal deposition step. For this, a fairly thick SiO2 layer is grown on the wafer surface to cover all existing surface nonuniformities. Its surface is then planarised by any one of: Glass reflow (heat treatment), Etch back, Chemical mechanical polishing (CMP). CMP: Actual polishing of wafer surface using abrasive silica slurry. 32 Adopted in recent years.

EXERCISE:
*Epitaxial layer ** Difference between ion implantation and diffusion processes of doping. *** Design masks for all patterning and etching steps in the fabrication of nMOS transistor for positive and negative photoresist material.
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