Computer Architecture Project Lab 10 Design of a 4-bit Arithmetic-Logic Unit using VHDL Joe Jackson Thursday April 24,

2008 CENG 3511 Tony Kolluri

Abstract The objective of the project is to implement a four-bit arithmetic logic unit from
a central processing unit using two approaches. The first being a structural design, using componentized VHDL code to create separate units for an arithmetic unit, a logic unit, and a shifting unit, using Boolean expressions, and to port map them together into one functioning arithmetic logic unit. The second approach is a behavioral one, using C style code to implement the same design. In a direct comparison between the two approaches, the general conclusion drawn is that the structural design is more efficient, while having more obfuscated coding, and the behavioral design is less efficient, with direct, quickly written, and very readable code.

Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p5

I. Introduction
In general computer architecture, the central processing unit of a computer is made of two main units, with several supporting systems; one of the two main units is called the ALU, or arithmetic-logic unit. This structure takes inputs, performs various calculations or logical operations on the inputs, and returns an output. While the calculations and logical operations can be as complex as desired, all ALUs work in this simple way. The objective of this experiment was to learn precisely how an ALU functions as a component of the CPU, and reproduce its behavior using two separate designs in VHSIC (Very High Speed Integrated Circuit) Hardware Descriptor Language or VHDL. Understanding how an ALU functions is one small step towards designing next generation processors, whether they are designed to be powerful implementations for super computers, or ultra low power designs for embedded systems. In this report, the focus will be on the two implementations in VHDL, as well as more detailed explanations of the various functions of the ALUs that were designed.

II. Objectives
The five key objectives of this experiment are: To design four-bit arithmetic logic units using structural and behavioral approaches. To ensure the units can perform basic arithmetic functions, such as adding, and subtracting, as well as the four basic logical operations: AND, OR, XOR, and NOT. The ALU must have a four line operation code input that determines which operation the ALU will perform. The ALU must be able to do left and right shifts. The unit needs a carry-in input, and a carry-out output.

III. Procedure
After researching how ALUs function, using a one-bit design as the foundation, the modules required for a structural design were determined to be an arithmetic module, to perform addition, subtraction, increment and decrement operations, a logic unit to perform the logical operations as described above, and a shifting unit to move all the bits to the left or right. The equations to satisfy these modules were generated by an interactive lab-wide lecture, as well as how the VHDL modules would need to be created. For the structural design, the VHDL modules were all made as one bit designs, then port mapped, that is instantiated in another VHDL module similar to a function call, or a method in other high level languages, into four bit designs. Once these four bit designs were tested and confirmed to be fully functional, a new VHDL module was created to port map all three separate units into one complete unit.

-1-

On the arithmetic module, it was noted that the carry in was always tied to the least significant bit on the operation code, so in an effort to increase efficiency, compactness, and to reduce the input pin count used, the carry in value was forced to the least significant bit, and there is no true carry-in on this design. As the operation code, or op code, is given to each unit separately, and only one operation, and thus, one unit will be active during a specific operation, all three units always receive the op codes, and the result is logically ORd together. The result of this is that the non functional units return all low signals, and the active unit returns high signals where necessary, so only the active high signals are translated through the ALU. The test bench waveform of the design can be seen in Figure 1, displaying all functional operation codes as well as the outputs that each function resulted in, with each module of code being separated by a value of 0000. The first section, commands 4h1 through 4h7, is the arithmetic module, the second section, commands 4h8 through 4hB, is the logic module, and the third section, commands 4hC and 4hE, is the shifting module.

Figure 1 - Test Bench Waveform of a Structurally Designed 4 Bit ALU The behavioral approach was much similar to that of a high level language, using conditional statements to determine which op code was given by the user, and performing the appropriate action. An if-then-else conditional structure was used, over a switch statement, due to no other reason than simplicity. While in general, switch statements are slightly more efficient then if-then-else structures, the differences are usually negligible, and in the case of switch statements, the required layout of whitespace can vary from language to language and cause significant problems.

-2-

Code generation for behavioral designs in VHDL is far simpler than the designs using Boolean expressions, and as such, is much faster to produce. As shown in Figure 2, the functionality of the ALU is almost exactly the same than that of the structural design, with a slight higher accuracy in the carry out in some situations, due to the linking of the least significant bit in the structural design.

Figure 2 Test Bench Waveform of a Behaviorally Designed 4 Bit ALU Once the coding was complete, the different implementations needed to be programmed onto the CPLD or Complex Programmable Logic Device to demonstrate that the code was completely functional. Using the Xilinx ISE software suite, in particular the software designed to transmit compiled VHDL code to the CPLD, both approaches of the ALU code was successfully demonstrated on the CPLD.

IV. Results
When compiling the VHDL code, the Xilinx ISE reports resource usage summaries on the compiled code, and as shown in figures 3 and 4, the relative efficiency can be seen. The behavioral design uses nearly twice as many macrocells, or componentized blocks of logic, as the structural design. The behavioral design also uses twelve percent more product terms, as the behavioral code must be converted into Boolean expressions, and the developer has no true control over how the compiler does that, whereas the developer has complete control over the product terms used in the structural designs. Both designs function the same way, without using registers and have the exact same inputs, so the register count, and number of pins used is identical. The function blocks used in the behavioral design has an increase of fourteen percent, due to the increase of macrocells and product terms used. The trade off in the inefficiency of the behavioral design lies entirely in its brevity, and the speed at which the code can be generated. The structural design uses nine separate VHDL files, the behavioral uses one. The number of lines of code is roughly doubled in the structural design than that of the behavioral one. Finally, the time it took to code the structural design was nearly three times than the behavioral design. -3-

Figure 3 Resource Summary of a Structurally Designed 4 Bit ALU

Figure 4 Resource Summary of a Behaviorally Designed 4 Bit ALU

V. Conclusion
The design and implementation of ALUs is far simpler than it seems at a cursory glance. Depending on the size and number of op codes available, the ALU can be simple or complex, using a reduced instruction set, or a complex one, which ever design is required to complete the objective that is at hand. The implementation of the code can emphasize efficiency or speed of coding, using a structural design for high constraint designs for such situations as embedded systems that require the strictest coding practices due to size, heat, power draw, and other factors, while behavioral designs can be used not only for rapid production of code for designs that have constraints are not so high and have largely complex operations, but also can be used to prove a design works before trying to implement it in a structural design.

-4-

VI. References General information provided by: http://www.xilinx.com/ http://en.wikipedia.org/ http://www.eda.org/ FPGA and CPLD Solutions from Xilinx, Inc. Wikipedia, the free encyclopedia The Electronic Design Automation Industry Working Groups

No code from external sources was used, nor any information from these sources used directly in this paper.

-5-