CPLD Experiment 8

Encoders & Application to a 7-Segment Display Driver

Based on Xilinx ISE Design Suit 10.1
Department of Electrical & Computer Engineering

OBJECTIVES
Examine encoders and their applications. Examine the characteristics of a decimal-to-BCD priority encoder. Design an 8-to-3 line priority encoder in schematic mode and test it on a target board. Create a macro for a 7-segment decoder with active-HIGH outputs using VHDL. Utilizing a created macro, design a circuit in schematic mode to display a decimal digit on a 7-segment display.

MATERIALS
Xilinx ISE software, student or professional edition V10.1 or higher. IBM or compatible computer with Pentium III or higher, 128 M-byte or more RAM, and 8 G-byte or larger hard drive. CoolRunner-II CPLD board by Xilinx Inc with an XC2C256 device.

DISCUSSION
As we saw in the previous experiment, a decoder identifies or detects a particular binary number or code. Encoding is the opposite process of decoding. An encoder has a number of input lines (up to 2n), only one of which is activated at any given time, and produces the n-bit output code for the input selected. For example, consider an 8-to-3 encoder. When one of its eight inputs is activated, the output will be a 3-bit binary number (code) corresponding to that input. If two or more inputs are activated at the same time, which one of the inputs should be encoded and reflected on the outputs? This is when priority is used in the encoder design. When multiple inputs are activated, priority specifies which input will get selected to produce the output code. A common application of encoders is in the keyboards of calculators and computer systems to convert key-presses to binary numbers or to codes such as BCD or ASCII.

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The 8-to-3 Line Encoder with Active-LOW Inputs The 8-to-3 (octal-to-binary) encoder accepts eight input lines and produces a unique 3-bit output code for each set of inputs. Table 9.1 below describes the function of this encoder. Note the active-low inputs, as could be obtained from a keypad with normally-open contacts to ground.

The Decimal-to-BCD Priority Encoder Figure 9.2 is the truth-table for a decimal-to-BCD priority-encoder (such as the 74147 TTL chip). It has nine active-low inputs representing decimal numbers 1 through 9. The encoder produces the inverted BCD code corresponding to which of the nine inputs is activated.

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Note the dont-cares (Xs) in the truth table. They imply that, if two inputs are activated simultaneously, only the highest data line is encoded. For example, if lines A1 and A5 are activated at the same time, A5 will be encoded producing the output 1010 (which is 0101 inverted, or BCD 5). Thats why its called a priority encoder. Moreover, the implied decimal zero condition requires no inputs since zero is encoded when all nine data lines are at HIGH. For a more detailed discussion of encoder circuits, refer to your digital textbook.

7-Segment Display A 7-segment display is composed of seven bars (the segments; either LED or LCD) that can be individually activated to emit light. Such a display can show digits from 0 to 9, as well as a few letters (A, b, C, d, E, F, H, L, P, S, U, Y), a minus sign (-) and a decimal point. For a commoncathode 7-segment LED display, the common input is connected to GND, and a HIGH on any segment-input will light up that segment. For a common- anode display, the common-input is connected to a HIGH, and a LOW on a segment- input lights the segment. Figure 9.1 (a) and (b) show how the seven segments are arranged.

A:

B:

C:

D:

E:

F:

7-Segment Decoder 7-segment decoder is not available in the symbol library of the Xilinx software, so we will design one. We will design the decoder with active-high outputs for a common- cathode display. The lit display segments for each digit from 0 to 9 are given in the following truth table:

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BCD to 7-Segment Decoder Driver (74LS47) Table

Decimal Number

Inputs
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a b c

Outputs
d e f g

0 1 2 3 4 5 6 7 8 9
Invalid Invalid Invalid Invalid Invalid Invalid

Table 9.3 Truth Table for a 7-Segment Decoder with Active-High Outputs

Note that the outputs of this decoder are all LOW for invalid (mv) BCD codes. Based on the above truth table, we can derive the Boolean equations for the outputs using Kmaps or Boolean algebra:

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PROCEDURE:
Section I. An 8-to-3 Line Encoder (74148)
1. Create a new project called ENCO8_3 in schematic mode. Add a schematic source named enco83 to this project. 2. Create a schematic diagram similar to the one below. Note that X74_148 (8-to-3 encoder with active-low inputs and active-low outputs) is retrieved from the Symbol library. I0 through I7 are the data inputs. EI (enable input) is a control input. A0, Al, and A2 are the encoded data outputs. To cascade encoders for a multi-digit display, the EO of each stage is connected to the EI of the next stage (EI of first stage is held low). GS goes low whenever one of the data inputs goes low. (IT IS EO, INSTEAD OF E0!!!!!) The 74F148 8-input priority encoder accepts data from eight active-Low inputs and provides a binary representation on the three active-Low outputs. A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line I7 having the highest priority. A High on the Enable Input (EI) will force all outputs to the inactive (High) state and allow new data to settle without producing erroneous information at the outputs. A Group Signal (GS) output and an Enable Output (EO) are provided with the three data outputs. The GS is active-Low when any input is Low: this indicates when any input is active. The EO is active-Low when all inputs are High. Using the Enable Output along with the Enable Input allows priority encoding of N input signals. Both EO and GS are active-High when the Enable Input is High. Pin assignment -Inputs of X74_148 I0 P61 I1 P42 I2 P41 I3 P40 I4 P39 I5 P35 I6 P34 I7 P33 EI P43

Pin assignment-Outputs of X74_148 A0 P6 A1 P131 A2 P88 EO P105 GS P74

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For generate program file and simulation, it does not require input Pin assignments in I/O floor map, only require assign pin number on the I/O markers instead. If you want to test on the target board, open the Floorplan and make pin assignments for your design. The example is in the below:

*Here you can see that from the upper figure, the EI is assigned one switch, while the I0 is not assigned to a switch, that is because we do not need to care about the true value of the I0 based on the truth table in figure 9.1 3. Save your schematic design. Synthesize and implement the design and then download it onto your target board.
Test the 8-to-3 line encoder and complete the function table below. Note that both the inputs and the outputs are active-low for this encoder. So, an input is activated by a LOW logic level and the outputs are inverted binary numbers.

Note: 1. LED on represents 1. 2. P61 is a push button. (Press to turn it off) 3. EI (P43) has to be on to enable the inputs.
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X-board pins lay out:

FF O N O 40 42 41 43 2-5 39
39 35 34 33

P61:I0

75

---

82 -- 7

78

Input EI' I0' I1' I2' I3' I4' I5' I6' I7' H L L L L L L L L L X H X X X X X X X L X H X X X X X X L H X H X X X X X L H H X H X X X X L H H H X H X X X L H H H H X H X X L H H H H H X H X L H H H H H H X H L H H H H H H H

35

34

33

43

40

Note: 1. LED on represents 1. 2. P61 is a push button. ( Press off) 3. EI (P43) has to be on to enable the inputs. Table 9.4
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96 --1 00 3 14 42 1 0 14 39 1 10 2-1 04

Output A2' A1' A0' EO (GS)'

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4. Based on what you observed from the completed Table 9.4, how does EI function? Explain how the active-L outputs form an octal number. Comment on why the EO and GS outputs behave as they do.

Checked by_______________________ Date_______________________

Section II. Creating a Macro for a 7-Segment Decoder

In this section of the experiment, we will design a 7-segment decoder with active-high outputs in HDL mode. We will save the design as a macro, and use it in Section III and in later experiments. 1. Create a new project called deco_7seg in HDL mode. Add new source, deco7g as VHDL module. 2. In the Define VHDL Source window, type four inputs: D3, D2, Dl, and D0 and seven outputs: a, b, c, d, e, f, and g as shown in Figure 9.4. Click on Next and then Finish.

Figure 9.4 Define VHDL Source window for deco7g.

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3. In the deco7g. vhd workspace, add the seven statements representing the seven Boolean equations (listed in the Discussion section of this lab experiment) between begin and end Behavioral. Below is the VHDL code for the 7- segment decoder. Check the syntax by clicking the + sign next to Synthesis and then Check Syntax. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity deco7g is Port ( D3 : in STD_LOGIC; D2 : in STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC); end deco7g; architecture Behavioral of deco7g is begin a <=(not D3 and D1) or (not D2 and not D1 and not D0) or (D3 and not D2 and not D1) or (not D3 and D2 and D0); b <=(not D3 and not D2) or (not D2 and not D1) or (not D3 and not D1 and not D0) or (not D3 and D1 and D0); c <=(not D3 and D2) or (not D2 and not D1) or (not D3 and D0); d <=(not D2 and not D1 and not D0) or (not D3 and not D2 and D1) or (not D3 and D1 and not D0) or (not D3 and D2 and not D1 and D0); e <=(not D2 and not D1 and not D0) or (not D3 and D1 and not D0); f <=(not D2 and not D1 and not D0) or (not D3 and D2 and not D1) or (not D3 and D2 and not D0) or (D3 and not D2 and not D1); g <=(not D3 and not D2 and D1) or (not D3 and D2 and not D1) or (D3 and not D2 and not D1) or (not D3 and D1 and not D0); end Behavioral;

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4. Use the simulator to test the function of the deco7g.vhd, your result should look like this:

Checked by_______________________ Date_______________________

Section III. Decimal Numbers on a 7-Segment Display

In this section of the experiment, we will build a circuit that takes a decimal input and encodes it as a BCD, which is then decoded to drive a 7-segment display. Download the dec_to_bcd.jed file on the target board and demonstrate. 1) Create a new project named dec2bcd. Add a new source file dec_to_bcd in schematic mode. 2) Add the VHDL file deco 7g.vhd from project deco 7seg that you created in section 1, Click project->Add source. High ligh the file called deco7g.vhd you created before and click ok.

3) Now you need to create the symbol for the deco7g.vhd. Select it and find the design utilities under the processes window, double click Create Schematic Symbol. After this the new symbol is created and added to the library.

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4) Open your Xilinx ECS[dec_to_bcd.sch] window and draw the schematic diagram in the workspace as shown below. Note that inverters are used since the X74_147 decimal-to-BCD encoder has active-low outputs and our deco7g macro has active-high inputs.

Pin assignment -Inputs of X74_147 I1 P61 I2 P43 I3 P42 I4 P41 I5 P40 I6 P39 I7 P35 I8 P34 I9 P33

Pin assignment-Outputs of deco7g a P5 b P4 c P3 d P2 e P143 f P142 g P140

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5) Use the simulator to test the result. Assign Pin numbers on the schematics. It does not require to assign the pin numbers on the Floor Plan I/O. 6) Implement the design in Processes window. Generate the dec_to_bcd.jed and download to the target board. 7) What does the 7-segment show when no input is activated? Try to simulate all the digits 0 to 9 with different combinations.

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8) Describe the function of this circuit in your own words.

Checked by_____________________ Date_____________________

QUESTIONS:
1. Priority encoders are much more common than non-priority encoders. What do you think the reasons are for that?

2. Which bit has the highest priority? I0 or I9? (Why is there no EO input in the decimal-toBCD encoder?

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3. If a common-anode 7-segment is used, what modifications must you make on the project design in Section III? If you have more than one, list them all.

4. Name two applications for encoders.

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