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The Surface/Bulk Micromachining (SBM) Process: A New Method for Fabricating Released MEMS in Single Crystal Silicon
Sangwoo Lee, Sangjun Park, and Dong-il (Dan) Cho, Member, IEEE
AbstractThis paper presents the surface/bulk micromachining (SBM) process to allow fabricating released microelectromechanical systems using bulk silicon. The process starts with a (111)-oriented silicon wafer. The structural patterns are dened using the reactive ion etching technique used in surface micromachining. Then the patterns, as well as sidewalls, are passivated with an oxide lm, and bare silicon is exposed at desired areas. The exposed bare silicon is further reactive ion etched, which denes sacricial gap dimensions. The nal release is accomplished by undercutting the exposed bulk silicon sidewalls in aqueous alkaline etchants. Because {111} planes are used as etch stops, very clean structural surfaces can be obtained. Using the SBM process, 5-, 10-, and 100-m-thick arbitrarily-shaped single crystal silicon structures, including comb-drive resonators, at 5-, 30-, and 100m sacricial gaps, respectively, are fabricated. An electrostatic actuation method using p-n junction isolation is also developed in this paper, and it is applied to actuate comb-drive resonators. The leakage current and junction capacitance of the reversedbiased p-n junction diodes are also found to be sufciently small for sensor applications. The developed SBM process is a plausible alternative to the existing micromachining methods in fabricating microsensors and microactuators, with the advantage of using single crystal silicon. [430] Index Terms Aqueous alkaline etching, deep silicon reactive ion etching, p-n junction isolation, surface/bulk micromachining (SBM) process, (111)-oriented silicon.

I. INTRODUCTION ULK and surface micromachining technologies have been widely used to fabricate silicon microelectromechanical systems (MEMS). Bulk micromachining utilizes the etch selectivity between {111} planes and {100} and/or {110} planes in aqueous alkaline etchants to fabricate structures [1]. Silicon wafers with (100) and (110) orientations have been used in bulk micromachining. Using (100) silicon, simple structures such as diaphragms, V-grooves, and nozzles, as well as more complicated structures such as corner cubes and rectangular masses, can be fabricated [1][3]. On a (110) silicon wafer, there are four {111} planes that intersect the wafer surface vertically. Thus, vertical microstructures can be fabricated [4], [5]. However, in either (100) or (110) silicon, severe geometric
Manuscript received March 11, 1999; revised June 12, 1999. This research was supported by the Ministry of Science and Technology and the Ministry of Industry and Energy under the Micromachine Technology Development Program. Subject Editor, N. de Rooij. The authors are with the School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea. Publisher Item Identier S 1057-7157(99)08240-2.

limitations are imposed by the crystallographic constraints, and complicated structures are difcult to fabricate. In surface micromachining, the structural shape is dened by reactive ion etching (RIE), which allows fabricating arbitrary patterns. The most common structural material used in surface micromachining is polysilicon deposited by low-pressure chemical vapor deposition [6], [7]. However, depositing a 2m-thick lm takes several hours or more. Moreover, the material properties of amorphous silicon and polysilicon vary signicantly with deposition conditions and postdeposition processes [8]. Thus, accurately controlling the residual stress, stress gradient, and Youngs modulus of polysilicon is difcult. In addition, it is very difcult to grow and control the properties of thick polysilicon lms. To solve these limitations, there have been many attempts to develop a surface-micromachining-like process using single crystal silicon. There are several well-known methods for fabricating single crystal silicon microstructures. They include single crystal reactive etching and metallization (SCREAM) [9], silicon micromachining by plasma etching (SIMPLE) [10], black silicon method [11], merged epitaxial lateral overgrowth (MELO) [12], silicon-on-insulator (SOI) wafer process [13], dissolved wafer process [14], and porous silicon method [15]. Compared to the conventional bulk micromachining method, these techniques allow the fabrication of released, arbitraryshaped microstructures in single crystal silicon. However, each process has its own limitations. In the SCREAM process, the width of released structures cannot be large, and the structure undersurfaces are unevenly etched during the isotropic release etch using a SF -based chemistry. In the SIMPLE process, a high-concentration n-type buried layer is needed, and the limitation on the structural width is similar to that of the SCREAM process. In the black silicon method, a buried oxide layer is required. In the MELO process, the structural layer is laterally grown epitaxial silicon on top of an oxide or nitride lm. Therefore, fabricating a released structure with large area is difcult. In the porous silicon method, lightly doped n-type silicon is used as a structural material and p-type silicon as a sacricial material. Although there are various approaches in preparing structural and sacricial materials, it is difcult to prevent unwanted areas from becoming porous silicon. This results in underetching of anchoring areas during sacricial etching. In the SOI wafer process, complicated structures can be fabricated, but the thickness of oxide sacricial layers is limited. In the dissolved wafer process, high-concentration

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(a)

(b)

(c) Fig. 1. Crystallography of (111)-oriented silicon. (a) h111i directions. (b) Six normal h110i directions. (c) Six oblique h110i directions.

boron doping as well as topside bonding with another wafer is needed. The backside etch process can also take a long time. This paper presents a new method for micromachining released structures with single crystal silicon. The developed surface/bulk micromachining (SBM) process utilizes (111) silicon wafers. First, a (111) silicon wafer is reactive ion etched leaving the structural patterns to be released later, and the bulk silicon under the patterns is etched in an aqueous alkaline etchant to release the patterns. In the developed technology, the thickness of the structural layer as well as the thickness of the sacricial gap are dened by deep silicon RIE. The release of structure is accomplished by aqueous alkaline etching, utilizing the slow etching {111} planes as the etch stop. This results in very smooth and at bottom surfaces. The required release etch time in a KOH solution, a commonly used alkaline etchant, is comparable to that of etching the sacricial oxide in HF. The ensuing sections present the complete fabrication method as well as examples of SBM fabricated complex structures, including mesa-island anchored structures and comb-drive resonators. For electrostatic actuation of released microstructures, an electrical isolation method with reverse-biased p-n junction diodes is also developed in this paper. The breakdown voltage

of p-n junction diodes, which determines the maximum voltage difference between electrodes, is sufciently high for most MEMS. An example of electrostatically actuating an SBMfabricated comb-drive resonator is shown. The depletion layer at the p-n junction is also found to be sufciently large. This results in a very low paracitic capacitance, which is advantageous in sensor applications. Micromachining with (111) silicon has been attempted previously [16]. However, the structures must be crystallographically aligned to three special directions, and complex structures cannot be fabricated. In addition, the process in [16] requires two photoresist exposure steps that limit the structural thickness. The electrostatic actuation method using junction isolation of single crystal silicon microstructure is reported rst in this paper. II. PRINCIPLES OF SBM PROCESS AND (111) SILICON CRYSTALLOGRAPHY To understand the salient features of the SBM process, consider the six {111} planes on a (111)-oriented silicon wafer, as shown in Fig. 1(a). These {111} planes represent six of eight {111} planes, the others being the top and bottom planes. These six {111} planes are tilted at 19.47 from

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(b)

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Fig. 2. Detailed process ow. (a) Silicon etch using RIE. (b) Passivation nitride and oxide deposition. (c) Oxide and nitride etch. (d) Silicon wet etch in aqueous alkaline etchant.

the vertical as indicated. The eight {111} planes are the slow etching planes in an alkaline etchant, and they are used as the etch stops in fabricating released structures. The fast etching planes of (111) silicon in alkaline etchants are {110} planes. There are total of 12 {110} planes. Six are found by rotating the equilateral triangles in Fig. 1(a) by 30 in either a clockwise or counterclockwise direction, as shown in Fig. 1(b). These {110} planes form 90 angles to the (111) plane. Six more {110} planes are aligned to the (111) plane, as shown in Fig. 1(c). These {110} planes are tilted by 54.7 from the vertical. The six {110} planes that intersect the (111) plane vertically, i.e., those identied in Fig. 1(b), are the fastest etching planes. The other six {110} planes as well as all the {100} planes etch slower due to the various intersecting {111} planes that must etch with them. In KOH, the etch selectivity between the fast etching vertical {110} planes and the slow etching {111} planes is on the order of 100 [17]. The fabrication steps of the SBM process are shown in Fig. 2. A plasma-enhanced chemical vapor deposition (PECVD) oxide layer is deposited and patterned as shown in Fig. 2(a). Next, a vertical silicon RIE process is used to dene the structural patterns. The rst oxide layer should be thick enough to withstand the vertical silicon RIE steps for structure patterning and sacricial-gap denition, as well as the nal aqueous alkaline etching. Then, a second PECVD oxide lm is deposited, as shown in Fig. 2(b). The lm is used to protect the structure sidewalls in alkaline etching. The second oxide lm is then anisotropically etched using RIE to expose bare silicon at the bottom of the etched trenches, as shown in Fig. 2(c). This step does not require a photoresist/lithography step and must not etch the pattern sidewalls. Then, the silicon wafer is vertically etched again using deep silicon RIE. The etch depth is the same as the desired spacing between the structural layer and the bottom surface. This is the same concept as the oxide sacricial layer in surface micromachining. Finally, the wafer is dipped into an aqueous alkaline solution such as KOH, ethylene diamine pyrocatechol, or tetramethyl ammonium hydrox-

ides to perform the sacricial etch. In this nal step, the lower parts of the sidewalls without oxide passivation will be etched in the lateral direction. This wet etch will terminate when etch fronts meet {111} planes. This results in released patterns, as shown in Fig. 2(d). Note that nitrides lms can be used together with the PECVD oxide lms, if the required release etch time is long, or if KOH is used as the sacricial etchant. Fig. 3 shows some examples of SBM-processed microstructures. Fig. 3(a) and (b) shows released letters MEMS and a released beam-supported round plate. Because the structures are patterned by RIE, the patterns are sharply dened, and arbitrary shapes with arbitrary sacricial gaps can be fabricated. The examples show a 10- m structural thickness with a 30- m sacricial gap. The structures are very smooth since they are made of single crystal silicon. The bottom surface is also smooth, which is the (111) plane. An example of the plane, is shown structural bottom surface, which is the in Fig. 3(c). The bottom surface is also smooth. The slight scaling phenomenon is due to a slight wafer misorientation and the nite etch selectivity. Fig. 3(d) shows a released 100- mthick round plate with a 100- m sacricial gap. Fig. 3(b)(d) shows that large plates can be cleanly released without requiring additional etch holes. One of the advantages of the SBM process is that sacricial gaps can be made very large. This alleviates stiction problems and reduces air damping. III. MORE
ON THE

SBM PROCESS

A. Undercut Mechanism of (111) Silicon in Aqueous Alkaline Etchants Since aqueous alkaline etching is used in the nal release step, understanding the directions of etch front propagation in alkaline etchants at convex and concave corners is important. The prediction of the etch front is based on the two conditions stated in Batterman [18]. On a concave surface, etch fronts will develop at the plane with a relatively minimum etch rate versus orientation, while on a convex surface the converse will hold. Aqueous alkaline etching of (111) silicon has not been studied in detail previously, we start with the fact that in most alkaline etchants, etch rate is slowest in the 111 directions. Therefore, on a concave surface, the six tilted {111} planes should develop during wet etch in the SBM process. The etching process will terminate where {111} planes intersect. In fact, this is evident in Fig. 3(b). On a convex surface, the etching process will continue in the direction of etch front propagation until the pattern is completely released. However, the fastest etch direction is generally dependent on the concentration, temperature, and additives of etchants, and it is not practical to determine the exact direction of etch front propagation for all etch conditions. However, in the SBM process, the direction of etch propagation must lie on the (111) plane. There are many possible directions, but generally, the six 110 directions that lie on the (111) plane, shown in Fig. 1(b), have to be the fastest etching directions based on the crystallography. The directions of etch propagation should be then those six 110 directions on a convex corner.

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(a)

(b)

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Fig. 3. Examples of fabricated structures. (a) Released letters MEMS (structural thickness = 10 m, sacricial gap = 30 m). (b) Released beam-supported round plate (structural thickness = 10 m, sacricial gap = 30 m). (c) Backside of the round plate. (d) Released beam-supported thick round plate (structural thickness = 100 m, sacricial gap = 100 m).

(a)

(b)

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Fig. 4. Convex corner underetch mechanism of (111) silicon. (a) This gure shows the convex corner underetch mechanism. The outer hexagon is the patterned oxide mask and aligned to the h111i directions. The inner hexagon is a silicon mesa developed by the underetch mechanism; the sides are aligned to the h110i directions. (b) The outer hexagon is aligned to the h110i directions. The inner hexagon is developed by the underetch mechanism; the sides are aligned to the h110i directions. (c) The sides of outer hexagon are rotated from the h110i directions by 15 . The inner hexagon is developed by the underetch mechanism; the sides are aligned to the h110i directions. (d) Cross section of (a)(c) before aqueous alkaline etch.

solution. Fig. 4 shows the optical micrographs of fabricated test structures. To inspect the etch propagation, a 1.5- mthick PECVD oxide mask is used. Fig. 4 shows three identical convex test structures with different crystallographic orientations etched for 17 min in a 30wt%, 90 C KOH solution. In Fig. 4(a), the sides of the hexagonal pattern are aligned to lie on the intersection of six tilted {111} planes and the (111) plane. In Fig. 4(b) and (c), the hexagonal patterns are rotated by 30 and 45 from the 111 directions, respectively. Clearly, the results show that the etch front planes are the six {110} planes that are vertical to the wafer as identied in Fig. 1(b). The calculated etch rate in 110 directions is about 170 m/h. This etch rate is slightly larger than that of underetching an oxide sacricial layer in concentrated HF. The scaling phenomenon shown in the gures is due to a slight wafer misorientation. However, the roughness of the scales is very small, as shown earlier in Fig. 3(d). In the SBM process, the shape of released structure is dened by RIE. Therefore, arbitrary shape can be dened. However, if etch fronts do not intersect under the structure to be released, the release process cannot be completed. When the structures to be released have only concave corners, care must be taken so that the etch front planes intersect under the structures to be released. B. Fabrication of Mesa-Island Anchors

To verify the assumptions, test structures with convex corners are fabricated and wet etched in a 30wt%, 90 C KOH

To fabricate folded-type comb-drive resonators, mesa islands are needed for the anchor points. Since mesa islands

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Fig. 6. SEM micrography of a compensation pattern. (c) (d)

Fig. 5. Examples of compensation patterns etched in a 90  C, 30 wt% KOH solutions. (a) Before etch. (b) After 37 min.

have convex corners, it will be etched during the alkaline sacricial etch. This will result in unwanted changes in the support boundary conditions. Therefore, to fabricate mesaisland supported released beams, a suitable compensation pattern is required. Generally, a small anchor size and small compensation patterns are desirable. These will be functions of the etch time as well as crystallographic orientation of patterns. Consider equilateral triangle mesa patterns for a simple calculation to determine compensation patterns. When the three sides of a triangle are aligned to 110 directions, side etching will take place at an equal rate on all three sides. When the sides are aligned to 111 directions, side etching occurs only at the three vertices. This implies that for the fabrication of mesa islands, the combined pattern of triangles aligned to 111 directions will result in the smallest patterns. Fig. 5 shows examples of compensation pattern to fabricate mesa islands. In these examples, the areas to be anchored to the substrate are designed with a solid hexagon or triangle. The patterns that protect the anchoring area from being underetched are designed with diapered triangles with void inner areas. All sides of compensation patterns are aligned to the 111 directions. Since the (111) silicon is of threefold symmetry, the sides of triangular compensation patterns etch with the same speed from all convex corners. Fig. 5(b) is the results after 37 min in a 30wt%, 90 C KOH solution. If the time to release one triangular compensation pattern is known in a specic etching condition, the number of triangular compensation patterns needed for protecting an anchor area can be easily calculated. Fig. 6 shows a mesa island fabricated with a triangular compensation pattern. It clearly shows that a mesaisland support with true boundary conditions can be fabricated. IV. JUNCTION ISOLATION FOR ELECTROSTATIC ACTUATION Electrostatic actuation is the most widely used method for actuating microstructures. The actuation voltages can be in excess of several tens of volts, and a proper electric isolation of electrodes is required. In surface micromachining, oxide

or nitride lms are used to electrically isolate electrodes. However, in the SBM process, microstructures are made from bulk silicon, and the use of dielectric lms is difcult. In the SCREAM process, electrical isolation is accomplished after the release step, using a PECVD oxide intermediate layer and a sputtered metal layer [9]. The method can be exactly duplicated for the SBM process. However, this approach can have limitations, since the isolation and metallization steps are performed after releasing the structures. In addition, sidewalls cannot be metallized easily. In this paper, a p-n junction isolation method using reversebiased diodes is developed. In the developed method, isolation is accomplished in two steps. The rst step is done at the very beginning of the process by forming a p-n junction. The p-n junction is formed by diffusion doping of an n-type impurity into a p-type wafer, and vice versa. The diffusion-doped area can be isolated from the substrate using a reverse-biased junction. The second isolation step is done during the main SBM process by etching away the parts of doped areas. By etching deeper than the junction depth, the isolation between electrodes is accomplished. One drawback of the developed isolation method is that it is difcult to dope bulk silicon to a depth larger than several micrometers. The use of epitaxially grown low-resistivity (111) silicon is an alternative if a junction depth of more than several micrometers is required. This junction isolation method is applied to fabricate a comb-drive resonator. The process steps for achieving electrical isolation are as follows. With the starting material of (111) silicon wafers, a 1.6- m-thick oxide lm is thermally grown. Then, the oxide lm is patterned to expose bare silicon for doping. After patterning of the masking oxide, the wafer is diffusion-doped. The doped area covers the region used as electrodes and the region used as a main body of resonator. Both n- and n-type wafers are used for fabrication. For the n-type wafer, a solid boron source is used for doping. The predeposition process is performed at atmospheric pressure with 1.5 sL/min (standard liter per minute) of N for 12 h. Before the predeposition step, the solid boron source is activated for 30 min in the O environment. The drive-in process is performed with 1.5 slpm of O at atmospheric pressure for 1 h, with the boron source removed.

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(a) (a)

(b) (b) Fig. 7. Fabricated comb-drive resonator for electrostatic actuation. (a) Doubly-clamped comb-drive resonator. (b) Close-up view of (a). Fig. 8. Doping proles and resistivity of doped region. (a) Boron doping. (b) Phosphorus doping.

For the p-type wafer, a liquid POCl source is used for doping. The predeposition of phosphorus-containing oxide is performed at atmospheric pressure with 2 slpm of N , 0.4 slpm of POCl -containing N , and 0.2 slpm of O for 1 h. The drivein process is performed with 2 slpm of N at the atmospheric pressure for 16 h. The diffusion temperature is 1000 C in all cases. After the removal of the masking oxide, the main SBM process steps are used to complete fabrication. The isolation of electrodes is accomplished by the silicon RIE steps in dening the structure patterns and sacricial gaps. Fig. 7(a) shows the four electrodes which are located at each of the four sides. Fig. 8 shows the doping proles of n- and p-type wafers. The doping concentration and resistivity is plotted as a function of the diffusion depth. The junction depths of n- and p-type wafers are 6 and 5 m, respectively. For a proper electrical isolation, the junction depth should be less than the sum of structural height and sacricial gap. Fig. 9 shows the IV traces of the reverse-biased junction diodes. For the case of n-type wafer, measurements are done at ve different locations. The breakdown voltage ranges from 150 to 180 V. For the case of p-type wafer, measurements are done at four different locations, and the breakdown voltage is about 150 V for all cases. These breakdown voltages are sufciently large for electrostatically actuating almost all MEMS devices.

In capacitive sensing applications, the leakage current through the junction diodes can become a problem. The insets of Fig. 9 shows the reverse-bias leakage current as a function of reverse-bias voltage in the range of 030 V. The leakage current is about 4.3 A at 30 V and about 560 nA at 10 V, for the case of n-type wafer. In this case, capacitance sensing circuits with a low-impedance input node, such as a transresistance amplier and charge amplier, cannot be implemented because of the large leakage current. However, even in such a case, a buffer circuit that has a high-impedance input node can be implemented. For the case of p-type wafer, the leakage current is only about 44 nA at 30 V and 20 nA at 10 V. The leakage current of tens of nanometers would not cause a problem in circuits. Thus, p-type wafer process would be preferred in sensor applications.

V. ELECTROSTATIC ACTUATION OF SBM-FABRICATED RESONATORS Comb-drive resonators [19] represent the most widely used conguration for microsensors and microactuators. After doping (111) wafers for junction isolation, the SBM process is applied to fabricate comb-drive resonators in both n- and ptype silicon. Fig. 7 shows comb-drive resonators fabricated using a phosphorus-doped p-type wafer. In Fig. 7, the small

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(a)

Fig. 10. Experimental setup for electrostatic actuation. (The gure corresponds to the n-type, boron-doped wafer. In the case of a p-type, phosphorus-doped wafer, the polarity of V2 must be reversed.)

(b) Fig. 9. I-V curves of fabricated junction diodes. (a) Boron-doped junction diode. (b) Phosphorus-doped junction diode. Fig. 11. Calculated junction capacitance and depletion width.

steps around the electrodes are due to the thermal oxide grown at the doping step. Fig. 10 shows experimental setup for electrostatic actuation. For the n-type wafer, the tested comb-drive resonator has a spring length of 380 m and a structural thickness of 5 m. For the p-type wafer, the tested comb-drive resonator has a spring length of 228 m and a structural thickness of 10 m. For the n-type wafer, a 20-V peak-to-peak sinusoidal voltage with a 10-V offset was applied to , with the positive output terminal connected to the xed electrode. A 30-V dc voltage with the positive output terminal connected was applied to to the substrate. The actuator resonated at 36 kHz with a comb amplitude of approximately 5 m in atmospheric pressure. For the p-type wafer, a 140-V peak-to-peak sinusoidal voltage with a 70-V offset was applied to , with the positive output terminal connected to the xed electrode. A 30-V dc voltage with the negative output terminal connected was applied to to the substrate. The actuator resonated at 50 kHz with a comb amplitude of approximately 10 m in atmospheric pressure. The different voltage requirements are due to the fact that the resonator sizes are different and the fact that the doped depth is less than the structural height in the p-type. Note that if the experiments are performed in a reduced pressure, the displacement would be much larger. The comb displacement factor. Also, the actuation voltage is proportional to the seems large, but this can be reduced by simply increasing the

number of combs. Note that by varying , this conguration can be used for a simultaneous vertical actuation. For high performance sensor applications, one could be concerned with the junction capacitance and leakage current of the junction isolation method. The junction capacitance between the electrodes and the substrate can be interpreted as a parasitic capacitance between the anchoring area and the substrate. For the calculation of junction capacitance as a function of reverse-bias voltage, the depletion width should be known. The depletion width is calculated assuming a breakdown voltage of 165 V. The results can be applied to both n- and p-type wafers. In the calculation, since diffusion doping is used, the doping concentration can be approximated as a linear function of distance [20]. The results are plotted in Fig. 11. As the reverse-bias voltage increases, the depletion width increases, and the junction capacitance decreases. The calculated junction capacitance is smaller than that of the conventional dielectric isolation. For a comparison, let us assume that a nitride lm with the thickness of 6000 A is used between a highly phosphorus-doped silicon wafer and a highly phosphorus-doped polysilicon electrode. Assuming a pad size of 100 m by 100 m, the calculated capacitance of the nitride isolation is 1.107 pF. When a 30 V of reverse-bias voltage is applied to the junction isolation case, the junction capacitance is only 0.116 pF. With no reverse-bias, which has the maximum value, the junction capacitance is 0.4495 pF.

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VI. SUMMARY

AND

CONCLUSIONS

In this paper, the SBM process is developed, which allows surface micromachining with bulk silicon. The SBM process denes structural patterns using RIE on a (111) silicon wafer and releases the patterned structures using aqueous alkaline etch. The SBM process can fabricate sharply dened, arbitrarily thick, and arbitrarily shaped released microstructures in single crystal silicon with arbitrarily large sacricial gaps. Examples presented include sharply dened 5-, 10-, and 100- m-thick structures with 5-, 30-, and 100- m sacricial gaps, respectively. Diapered triangle compensation patterns were also developed and applied to fabricate mesa-island supported structures. Using phosphorus and boron diffusion doping on p- and n-type wafers, respectively, a p-n junction isolation method was developed to actuate SBM-processed resonators. The breakdown voltage of reverse-biased p-n junction diodes are sufciently large in both p- and n-type wafers for electrostatic actuation. The leakage current and capacitance of reverse-biased junctions were also studied. The leakage current was measured to be on the order of A for the n-type wafer and lower than 40 nA for the p-type wafer for voltage up to 30 V. Thus, p-type wafers can be used in capacitive sensing devices. The SBM process can duplicate almost all surface micromachined microsensors and microactuators that use a single layer of structural polysilicon. For most applications, however, the developed SBM process can offer an advantage of more predictable and stable material properties of single crystal silicon. Furthermore, the SBM process can fabricate high-aspect ratio microstructures, which is difcult with the polysilicon technology. The SBM process also allows large sacricial gaps, which is benecial for preventing stiction and reducing air damping. We believe that the advantages of bulk properties, high-aspect ratio structures, and large sacricial gaps of the SBM process are suitable for high performance sensors and large force actuators. REFERENCES
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Sangjun Park received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1997 and 1999, respectively. He is currently working toward the Ph.D. degree at the School of Electrical Engineering, Seoul National University. His research interests include design, optimization, and fabrication of microactuators and microinertial sensors.

Dong-il (Dan) Cho (M88) received the B.S.M.E. degree from CarnegieMellon University, Pittsburgh, PA, in 1980, and the S.M. and Ph.D. degrees from Massachusetts Institute of Technology, Cambridge, in 1984 and 1987, respectively. From 1987 to 1993, he was Assistant Professor in the Mechanical and Aerospace Engineering Department, Princeton University, Princeton, NJ. In 1993, he joined the Department of Control and Instrumentation Engineering, Seoul National University, Seoul, Korea, where is currently Associate Professor in the School of Electrical Engineering. His research interests include variable structure control, mechatronics, ITS, and MEMS. From 1992 to 1997, he was an Associate Editor for the IOP Journal of Micromechanics and Microengineering. He also served as an Acting Associate Editor for the ASME Transactions Journal of Dynamic Systems, Measurement and Control in 1993. Dr. Cho was an Associate Editor for the IEEE/ASME JOURNAL OF MICROELECTROMECHANICAL SYSTEMS from 1992 to 1997.