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Low Power Consumption, suitable for battery operated systems Interfaces Supply Voltage range from 1.6 to 3.6V High Voltage Generator Supply Voltage range from 2.4 to 3.6V Display Supply Voltage range from 3 to 13.2V (Tamb = 25C)
68 x 96 bits Display Data RAM 33,49, 65 and 68 Lines Mode Row by Row Scrolling Interfaces 3-lines Serial Interface (read and write) I2C (read and write) 4-Line Serial (read and write) Partial Display Mode (33,25,17,9 Lines Mode) Fully Integrated Oscillator requires no external components CMOS Compatible Inputs Programmable ID-Number Programmable Bias Ratio Programmable Columns Organization Fully Integrated Configurable LCD bias voltage generator with: Selectable multiplication factor (3x, 4X and 5X) Effective sensing for High Precision Output Eight selectable temperature compensation coefficients Designed for chip-on-glass (COG) applications
Description
The STE2007 is a low power LCD driver, capable to drive 96 columns and up to 68 lines, designed for monochrome displays. The STE2007 includes fully integrated bias voltage generator (up to 5x multiplication factor), and internal oscillator, thus reducing to minimum the number of external components required and the current consumption. The STE2007 features the three standard serial interfaces (3 and 4 lines serial, I2C interface).
Order codes
Type Bumped Dice on Waffle Pack Ordering Number STE2007DIE2
November 2005
Rev 1 1/62
www.st.com
62
STE2007
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Driver Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 3-lines 9 bit Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 4.1.2 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
4-Line SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1 4.2.2 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1 4.3.2 4.3.3 4.3.4 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Starting the Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4
Reading Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.1 IIdentification byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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5.4
Instruction Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1 6.2 6.3 Initialization (Power ON Sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Display Data Writing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 8
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STE2007 8.17 8.18 8.19 8.20 8.21 8.22 8.23 Bias Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Charge Pump Multiplication Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Icon Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 N- Line Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Number of Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9 10
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STE2007
1 Introduction
Introduction
In this document is specified LCD driver for Black&White full graphic displays with a resolution of 96x68, 96x65, 96x49, and 96x33 (ColumnsXRows). Abbreviations LCD COG MCU Liquid Crystal Display Chip On Glass technology Micro Controller Unit
DDRAM Display Data Random Access Memory MSB LSB T.B.D. Most Significant Bit Least Significant Bit To Be Defined
Table 1.
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1 Introduction
STE2007
Figure 1.
R66
STE2007
BUMP SIDE
(0,0) Y
X
! /
! ! 45m 72m
R67 R65
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STE2007
2
2.1
0 I I 0 I I
Serial Data Output Serial Data Input /I2C Interface Data Input Serial Clock Input/I2C Interface Clock
Must be left floating I2C Bus Data Out I2C Slave Address I2C Slave Address 4 Line SPI Data/Command Selector when I2C Interface is not is use Cannot be left floating Cannot be left floating Must be connected to VSSAUX at Module Level when 4-Line SPI is not in USE
!D/C
2.2
Table 4. PIN
Type
High Voltage High Voltage
Description
Booster Output Booster Sense Input
Note
Cext = 0.1-1F Connected to Vss Must be connected to Vlcd at module level
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STE2007
High Voltage Pins (continued)
Table 4. PIN
Signal
COM0 to COM67 COMS SEG0 to SEG95
Type
High Voltage High Voltage High Voltage
Description
LCD Row Driver Output LCD Row Driver Output LCD Column Driver Output
Note
Unused lines must be left floating Unused lines must be left floating Unused lines must be left floating
2.3
Configuration Pins
Table 5. PIN Configuration Pin Description Signal
OSCIN
Type
I
Config
VSS/VSSAUX VDDI
Description
Internal Oscillator Stopped Internal Oscillator Active
Note
SEL1 VSS/VSSAUX SEL0 -SEL1 I VSS/VSSAUX VDD1 VDD1 VSS/VSSAUX IDA I VDDI VSS/VSSAUX IDB I VDDI
Interface I2C SPI 4-Lines 8 bit Serial 3-Lines 9 bit Not Used
2.4
Test Pins
Table 6. PIN Test Pin Description Signal
T2 T1 T0 T3
Type
I I I O
Description
Test Input. Enable Test Mode. Test Input. Enable Test Mode. Test Input. Test Output.
Note
Must Be connected to VSS in Normal Working Mode Must Be connected to VSS in Normal Working Mode Must Be connected to VSS in Normal Working Mode Must Be OPEN in Normal Working Mode
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STE2007
Table 6. PIN Test Pin Description (continued) Signal
T4 T5 T6 VREF_B UFF
Type
O O O O Test Output. Test Output. Test Output.
Description
Note
Must Be OPEN in Normal Working Mode Must Be OPEN in Normal Working Mode Must Be OPEN in Normal Working Mode Must be left floating
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STE2007
3
3.1
2000
Note:
(*) ESD tests have been performed with VSS, VSS_LCD and VSS_CP shorted together
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STE2007
3.2
Table 8.
DC Characteristics
DC characteristics
Parameter Power Supply Voltage Power Supply Voltage(Logic) Booster Output Test Condition Operating Voltage I/O supply Voltage Min. 2.4 1.6 Typ. Max. 3.6 3.6 13.5 13.5 VLCD=10V; VDD=2.6V; Tamb = 25C; No display Load; fSCLK=0Hz Power Saver Mode ON (Interfaces quiescent) Unit V V V V
1 6 120
3 20 250
A A A
I(VDDI)
Power Saver Mode OFF (Interfaces quiescent) Write Mode VLCD=10V;Booster= 5X; fSCLK=0Hz; VDD=2.4V Refresh Rate=75Hz; no display load;Tamb = 25C
90
180
Logic Inputs VIH VIL IIH IlL Logic High level input voltage Logic Low level input voltage Logic High level input current Logic Low level input current 0.7VDD
I
VDDI 0.3VDD
I
V V A A
Vss
1 -1
Logic Outputs VOH VOL Logic High level output voltage lOUT = -500A; VDDI=1.6V Logic Low level output voltage lOUT = 500A; VDDI=1.6V 0.8VDD
I
VDDI 0.2VDDl
V V
Vss
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STE2007
3.3
Table 9.
AC Characteristics
AC Operation - Internal Oscillator
Parameter Test Condition VDDI= 1.6; VDD= 2.9V Rafresh Rate = 75Hz Tamb = -20C to +70C Min. Typ. Max. Unit
Symbol
FFRAME
68
75
82
Hz
3.4
Table 10.
Chip Select
SDAIN
SDAOUT
SCLK
tshw tslw
Data setup time Data hold time Access Time Output Disable Time Serial clock cycle Serial clock H pulse width Serial clock L pulse width
Note: 1 The input signal rise and fall times must be within 10ns. 2 Every timing is specified on the basis of 30% and 70% of VDDI. 3 Tamb = -40 to 85C, unless otherwise specified.
Figure 2. MCU TxData timing
tchw tcss tcsh tchw
!CS
tscyc tslw
SCLK
tf tsds tr tsdh
tshw
SDA/MCU TxData
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STE2007
Table 11.
Signal Inputs
3.4.1
Table 12.
Data hold time Access time Output disable time Data setup time !CS pulse width high
T1 T2 T3 T4 T5
Note 1
Note: 1 Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is Always 3-8ns before SCLK pulse falling edge 2 The input signal rise and fall times must be within 10ns. 3 Every timing is specified on the basis of 30% and 70% of VDDI. 4 Tamb = -40 to 85C, unless otherwise specified.
Table 13. Timings based on 1 MHz SCLK Speed
Item Symbol Condition Min. Data hold time *) Access time Output disable time Data setup time 1CS pulse width high T1 T2 T3 T4 T5 100 10 25 100 250 Rating Max. 125 450 450 ns ns ns ns ns Units
Note: 1 The input signal rise and fall times must be within 10ns. 2 Every timing is specified on the basis of 30% and 70% of VDDI. 3 Tamb = -40 to 85C, unless otherwise specified.
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STE2007
Figure 3.
Timing B
Command Tx HiZ
T1
HiZ Rx Status
T2
Command Tx HiZ
Timing A
!CS Timing B
T3 T4
Driver TxData
out T5
in
!CS
1/2 SCLK 1/2 SCLK
3.4.2
Table 14.
Reset Timing
Reset Timing
Description Signal !RES !RES !RES Symbol trs trw trj Min. 2500 1000 Max. 2500 ns Unit
Reset time Reset low pulse width (for valid reset) Reset rejection (for noise spike)
Note: 1 The input signal rise and fall times must be within 10ns. 2 Every timing is specified on the basis of 30% and 70% of VDDI. 3 Tamb = -40 to 85C, unless otherwise specified.
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STE2007
Figure 4.
trj !RES trs During reset trw
Normal operation
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4 INTERFACE
STE2007
4
4.1
INTERFACE
3-lines 9 bit Serial Interface
STE2007 3-lines 9 bits serial interface is a bidirectional link between the display driver and the host processor. It consists of three lines: SDAIN/SDAOUT Serial Data SCLK Serial Clock !CS Peripheral enable: - Active Low- Enables and Disables the serial interface
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of !RES, the serial interface is ready to receive data after the internal reset time. Serial data must be input to SDA in the sequence D/!C, D7 to D0. STE2007 read data on SCLK rising edge. The first bit of serial data D/!C is data/command flag. When D/!C =1 D7 to D0 bits are display RAM data or Command Parameters. When D/!C=0 D7 to D0 bits identify a command
4.1.1
Figure 5.
!CS
SDA
D/C D7
D6
D5
D4
D3
D2
D1
D0 D/C
D7
D6
D5
D4
SCLK
10
11
12
13
14
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STE2007
Figure 6. 3-lines SPI Data Transfer break condition
Break !CS
4 INTERFACE
SCL
SDA
D7
D6
D5
D4
D3
D/!C
D7
D6
D5
D4
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0204
SCL
SDA
D3
D2
D1
D0
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0203
4.1.2
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4 INTERFACE
STE2007
Self Testing of the electrical contacts is based on the monitoring of VLCD. The improper electrical contact on VDD can be noted from a too low level of VLCD. The serial interface Driver TxDatamode is controlled by three input signals. The serial data output (SDAOUT/Driver TxData) and serial clock input (SCLK) are enabled when !CS is low after having received one Reading Command. To access Driver TxDatamode a Reading command must be sent to STE2007 driver. The first bit (D/C) is low to indicates next 8bits are for command. The data is read to the driver on the rising edge of SCLK (see section MCU TxDatamode). After last command bit (bit 0) is read SDAOUT becomes active (Low impedance) and MCU is able to read data from driver. SDAOUT is forced in high impedence when !CS line is forced high or after the eight SCLK rising edges from the last SCLK rising edge of teh reading command transfer (Figure 8). After sending out all 8 bits the driver release automatically the bus and go back to the MCU TxDatamode. MCU Txdata line changes from highz to active low or high in the falling edge of 8th SCLK pulse. !CS must be set high and low again before !D/C writing can continue. If !CS is forced high during the Driver TxDAta-mode, the Driver Tx data session is aborted and SDAOUT is forced in high impedance Mode. SDAOUT and SDAIN line can be short circuited in normal working conditions. Figure 8. AC timing characteristics
Timing A SCLK
MCU TxData MCU Data direction Driver TxData
Timing B
Command Tx HiZ
T1
HiZ Rx Status
T2
Command Tx HiZ
Timing A
!CS Timing B
T3 T4
Driver TxData
out T5
in
!CS
1/2 SCLK 1/2 SCLK
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STE2007
Figure 9. Timing chart for start and stop of data reading from driver
Self Test command writing
SCLK 1 2 7
4 INTERFACE
Reading of status
9 1 2
D/C writing
1 D/C 2 7
8 1
...
High Z ...
7 6
... ...
!CS
4.2
4-Line SPI
STE2007 4-lines serial interface is a bidirectional link between the display driver and the host processor. It consists of four lines: SDA Serial Data SCL Serial Clock !CS Peripheral enable: - Active Low- Enables and Disables the serial interface Mode selection (D/!C).
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of !RES, the serial interface is ready to receive data after the internal reset time.
4.2.1
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4 INTERFACE
STE2007
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
COMMAND
COMMAND
COMMAND
LR0189
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
LR0190
D/!C
SCL
SDA
D7
D6
D5
D4
D3
D7
D6
D5
D4
D3
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0192
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STE2007
4 INTERFACE
If a new command identifier is transferred after a pause condition the previous communication session is definitively closed. Four are the possible conditions: Command-Pause-Command Command-Pause-Parameter Parameter-Pause-Command Parameter-Pause-Parameter
D/!C
SCL
SDA
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0191
4.2.2
DATA
Next Command
D7
D6
D5
D4
D3
D2
D1
D0 D7 D6 D5
High Z
D4 D3 D2 D1 D0
D7
D6
D5
D4
D3
D2
D1
D0
High Z
LR0255
MCU Data Tx Start LCD Driver Data Tx Start MCU Data Tx Start
4.3
I2C Bus
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different ICs. It consists of two lines: one bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined:
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4 INTERFACE
STE2007
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop Data Transfer condition (see below).
Accordingly, the following bus conditions have been defined: BUS not busy: Both data and clock lines remain High. Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the START condition. Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer starts with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves" Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2007 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. To be compliant with the I2C-bus Hs-mode specification the STE2007 is able to detect the special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hsmode without detecting the master code.
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STE2007
Figure 15. Bit transfer and START,STOP conditions definition
DATA LINE STABLE DATA VALID CLOCK
4 INTERFACE
DATA
START CONDITION
D00IN1151
STOP CONDITION
MSB
LSB
D00IN1152
4.3.1
Communication Protocol
The STE2007 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed. Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1.
4.3.2
ADDRESS BYTE
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4 INTERFACE
STE2007
4.3.3
The Co bit is the control byte MSB and defines if after this control byte will follow a single byte sequence (Co = 1) or a multiple bytes sequence (Co = 0). The D/C bit defines whether the following byte (if Co = 1) or the following stream of bytes (if Co = 0) are command (D/C = 0) or DDRAM data (D/C = 1). Depending on state of flags Co and D/C, four writing sequences are possible: SINGLE COMMAND BYTE SEQUENCE (Co = 1, D/C = 0): a single byte interpreted as a command will follow the control byte; SINGLE DATA BYTE SEQUENCE (Co = 1, D/C = 1): a single byte interpreted as a data to be written in DDRAM will follow the control byte; MULTIPLE COMMAND BYTES SEQUENCE (Co = 0, D/C = 0): a stream of bytes will follow the control byte, with each single byte interpreted as a command; MULTIPLE DATA BYTES SEQUENCE (Co = 0, D/C = 1): a stream of bytes will follow the control byte, with each byte interpreted as a data byte to be written in DDRAM. Every single byte of a sequence must be acknowledged by all addressed units. A multiple data sequence is terminated only by sending a STOP condition on the I2C bus. When a sequence is terminated, another sequence of any type can follow or a I2C STOP condition can be sent to close the communication. In a single or multiple data bytes sequence, every data byte received is stored in the DDRAM at the location specified by the current values of data pointers. Data pointers are automatically updated after each single data byte written.
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STE2007
4 INTERFACE
4.3.4
WRITE MODE
COMMUNICATION START
I2C START 0 COND 1 1 1 1
STE2007 ACK
SA1 SA2
SLAVE ADDRESS
R/W
Co D/C
STE2007 ACK
STE2007 ACK
1 0 0 0 0 0 0 0 A
COMMAND Byte
STE2007 ACK
0 0 0 0 0 0 0 0 A
COMMAND Byte
COMMAND Byte
Control Byte
Co D/C
STE2007 ACK
STE2007 ACK
1 1 0 0 0 0 0 0 A
DATA Byte
Control Byte
Data Byte
Co D/C
STE2007 ACK
STE2007 ACK
STE2007 ACK
0 1 0 0 0 0 0 0 A
DATA Byte
DATA Byte
Control Byte
COMMUNICATION STOP
READ MODE
STE2007 ACK MASTER ACK
SA1 SA2
0 A
STATUS Byte
LR0008d
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4 INTERFACE
STE2007
4.4
Reading Mode
STE2007 features a reading Command to transmitt data from the LCD driver to Host Processor. After the reading command STE2007 transfers 8 bits to the Host controller: Identification Byte (Command Code DBhex)
4.4.1
IIdentification byte
Identification byte is an 8 Bit code that identify the module revision Number. Table 15.
Bit nr
ID byte format
D7(MSB) D6 0 0 D5 IDB PAD D4 IDA PAD D3 0 D2 0 D1 0 D0(LSB) 0
Figure 18.
STE2007
Power IC VDDCP VDD VDDI VSS VSSCP
Command decoder
ASIC(MCU)
MCU TxData
RESET
8 bit register
Multi plexer
ID
test
Auto return
VLCD
Figure 19.
Identification Information
Send rading command (DBh)
Command:E2H
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STE2007
5
5.1
Each pixel can be selected when page address and column address are specified. The MCU issues Page address set command to change the page and access to another page. In DDRAM page address 8 (D3,D2,D1,D0=1,0,0,0) only display data D0,D1,D2 & D3 are valid. The DDRAM column address is specified by Column address set command. The specified column address is automatically incremented by +1 when a Display data write command is entered. After the last column address (5Fh), column address returns to 00h and page address incremented by +1. After the very last address (column=5Fh, page=8h), both column address and page address return to 00h (column address=00h, page address=0h). Figure 21. Column address in normal mode
Data LSBit D0 D1 D2 D3 D4 D5 D6 MSBit D7 Data for page address 0H to 07H
0H 1H 2H 3H Page address 4H 5H 6H 7H 8H D0 D1 D2 D3
2 98 194 290 386 482 578 674 770 02H Column address
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95
191 287 383 479 575 671 767 863
94
190 286 382 478 574 670 766 862 Column address 98 194 290 386 482 578 674 770 97 193 289 385 481 577 673 769
5FH 5EH
Data can be written to the DDRAM at the same time as data is being displayed, without causing the LCD to flicker. Segment driver direction command can be used to reverse the relationship between the DDRAM column address and segment output. This function is achieved writing data into DDRAM in reverse order (from Right to left). Table 16.
Column address Normal Direction Reverse Direction
5.2
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STE2007
Figure 23. 68line Mode
ICONMODE="1"
Page address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM66 COM0 COM65 COM1 COM64 COM2 COM3 COM63 COM4 COM62 COM5 COM61 COM6 COM60 COM7 COM59 COM8 COM58 COM9 COM57 COM10 COM56 COM11 COM55 COM12 COM54 COM13 COM53 COM14 COM52 COM15 COM51 COM16 COM50 COM17 COM49 COM18 COM48 COM19 COM47 COM20 COM46 COM21 COM45 COM22 COM44 COM23 COM43 COM24 COM42 COM25 COM41 COM26 COM40 COM27 COM39 COM28 COM38 COM29 COM37 COM30 COM36 COM31 COM35 COM32 COM34 COM33 COM33 COM34 COM32 COM35 COM31 COM36 COM30 COM37 COM29 COM38 COM28 COM39 COM27 COM40 COM26 COM41 COM25 COM42 COM24 COM43 COM23 COM44 COM22 COM45 COM21 COM46 COM20 COM47 COM19 COM48 COM18 COM49 COM17 COM50 COM16 COM51 COM15 COM52 COM14 1 COM53 COM13 COM54 COM12 COM55 COM1 COM56 COM10 COM57 COM9 COM58 COM8 COM59 COM7 COM60 COM6 COM61 COM5 COM62 COM4 COM63 COM3 COM64 COM2 COM65 COM1 COM66 COM0 COMS COMS Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM0 COMS COM66 COM1 COM65 COM2 COM3 COM64 COM4 COM63 COM5 COM62 COM6 COM61 COM7 COM60 COM8 COM59 COM9 COM58 COM10 COM57 COM11 COM56 COM12 COM55 COM13 COM54 COM14 COM53 COM15 COM52 COM16 COM51 COM17 COM50 COM18 COM49 COM19 COM48 COM20 COM47 COM21 COM46 COM22 COM45 COM23 COM44 COM24 COM43 COM25 COM42 COM26 COM41 COM27 COM40 COM28 COM39 COM29 COM38 COM30 COM37 COM31 COM36 COM32 COM35 COM33 COM34 COM34 COM33 COM35 COM32 COM36 COM31 COM37 COM30 COM38 COM29 COM39 COM28 COM40 COM27 COM41 COM26 COM42 COM25 COM43 COM24 COM44 COM23 COM45 COM22 COM46 COM21 COM47 COM20 COM48 COM19 COM49 COM18 COM50 COM17 COM51 COM16 COM52 COM15 COM53 COM14 COM54 COM13 COM55 COM12 COM56 COM11 COM57 COM10 COM58 COM9 COM59 COM8 COM60 COM7 COM61 COM6 COM62 COM5 COM63 COM4 COM64 COM3 COM65 COM2 COM66 COM1 COM0 COMS
Page 0
Page 1
Page 2
Page 3
Start
Start
Page 4
Page 5
Page 6
Page 7
Column address
Display start line does not access 65th, 66th, 67th, 68th line
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
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ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COM64 COM64 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
Page 0
Page 1
Page 2
Page 3
Start
Start
Page 4
Page 5
Page 6
Page 7
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
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Figure 25. 49line Mode
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM47 COM1 COM46 COM2 COM45 COM3 COM44 COM4 COM43 COM5 COM42 COM6 COM41 COM7 COM40 COM8 COM39 COM9 COM38 COM10 COM37 COM11 COM36 COM12 COM35 COM13 COM34 COM14 COM33 COM15 COM32 COM16 COM31 COM17 COM30 COM18 COM29 COM19 COM28 COM20 COM27 COM21 COM26 COM22 COM25 COM23 COM24 COM24 COM23 COM25 COM22 COM26 COM21 COM27 COM20 COM28 COM19 COM29 COM18 COM30 COM17 COM31 COM16 COM32 COM15 COM33 COM14 COM34 COM13 COM35 COM12 COM36 COM11 COM37 COM10 COM38 COM9 COM39 COM8 COM40 COM7 COM41 COM6 COM42 COM5 COM43 COM4 COM44 COM3 COM45 COM2 COM46 COM1 COM47 COM0 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM0 COM48 COM47 COM1 COM46 COM2 COM45 COM3 COM44 COM4 COM43 COM5 COM42 COM6 COM41 COM7 COM40 COM8 COM39 COM9 COM10 COM38 COM11 COM37 COM12 COM36 COM13 COM35 COM14 COM34 COM15 COM33 COM16 COM32 COM17 COM31 COM18 COM30 COM19 COM29 COM20 COM28 COM21 COM27 COM22 COM26 COM23 COM25 COM24 COM24 COM25 COM23 COM26 COM22 COM27 COM21 COM28 COM20 COM29 COM19 COM30 COM18 COM31 COM17 COM32 COM16 COM33 COM15 COM34 COM14 COM35 COM13 COM36 COM12 COM37 COM11 COM38 COM10 COM39 COM9 COM40 COM8 COM41 COM7 COM42 COM6 COM43 COM5 COM44 COM4 COM45 COM3 COM46 COM2 COM47 COM1 COM48 COM0
Page 0
Page 1
Page 2
Page 3
Start
Start
Page 4
Page 5
Page 6
Page 7
COM64
COM64
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
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ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM32 COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM10 COM22 COM11 COM21 COM12 COM20 COM13 COM19 COM14 COM18 COM15 COM17 COM16 COM16 COM17 COM15 COM18 COM14 COM19 COM13 COM20 COM12 COM21 COM11 COM22 COM10 COM23 COM9 COM24 COM8 COM25 COM7 COM26 COM6 COM27 COM5 COM28 COM4 COM29 COM3 COM30 COM2 COM31 COM1 COM32 COM0
Page 0
Page 1
Page 2
Page 3
Start
Start
Page 4
Page 5
Page 6
Page 7
COM64
COM64
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
5.3
Partial Display
STE2007 feature four configuration for Partial Display function: 33 Line Partial Display 25 Line Partial display 16 Line Partial Display 9 Line Partial Display
Partial display Area location on the screen is defined by Image Location Parameter. Image Location + Partial display area > Multiplexing rate.
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Figure 27.
Display
Display
When Partial Display Mode is enabled the user has to Update the Operative Voltage, Bias Ratio and Charge Pump Setting to match the new working conditions.
5.3.1
ICONMODE="0"
COM Output Normal Reverse direction direction COMS0 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COMS0 COM0
Page 0
IL[2:0]
IL[2:0]
Page 1
Page 2
Page 3
Start
Start
Page 4
Page 5
Page 6
Page 7
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
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ICONMODE="1"
ICONMODE="0"
Page address D3 D2 D1 D0
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
Page 0
IL[2:0]
Page 1
Page 2
Page 3
Start
Page 4
Page 5
Page 6
Page 7
COM Output Normal Reverse direction direction COM66 COM0 COM65 COM1 COM64 COM2 COM3 COM63 COM4 COM62 COM5 COM61 COM6 COM60 COM7 COM59 COM8 COM58 COM9 COM57 COM10 COM56 COM11 COM55 COM12 COM54 COM13 COM53 COM14 COM52 COM15 COM51 COM16 COM50 COM17 COM49 COM18 COM48 COM19 COM47 COM20 COM46 COM21 COM45 COM22 COM44 COM23 COM43 COM24 COM42 COM25 COM41 COM26 COM40 COM27 COM39 COM28 COM38 COM29 COM37 COM30 COM36 COM31 COM35 COM32 COM34 COM33 COM33 COM34 COM32 COM35 COM31 COM36 COM30 COM37 COM29 COM38 COM28 COM39 COM27 COM40 COM26 COM41 COM25 COM42 COM24 COM43 COM23 COM44 COM22 COM45 COM21 COM46 COM20 COM47 COM19 COM48 COM18 COM49 COM17 COM50 COM16 COM51 COM15 COM52 COM14 1 COM53 COM13 COM54 COM12 COM55 COM1 COM56 COM10 COM57 COM9 COM58 COM8 COM59 COM7 COM60 COM6 COM61 COM5 COM62 COM4 COM63 COM3 COM64 COM2 COM65 COM1 COM66 COM0 COMS COMS
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
IL[2:0]
Start
COM Output Normal Reverse direction direction COM0 COMS COM66 COM1 COM65 COM2 COM3 COM64 COM4 COM63 COM5 COM62 COM6 COM61 COM7 COM60 COM8 COM59 COM9 COM58 COM10 COM57 COM11 COM56 COM12 COM55 COM13 COM54 COM14 COM53 COM15 COM52 COM16 COM51 COM17 COM50 COM18 COM49 COM19 COM48 COM20 COM47 COM21 COM46 COM22 COM45 COM23 COM44 COM24 COM43 COM25 COM42 COM26 COM41 COM27 COM40 COM28 COM39 COM29 COM38 COM30 COM37 COM31 COM36 COM32 COM35 COM33 COM34 COM34 COM33 COM35 COM32 COM36 COM31 COM37 COM30 COM38 COM29 COM39 COM28 COM40 COM27 COM41 COM26 COM42 COM25 COM43 COM24 COM44 COM23 COM45 COM22 COM46 COM21 COM47 COM20 COM48 COM19 COM49 COM18 COM50 COM17 COM51 COM16 COM52 COM15 COM53 COM14 COM54 COM13 COM55 COM12 COM56 COM11 COM57 COM10 COM58 COM9 COM59 COM8 COM60 COM7 COM61 COM6 COM62 COM5 COM63 COM4 COM64 COM3 COM65 COM2 COM66 COM1 COM0 COMS
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
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5.3.2
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
Page 0
IL[2:0]
IL[2:0]
Page 1
Page 2
Page 3
Start
Page 4
Page 5
Page 6
Page 7
Column address
Display start line does not access 65th, 66th, 67th, 68th line
IMAGE lOCATION (IL[2:0]) + Partial display Area Width (19hex) <= Multiplexing Rate (40hex)
Normal Direction Reverse Direction S E G 0 S E G 95 S E G 1 S E G 94 S E G 2 S E G 93 S E G 3 S E G 92 S E G 4 S E G 91 S E G 5 S E G 90 S E G 6 S E G 89 S E G 89 S E G 6 S E G 90 S E G 5 S E G 91 S E G 4 S E G 92 S E G 3 S E G 93 S E G 2 S E G 94 S E G 1 S E G 95 S E G 0
SEG Output
Start
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5.3.3
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COM64 COM64 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
Page 0
IL[2:0]
IL[2:0]
Page 1
Page 2
Page 3
Start
Start
Page 4
Page 5
Page 6
Page 7
Column address
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
Normal Direction Reverse Direction S E G 0 S E G 95 S E G 1 S E G 94 S E G 2 S E G 93 S E G 3 S E G 92 S E G 4 S E G 91 S E G 5 S E G 90 S E G 6 S E G 89 S E G 89 S E G 6 S E G 90 S E G 5 S E G 91 S E G 4 S E G 92 S E G 3 S E G 93 S E G 2 S E G 94 S E G 1 S E G 95 S E G 0
SEG Output
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5.3.4
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
Page 0
IL[2:0]
IL[2:0]
Page 1
Page 2
Page 3
Start
Start
Page 4
Page 5
Page 6
Page 7
Column address
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
Normal Direction Reverse Direction S E G 0 S E G 95 S E G 1 S E G 94 S E G 2 S E G 93 S E G 3 S E G 92 S E G 4 S E G 91 S E G 5 S E G 90 S E G 6 S E G 89 S E G 89 S E G 6 S E G 90 S E G 5 S E G 91 S E G 4 S E G 92 S E G 3 S E G 93 S E G 2 S E G 94 S E G 1 S E G 95 S E G 0
SEG Output
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5.4
Table 17.
Segment drivers Direction Common Drivers Direction VOR - Voltage Range Electronic Volume Power Control Register ID byte Charge Pump Bias Ratio VLCD Temeprature Comp. N-Line Inversion Multiplexing Rate Refresh Rate Image Location Icon Mode
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6 Instruction Setups
6
6.1
Instruction Setups
Initialization (Power ON Sequence)
Power ON
Reset status
V0-Voltage Range (**H) Electronic volume (**H) Power saver OFF (Display all points OFF (A4H))
6.2
Display data write This command is needed only at 1st time after initialization.
Display ON (AFH)
6.3
Power OFF
Optional Status !RES Pin="Low Level" min.20ms
Power Saver Status or Booster OFF Status !RES Pin="Low Level" min. 0ms
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VDDI VDD
tpi >0s tpi >0s
Inputs Outputs
High-Z tcs >0s tcs >0s High-Z
!CS
tPWROFF1 >0 ms tPWROFF2 >20ms tp2 >0s
!RES
trs = max. 5s
INTERNAL RESET
Reset State
Trs = max. 5s
Reset State
XCS,SDAIN,XRES can become High simultaneously with VDDI (tcs>0,tpi>0;tp2>0). trs= max 5000ns (Internal Reset Time- see AC Characteristics Paragraph) tPWROFF1>0ms must be considered when driver is in Power Saver or Booster OFF status tPWROFF2>20ms must be considered when driver is in Normal Working Condition VDDI, VDD and VDD_CP can come up/go down in any sequence VDDI can be Up with VDD, VDDCP down and viceversa. If only one supply rail is up, the driver is forced in reset state. If VDD is high after VDDI all timing referred to VDDI must be referred to VDD (Fig. 24) Figure 34. Timing for phones power on sequence when VDDI Up before VDD
tp1 < 0 tp1 < 0
VDDI VDD
tpi >0s tpi >0s
SDAIN SDAOUT
High-Z tcs >0s tcs >0s High-Z
!CS
tPWROFF1 >0 ms tPWROFF2 >20ms tp2 >0s
!RES
trs = max. 5s
INTERNAL RESET
Reset State
Trs = max. 5s
Reset State
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Table 18. Instruction Set
Code Command (D/C) D7 Display ON/OFF Display normal/ reverse Display all points ON/ OFF Page address set Column address set upper 3bit address Column address set lower 4bit address Display start line address set Segment driver direction 0 0 0 0 0 0 0 1 1 1 1 0 0 0 D6 0 0 0 0 0 0 1 D5 1 1 1 1 0 0 D4 0 0 0 1 1 0 * D3 1 0 0 D2 1 1 1 D1 1 1 0
Function D0 Hex 0 1 0 1 0 1 AE LCD display AF 0: OFF, 1: ON A6 LCD display A7 0: normal, 1: reverse A4 LCD display A5 0: normal display, 1: all points ON Sets the DDRAM page address
address address
Sets the DDRAM column address address address Sets the DDRAM display start line address 0 1 Sets the correspondence between A0 the DDRAM column address and A1 the SEG driver output. 0:Normal, 1: reverse Sets the correspondence between the DDRAM line address and the COM driver output. 0: normal, 1: reverse Writes to the DDRAM 0 1 1 DB Identification byte Sets the onchip power supply circuit operating mode Sets the electronic volume value Sets the electronic volume value Compound command of Display OFF and Display-all-points-ON E2 Internal reset E3 Nonoperation E1 Sets the VLCD 0 0 Termal Compensation 0 * * * * * 0 0 1 VOP[7:0] 1 1 0 0 Thermal Comp 0 38 SET VLCD Slope in temperature
0 1
Display data write Self Test/Identification data reading Power control set VO-Range Electronic volume Power saver Reset NOP VOP
1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 1 0 1 1 1
Write data 1 0 0 1 1 0
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Table 18.
Command
Charge Pump 0 0 Refresh Rate 0 Bias ratio N-line Inversion 0 Number of Lines Image Location 0 Icon Mode 0 0 STM TEST MODE1 0 STM TEST MODE2 STM TEST MODE3 STM TEST MODE4 STM TEST MODE5 STM TEST MODE6 STM TEST MODE7 STM TEST MODE8 0 0 0 0 0 0 0 * 1 1 1 1 1 1 1 * 0 0 0 1 1 1 1 * 1 1 0 0 0 0 0 0
Refersh Rate
Bias Ratio 1 0 1 AD
N-Line Inversion 0 1 Mux Rate 1 0 IL[2:0] 0 0 * 1 1 0 1 0 1 0 Ico n 1 * 0 1 0 1 0 0 1 A9 Reserved for STM (STM Test Mode) AA AB A8 FF FC FE FD Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) 0 AC SET Initial Row on Display
* = Disabled bits.
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8 Commands
8
8.1
Commands
Display ON/OFF
This command turns the display ON and OFF
Table 19.
(D/C) 0 0
Display ON/OFF
D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 HEX AE AF Setting Display OFF Display ON
When the Display OFF command is executed in the Display all points ON mode, Power saver mode is entered. See the section on the Power saver for details.
8.2
Display normal/reverse
This command can reverse the lit and unlit without overwriting the contents of the DDRAM.
Table 20.
(D/C) 0 0 D7 1
Display normal/reverse
D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 HEX A6 A7 Setting Normal:DDRAM Data H=LCD ON voltage Reverse:DDRAM Data L=LCD ON voltage
8.3
Table 21.
(D/C) 0 0 D7 1
When the Display all points ON command is executed when in the Display OFF mode, Power saver mode is entered. See the section on the Power Saver for details.
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8.4
Table 22.
(D/C) 0 0 0 0 0 D7 1
8.5
Table 23.
(D/C) 0 D7 0
* Disabled bit
(D/C) 0 0 0 . . 0 0 1 1 0 0 1 1 A6 0 0 0 A5 0 0 0 A4 0 0 0 A3 0 0 0 . . 1 1 1 1 1 1 0 1 5EH 5FH A2 0 0 0 A1 0 0 1 A0 0 1 0 Column address 00H 01H 02H
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8 Commands
8.6
Table 24.
(D/C) 0 0 0 : 0 0 0 0 D7 0 0 0
Display start line assress con be used in partial dispaly mode to relocate the partial display window on the screen. Display start line + Partial Display area with must be smaller or equal to the number of line selected.
8.7
Table 25.
(D/C) 0 0 D7 1
8.8
Table 26.
(D/C) 0 D7 1
* Disabled bit
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8.9
Table 27.
(D/C) 1
Write Data
8.10
Table 28.
(D/C) 0 0 D7 1 0
ID Byte
D6 1 0 D5 0 IDB D4 1 IDA D3 1 0 D2 0 0 D1 1 0 D0 1 0 HEX DB Setting Reads ID byte Pad Default
8.11
Table 29.
(D/C) 0 0 0 0 0 0 0 0 D7 0
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8 Commands
8.12
VLCD set
The LCD Voltage VLCD at reference temperature (TA = 25C) can be set using the Voltage Range V0R, Electronic Volume EV and VOP registers content according to the following formula: VLCD (T=TA) = ( V0P[7:0] + EV[4:0] - 16 + 32 V0R[2:0]) B + VLCDMIN with the following values:
Symbol B VLCDMIN TA Value 0.04 3 25 Unit V V C Room Temperature Note Single Voltage Step
For information on VLCD thermal compensation see PAR. 8.18 . Figure 35.
Vout 13.20V EV[3:0]
12h 10h 11h 1Fh
B
00h
VOP[7:0]*B+V-OR
3V
00h
FFh
Figure 36.
V0R[2:0] EV[4:0] DAC Step: 40mV Range 3V-13.20V Thermal Compensation VOUT
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V0R
D6 0 D5 1 D4 0 D3 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 HEX 20 21 22 23 24 25 26 27 V0R Value 0 1 2 3 4 5 6 7 32 V0R B + VLCDMIN 3.00 V 4.28 V 5.56 V 6.84 V 8.12 V (Default) 9.40 V 10.68 V 11.96 V
Table 31.
(D/C) 0 0 0 0 0 0 0 0 D7 0
VOP Set
D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 HEX E1 Function Command Identifier Data Field
Table 33.
VOP
HEX 00 01 02 : 7F 80 81 : FD FE FF VOP Adjustment 0 Step (Default) +1 Step +2 Step : +127 Step 0 Step -1 Step : -125 Step -126 Step -127 Step
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8 Commands
Electronic volume
D7 1 D6 0 D5 0 D4 D3 D2 D1 D0 Setting Command Identifier + Data Field
Table 35.
(D/C) 0 0 0 : 0 : 0 0 D7 1
EV
D6 0 D5 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 : 1 0 0 : 1 1 1 1 1 1 1 1 0 1 0 0 D1 0 0 1 D0 0 1 0 Hex 80 81 82 : 90 : 9E 9F EV Value 0 Step 1 Step 2 Step : 16 Step (Default) : 30 Step 31 Step high : : VLCD voltage low
8.13
Command
Effect
The internal states in power saver mode are as follows: The oscillation circuit is stopped The LCD power supply circuit is stopped The LCD driver circuit is stopped and segment/common driver outputs to the Vss level
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The display data and operation mode before execution of the Power saver are held, and the MCU can access to the DDRAM and internal registers.
8.14
Reset
When this command is issued, the driver is initialized.This command doesnt change DDRAM content.
Table 36.
(D/C) 0
Reset
D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 HEX E2 Function Command Identifier
8.15
NOP
Nonoperation command.
Table 37.
(D/C) 0
NOP
D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 HEX E3 Function Command Identifier
8.16
Image Location
Image Location Command
Table 38.
(D/C) 0 0
Image Location
D7 1 * D6 0 * D5 1 * D4 0 * D3 1 * D2 1 IL2 D1 0 IL1 D0 0 IL0 HEX AC Function Command Identifier Data Field
Table 39.
IL2 0 0 0 0 1 1 1 1
Image Location
IL1 0 0 1 1 0 0 1 1 IL0 0 1 0 1 0 1 0 1 Function 0 Lines 8 Lines 16 Lines 24 Lines 32 Lines 48 Lines 56 Lines 64 Lines
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8 Commands
8.17
Bias Ratio
It is possible to select different Bias Ratio.
Table 40.
(D/C) 0
Bias Ratio
D7 0 D6 0 D5 1 D4 1 D3 0 D2 BR2 D1 BR1 D0 BR0 Function Command Identifier + Data Field
Table 41.
BR2 0 0 0 0 1 1 1 1
BIAS Ratio
BR1 0 0 1 1 0 0 1 1 BR0 0 1 0 1 0 1 0 1 Function Bias Ratio =1/10 - 81 Lines Bias Ratio = 1/9 - 65 Lines Bias Ratio =1/8 - 49 Lines Bias Ratio = 1/7 - 33 Lines Bias Ratio =1/6 - 25 Lines Bias Ratio = 1/5 - 17 Lines Bias Ratio =1/4 - 9 Lines Not Used
Table 42.
BR=001
VLCD R 9 VLCD 10 8 VLCD 9 R 8 VLCD 10 7 VLCD 9 5R 2 VLCD 10 2 VLCD 9 R 1 VLCD 10 1 VLCD 9 R
BR=010
VLCD
BR=011
VLCD R 7 VLCD 8 6 VLCD 7 R 6 VLCD 8 5 VLCD 7 3R 2 VLCD 8 2 VLCD 7 R 1 VLCD 8 1 VLCD 7 R
6R
4R
VSS
VSS
VSS
VSS
BR=100
VLCD
BR=101
VLCD R 5 VLCD 6 4 VLCD 5 R 4 VLCD 6 3 VLCD 5 1R 2 VLCD 6 2 VLCD 5 R 1 VLCD 6 1 VLCD 5 R
BR=110
VLCD
2R
VSS
VSS
VSS
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8.18
Temperature Compensation
Its is possible to select different VLCD temperature compensation Coefficients.
Table 43.
(D/C) 0 0
Temperature Compensation Formula: VLCD(T) = VLCD(TA) [1 + (T(C) - TA) TC] TC = Temperature Compensation Coefficients T(C) = Temperature VLCD(TA) = LCD Voltage at TA Temperature (Room Temperature) Table 44.
TC2 0 0 0 0 1 1 1 1
TC
TC0 0 1 0 1 0 1 0 1 TC Value TC= 0 PPM TC= -300 PPM TC= -600 PPM TC= -900 PPM TC= -1070 PPM TC= -1200 PPM TC= -1500 PPM TC= -1800 PPM
TC1 0 0 1 1 0 0 1 1
8.19
Table 45.
(D/C) 0 0
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Table 46.
CP1 0 0 1 1
8 Commands
8.20
Refresh Rate
It is possible to select different Refresh Rate.
Table 47.
(D/C) 0 0
Refresh Rate
D7 1 * D6 1 * D5 1 * D4 0 * D3 1 * D2 1 * D1 1 RR1 D0 1 RR0 HEX EF Function Command Identifier Data Field
Table 48.
RR1 0 0 1 1
Refresh Rate
RR0 0 1 0 1 Function 80 Hz 75 Hz 70 Hz 65 hz
8.21
Icon Mode
Icon Mode 0: Icon Mode Disabled 1: Icon Mode Enabled
Table 49.
(D/C) 0
Icon Mode
D7 1 D6 1 D5 1 D4 1 D3 1 D2 0 D1 0 D0 ICON Function Command Identifier
8.22
N- Line Inversion
N-line Inversion Function.
Table 50.
(D/C) 0 0
N-Line Inversion
D7 1 * D6 0 * D5 1 F1 D4 0 NL4 D3 1 NL3 D2 1 NL2 D1 0 NL1 D0 1 NL0 HEX AD Function Command Identifier Data Field
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N-Line
NL3 0 * * 0 0 : 1 NL2 0 * * 0 0 : 1 NL1 0 * * 0 1 : 1 NL0 0 * * 1 0 : 1 Function N-line inversion disabled (default) XOR function disabled XOR function enabled N-line inversion enabled N-line inversion enabled : N-line inversion enabled 2 3 : 32 N row
Table 51.
F1 * 0 1 * * : * NL4 0 * * 0 0 : 1
The XOR function defines the polarity as the result of the logical XOR between the N-Line and the frame polarity.
(D/C) 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 M2
8.23
Number of Lines
Multiplexing Rate setting command.
Table 52.
D1 M1 D0 M0
Number of Lines
Function Command Identifier + Data Field
Table 53.
M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1
Multiplexing Rate
M0 0 1 0 1 0 1 0 1 Function 68 Lines (Default) 65 Lines 49 Lines 33 Lines 33 Lines Partial Display 25 Lines Partial Display 17 Lines Partial Display 9 Lines Partial Display
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9
Table 54.
Wafer Thickness Die Size (X x Y) Bumps Size on Columns and Segments Side Pad Size on Columns and Segments Side Bumps Pitch on Columns and Segments Side Bumps Size on Interfaces Side Pad Size on Interfaces Side Bumps Pitch on Interfaces Side Spacing between Bumps
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Table 55.
Y(m) -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 NAME C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46
Table 55.
NAME R16 R14 R12 R10 R8 R6 R4 R2 R0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
Pad Coordinates
PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 X (m) -2632.5 -2587.5 -2542.5 -2497.5 -2452.5 -2407.5 -2362.5 -2317.5 -2272.5 -2227.5 -2182.5 -2137.5 -2092.5 -2047.5 -2002.5 -1957.5 -1912.5 -1867.5 -1822.5 -1777.5 -1732.5 -1687.5 -1642.5 -1597.5 -1552.5 -1507.5 -1462.5 -1417.5
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Table 55.
NAME C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74
Table 55.
NAME C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 R1 R3 R5 R7 R9 R11 R13
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Table 55.
NAME TEST4 VSS_AUX VSS_AUX VSS_AUX VSS_AUX N_RES N_CS T2 T1 T0 VSS VSS VSS VSS_LCD VSS_LCD VSS_LCD VSS_CP VSS_CP VSS_CP DC SDAOUT SDIN SDOUT SCLK VREF_BUFF VSS_AUX SEL1 SEL0
Table 55.
NAME R15 R17 R19 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 R41 R43 R45 R47 R49 R51 R53 R55 R57 R59 R61 R63 R65 R67 TEST3
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Table 55.
NAME SA1 SA0 IDB IDA OSC_IN VDDI VDDI VDDI VDDI VDDI VDDI VDD VDD VDD VDD VDD VDD VDD_CP VDD_CP VLCD_SNS VLCD VLCD VLCD VLCD TEST4 TEST5 R66 R64
Table 55.
NAME R62 R60 R58 R56 R54 R52 R50 R48 R46 R44 R42 R40 R38 R36 R34 R32 R30 R28 R26 R24 R22 R20 R18
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Figure 38. Alignment marks dimensions
Table 56.
MARKS Mark1 Mark2 Mark3 Mark4 Mark5
35 m 85 m
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10 Revision history
10
Revision history
Date 9-Nov-2005 Revision 1 Initial release. Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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