Exercise 6: Combinational Circuit Blocks

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Problem 1.

Complete the 4:1 mux circuit by sketching the missing wires.

I0 I0 I1 I2 I3 S1 S0 Y I2 I3 I1

S0 S1

4:1 Mux Symbol

4:1 Mux Circuit

Contains material Digilent, Inc.

7 pages

Exercise #6: Combinational Circuit Blocks

Problem 3.

Complete the truth table and circuit sketch for a 4:1 mux. When completing the truth table, make use of dont cares to reduce the number of required rows.
EN

EN

S1

S0

I0 EN I0 I1 I2 I3 S1 S0 I3 Y I2 I1 Y

4:1 mux with enable truth table

S0 S1

4:1 Mux with enable

Problem 4.

Sketch an 8:1 mux using two 4:1 muxes and one 2:1 mux. Be sure to label all inputs and outputs.

Exercise #6: Combinational Circuit Blocks

Problem 5:

Compete a circuit sketch to show how F = m(0, 2, 4, 5, 6) can be implemented using the mux shown. (Hint: prepare an enteredvariable K-map).

I0 I1 I2 I3 S1 S0 Y

S2

S1

S0

Problem 6.

Complete the 3:8 decoder schematic on the right by sketching the missing wires.
Y0 S2 S1 S0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

3:8 Decoder Symbol

EN

3:8 Decoder Circuit

S2 S1 S0

Problem 7.

Complete the 3:8 decoder with enable schematic by sketching the missing wires.
EN S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Exercise #6: Combinational Circuit Blocks

Problem 8:

Complete the 4:16 decoder built from 4 2:4 decoders below by sketching the missing wires. Label all inputs and outputs.

EIN I0 I1

Y0 Y1 Y2 Y3

EIN I0 I1 EIN I0 I1 Y0 Y1 Y2 Y3 EIN I0 I1

Y0 Y1 Y2 Y3

Y0 Y1 Y2 Y3

EIN I0 I1

Y0 Y1 Y2 Y3

Problem 9.

Complete a sketch to show how the 3:8 decoder can be used to implement the logic equation F = m(1, 2, 4, 6)

Decoder inputs and outputs are all asserted HIGH.

Y0 S0 S1 S2 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Exercise #6: Combinational Circuit Blocks

Problem 10. Complete the truth table. The table shows the nine decimal Digit Inputs Outputs 4-bit numbers Segment-drive functions digits, their binary equivalents, and seven columns labeled AB3 B2 B1 B0 A B C D E F G G. The columns labeled A-G 0 0 0 0 0 can be used to record when a 1 0 0 0 1 segment must be illuminated to 2 0 0 1 0 display a given digit. For 3 0 0 1 1 example, in the first row 4 0 1 0 0 corresponding to the digit '0', 5 0 1 0 1 segments A, B, C, D, E, and F 6 0 1 1 0 must be illuminated, so a '1' 7 0 1 1 1 must be placed in those 8 1 0 0 0 columns. When completed, the 9 1 0 0 1 table can serve as a truth table NA 1 0 1 0 for the seven-segment NA 1 0 1 1 controller it shows the NA 1 1 0 0 required logic relationship NA 1 1 0 1 between the four inputs and NA 1 1 1 0 seven outputs. Note that in the NA 1 1 1 1 truth table, the last six input patterns (1010 through 1111) are not associated with a decimal digit. They are therefore "illegal" inputs, so outputs can receive a don't care for those rows. Problem 12. Complete the truth table for a three-input priority encoder. When completing the truth table, note that if I3 is a 1, it DOES NOT matter what I2, I1, or I0 are the encoded output will be 11. This information can result in dont cares in the truth table, which makes the design much easier (note that Xs have been used in the truth table to indicate dont care input conditions). When the truth table is complete, write VHDL equations to define the encoder circuits.

EIN 0 1 1 1 1 1

I3 X 1 0 0 0 0

I2 X X 1 0 0 0

I1 X X X 1 0 0

I0 X X X X 1 0

GS 0

Y1 0

Y0 0

EOUT 0

Priority encoder truth table

Exercise #6: Combinational Circuit Blocks

Problem 13. Complete the truth table for a 4-bit shifter that has no enable input, no rotate input, two inputs that dictate whether the input is to be shifted 0, 1, 2, or 3 bits, a direction input, and a fill input.

A1

A0

Y3

Y2

Y1

Y0

Problem 14. Complete the table below to show the numerical results from applying the indicated operation to the data shown. Opcodes are six-bit numbers defined as shown below. R = 1 for Rotate; D = 1 for Right; F is fill, and A2-A0 define the number of bits. Show all work to be eligible for partial credit.

A2

A1

A0

Input(Base10) 47 96 16 111 63 188

Input(Base2/8-bit) 00101111

Op Code 000011 110111 011001 100011 001111 110001

Output(Base10) 188

Output(Base2/8-bit)) 01111000

Problem 15. Modify only two characters in the code below to add a Fill bit.

Exercise #6: Combinational Circuit Blocks

entity m _shift is y port (din : r , d, f, en : dout : end m _shift ; y

in std _logic _vector (7 dow nto 0); in std _logic ; out std _logic _vector (7 dow nto 0)) ;

architecture m _shift _arch of m _shift is y y begin dout <= 00000000 w hen en = '0' else din (6 dow nto 0) & din (7) w hen (r = '1' and d = '0') else din (0) & din (7 dow nto 1) w hen (r = '1' and d = '1') else din (6 dow nto 0) & ' 0' w hen (r = '0' and d = '0') else ' 0' & din (7 dow nto 1); end m _shift _arch ; y