library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.

ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity nonoverlap_seq is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; x : in STD_LOGIC; z : out STD_LOGIC); end nonoverlap_seq; architecture Behavioral of nonoverlap_seq is

type state_type is(s0,s1,s2,s3); signal state:state_type:=s0; begin process(clk,reset) begin if(reset='1')then state<=s0; elsif(clk'event and clk='1')then case state is when s0=> if(x='1')then state<=s1; end if; z<='0'; when s1=> if(x='0')then state<=s0; else state<=s2;

end if; z<='0'; when s2=> if(x='0')then state<=s3; end if; z<='0'; when s3=> if(x='0')then z<='0'; else z<='1'; end if; state<=s0; end case; end if; end process;

end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM; --use UNISIM.VComponents.all; entity seq is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; x : in STD_LOGIC; z : out STD_LOGIC); end seq; architecture Behavioral of seq is type state_type is(s0,s1,s2,s3); signal state:state_type:=s0; begin process(clk,reset) begin if(reset='1')then state<=s0; elsif(clk'event and clk='1')then case state is when s0=> if(x='1')then state<=s1; end if; z<='0'; when s1=> if(x='0')then state<=s0; else state<=s2; end if; z<='0'; when s2=> if(x='0')then state<=s3; end if; z<='0'; when s3=> if(x='0')then state<=s0; z<='0'; else state<=s1; z<='1';

end if; end case; end if; end process;

end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sa is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; x : in STD_LOGIC_VECTOR (3 downto 0); y : in STD_LOGIC_VECTOR (3 downto 0); sum : out STD_LOGIC_VECTOR (3 downto 0); carry : out STD_LOGIC;

start : in end sa;

STD_LOGIC);

architecture Behavioral of sa is signal cout:std_logic_vector(3 downto 0); type state_type is(s0,s1,s2,s3); signal state,nxtstate:state_type; begin p1:process(clk,reset) begin if(reset='1')then state<=s0; elsif(clk'event and clk='1')then state<=nxtstate; end if; end process p1; p2:process(state,start) begin case state is when s0=> if(start='1')then sum(0)<= x(0)xor y(0); cout(0)<=x(0)and y(0); nxtstate<=s1; end if; when s1=> sum(1)<= (x(1)xor y(1))xor cout(0); cout(1)<=(x(1)and y(1)) or (cout(0)and(x(1)and y(1))); nxtstate<=s2;

when s2=> sum(2)<= (x(2)xor y(2))xor cout(1); cout(2)<=(x(2)and y(2)) or (cout(1)and(x(2)and y(2))); nxtstate<=s3;

when s3=>

sum(3)<= (x(3)xor y(3))xor cout(2); cout(3)<=(x(3)and y(3)) or (cout(2)and(x(3)and y(3))); nxtstate<=s0;

end case; carry<=cout(3); end process p2; end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity upd is Port ( mode : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC; z : out integer); end upd;

architecture Behavioral of upd is type state_type is(s0,s1,s2,s3,s4,s5); signal state:state_type:=s0; begin p1:process(clk,reset) begin if(reset='1')then state<=s0; elsif(clk'event and clk='1')then case state is when s0=> if(mode='1')then state<=s1; else state<=s5; end if; when s1=> if(mode='1')then state<=s2; else state<=s0; end if; when s2=> if(mode='1')then state<=s3; else state<=s1; end if; when s3=> if(mode='1')then state<=s4; else state<=s2;

end if; when s4=> if(mode='1')then state<=s5; else state<=s3; end if; when s5=> if(mode='1')then state<=s0; else state<=s4; end if; end case; end if; end process p1; p2:process(state) begin case state is when s0=>z<=0; when s1=>z<=1; when s2=>z<=2; when s3=>z<=3; when s4=>z<=4; when s5=>z<=5; end case; end process p2;

end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

package mypkg is type array1 is array(9 downto 0) of integer;

function big(a:array1)return integer; function zeros(a:std_logic_vector(15 downto 0)) return integer; function ones(a:std_logic_vector(15 downto 0)) return integer; function bv(b:std_logic_vector) return integer; function intb(a:integer) return std_logic_vector; end mypkg; package body mypkg is

function big(a:array1)return integer is variable temp:integer:=0;

begin for i in a'range loop if(temp<a(i))then temp:=a(i); end if; end loop; return temp; end big;

function zeros(a:std_logic_vector(15 downto 0)) return integer is variable no: integer:=0; begin for i in a'range loop if(a(i)='0') then no:=no+1; end if; end loop; return no; end zeros;

function ones(a:std_logic_vector(15 downto 0)) return integer is variable no: integer:=0; begin for i in a'range loop if(a(i)='1') then no:=no+1; end if; end loop; return no; end ones;

function bv(b:std_logic_vector) return integer is variable result:integer:=0; begin for i in b'range loop if(b(i)='1')then result:=result*2+1; end if; end loop; return result;

end bv;

function intb(a:integer) return std_logic_vector is variable temp:std_logic_vector(0 to 64); variable no:integer:=a; variable i:integer:=0; begin while(no>=1)loop if((no rem 2)=1)then temp(i):='1'; else temp(i):='0'; end if; no:=no/2; i:=i+1; end loop; return temp(0 to i);

end intb;

end package body mypkg;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; library pkg_lib; use pkg_lib.mypkg.all; entity pk is port( x:in array1; y:in std_logic_vector(15 downto 0); z:in std_logic_vector(7 downto 0); w:in integer;

zero:out integer; biggest:out integer; one:out integer; binary:out std_logic_vector(0 to 64); number:out integer); end pk; architecture Behavioral of pk is begin process(x,y,z,w) begin zero<=zeros(y); biggest<=big(x); one<=ones(y); binary<=intb(w); number<=bv(z); end process; end Behavioral;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity SRAM is generic(

width:integer:=16; depth:integer:=4; addr:integer:=2); port( Clock:in std_logic; Enable:in std_logic; Read:in std_logic; Write:in std_logic; Read_Addr:in std_logic_vector(addr-1 downto 0); Write_Addr: in std_logic_vector(addr-1 downto 0); Data_in: in std_logic_vector(width-1 downto 0); Data_out: out std_logic_vector(width-1 downto 0)); end SRAM;

architecture behav of SRAM is-- use array to define the bunch of internal temparary signals type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram:ram_type; begin -- Read Functional Section process(Clock, Read) begin if (Clock'event and Clock='1') then if Enable='1' then if Read='1' then-- buildin function conv_integer change the type-- from std_logic_vector to integer Data_out <= tmp_ram(conv_integer(Read_Addr)); else Data_out <= (Data_out'range => 'Z'); end if; end if;

end if; end process;-- Write Functional Section

process(Clock, Write) begin if (Clock'event and Clock='1') then if Enable='1' then if Write='1' then tmp_ram(conv_integer(Write_Addr)) <= Data_in; end if; end if; end if; end process; end behav;