CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

October 1987 Revised March 2002

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

General Description
The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS.

Features
s Wide supply voltage range: s Low power TTL compatibility: or 1 driving 74LS s Low power: 50 nW (typ.) 3.0V to 15V Fan out of 2 driving 74L s High noise immunity: 0.45 VDD (typ.)

s Medium speed operation: 12 MHz (typ.) with 10V supply

Ordering Code:
Order Number CD4027BCM CD4027BCN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Truth Table
Inputs tn1 (Note 1) CL (Note 3) J I X O X X X X X K X O X I X X X X S O O O O O I O I R O O O O O O I I Q O I O I X X X X I O I Q I I O O Outputs tn (Note 2) Q O O I I (No Change) O I I

    
X X X

Top View

I = HIGH Level O = LOW Level X = Don't Care = LOW-to-HIGH = HIGH-to-LOW

 

Note 1: tn1 refers to the time interval prior to the positive clock pulse transition Note 2: tn refers to the time intervals after the positive clock pulse transition Note 3: Level Change

2002 Fairchild Semiconductor Corporation

DS005958

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CD4027BC

Logic Diagram

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CD4027BC

Absolute Maximum Ratings(Note 4)

(Note 5) DC Supply Voltage (VDD ) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW

Recommended Operating Conditions (Note 5)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3V to 15 VDC 0V to VDD VDC

0.5 VDC to +18 VDC 0.5V to VDD +0.5 VDC 65C to +150C

55C to +125C

Note 4: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device operation. Note 5: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 6)

Symbol IDD Parameter Quiescent Device Current Conditions VDD = 5V, VIN = VDD or VSS VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS VOL LOW Level Output Voltage |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage |IO| < 1 A VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage VIH HIGH Level Input Voltage IOL LOW Level Output Current (Note 7) IOH HIGH Level Output Current (Note 7) IIN Input Current VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V
Note 6: VSS = 0V unless otherwise specified. Note 7: IOH and IOL are tested one output at a time.

55C Min Max 1 2 4 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.64 1.6 4.2 0.64 1.6 4.2 0.1 0.1 3.5 7.0 11.0 0.51 1.3 3.4 0.51 1.3 3.4 4.95 9.95 14.95 Min

+25C Typ Max 1 2 4 0 0 0 5 10 15 1.5 3.0 4.0 0.05 0.05 0.05

+125C Min Max 30 60 120 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0

Units

0.88 2.25 8.8 0.88 2.25 8.8 105 105 0.1 0.1

0.36 0.9 2.4 0.36 0.9 2.4 1.0 1.0 A mA mA

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CD4027BC

AC Electrical Characteristics
Symbol tPHL or tPLH Parameter Propagation Delay Time from Clock to Q or Q tPHL or tPLH Propagation Delay Time from Set to Q or Reset to Q tPHL or tPLH Propagation Delay Time from Set to Q or Reset to Q tS Minimum Data Setup Time

(Note 8)
Conditions VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Min Typ 200 80 65 170 70 55 110 50 40 135 55 45 100 50 40 2.5 6.2 7.6 15 10 5 100 40 32 80 30 25 5 35 200 80 65 160 60 50 7.5 pF pF ns ns s 5 12.5 15.5 MHz Max 400 160 130 340 140 110 220 100 80 270 110 90 200 100 80 ns ns ns ns ns Units

TA = 25C, CL = 50 pF, trCL = tfCL = 20 ns, unless otherwise specified

tTHL or tTLH

Transition Time

VDD = 5V VDD = 10V VDD = 15V

fCL

Maximum Clock Frequency (Toggle Mode)

VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Any Input Per Flip-Flop (Note 9)

trCL or tfCL

Maximum Clock Rise and Fall Time

tW

Minimum Clock Pulse Width (tWH = tWL)

tWH

Minimum Set and Reset Pulse Width

CIN CPD

Average Input Capacitance Power Dissipation Capacity

Note 8: AC Parameters are guaranteed by DC correlated testing. Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90.

Typical Applications
Ripple Binary Counters

Shift Registers

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CD4027BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A

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CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com