EE271 @ Thuy T.

Le

SJSU-EE

EE271
Advanced Digital System Design & Synthesis

Introduction
Lets take 1 lecture for this chapter

Chapter 1: Introduction

Introduction to
Levels of Abstraction in Digital Design Methodology
Dramatic Change in the Way Industry Does Hardware Design Why? Pervasive use of Computer-Aided Design Tools De-emphasis on hand design methods Emphasis on abstract design representations Hardware design begins to look like software design Emergence of Rapid Implementation Circuit Technology Programmable rather than discrete logic Synchronous Designs
Chapter 1: Introduction 2

Chapter 1: Introduction

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Cost vs. Revenue: The Rule of 10

Technology Node
0.35m 0.25m 0.18m 130nm 90nm 65nm 45nm

IC Development Cost
$1-2M $2-6M $5-10M $8-12M $10-20M $15-30M $20-50M

IC Revenues
$10-20M $20-60M $50-100M $80-120M $100-200M $150-300M $200-500M

End-equipment Revenues*
$100-200M $200-600M $0.5-1B $0.8-1.2B $1-2B $1.5-3B $2-5B Source: I.B.S. Inc., 2005
3

Note: * IC products are 10 percent of system value

Chapter 1: Introduction

Moores law in Microprocessors

Transistors on Microprocessors double every 2 years

Web-site: http://www.intel.com/technology/silicon/mooreslaw/index.htm

An IC made in 2002 could hold about 15,000 chips of the logic density from 1981
Chapter 1: Introduction 4

Chapter 1: Introduction

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SJSU-EE

Frequency

Chapter 1: Introduction

Die Size

Chapter 1: Introduction

Chapter 1: Introduction

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Gate Length and Delay Trends

Chapter 1: Introduction

Power will be a major problem

Microprocessors power continues to increase
100000 10000 Power (Watts) 1000 100 10

Courtesy, Intel

18KW 5KW 1.5KW 500W Pentium proc

286 486 8086 386 8085 8080 8008 1 4004

0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year

Power delivery and dissipation will be prohibitive

Chapter 1: Introduction 8

Chapter 1: Introduction

EE271 @ Thuy T. Le

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Increasing Design Challenges (Courtesy, Synopsys)

188M Gates 3.6GHz 85-95W

Variation

125M Gates 3.4GHz 90-105W

Leakage Power

55M Gates 2.2GHz 55-95W 42M Gates 1.4GHz 55-75W

Signal Integrity

7.5M Gates 300MHz 35-45W

Timing Closure

Timing, Area
250nm 180nm 130nm 90nm 65nm 45nm
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Chapter 1: Introduction

Design Challenges
How critical issues and challenges become as process geometries continue to shrink?
*Meeting power budgets (leakage) Managing complexity Signal integrity *Meeting power budgets (active/dynamic) Meeting timing budgets Lengthy design cycles Completing functional verification Meeting cost budgets Design for manufacturability Analog/Mixed-signal blocks Engineering productivity Design for test Tool interoperability IP selection/verification Minimizing die size
25% 25% 22% 33% 32% 52% 50% 49% 47% 44% 44% 40% 60% 58% 57%

* EE Times Survey 2006

2/3 of 90/65nm projects delayed due to power issues*

Chapter 1: Introduction 10

Chapter 1: Introduction

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Top Issues in 65nm Design (Courtesy, Synopsys)

1 Power concerns with timing closure (Multi-Vth, Multi-VDD, Clock Gating ...) 2 Power network design becomes critical (e.g. total rail-to-rail drop is 50mV) 3 Flip chip packaging becoming more common (requiring extensive flow modification) 4 Immature libraries, new IP and advanced design rules 5 Concurrent optimization of area, timing, routing, SI, test, and yield (require full-chip flow) 6 Transition fault testing becomes mandatory Test data volume demands compression Physical verification decks 4X more complex (checks to deal with photolithography of feature size well below exposure wavelength)

Chapter 1: Introduction

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Timing vs. Power vs. Area (Courtesy, Synopsys)

90nm Die Size Gate Delay (ps) Capacitance (fF) Resistance ( ) Interconnect RC Delay (ps) Total Area for Repeater Cells Timing Variability (%) Voltage (V) PowerDyn (W) VTH (V) IOFF (nA/um) PowerDyn Density (W/cm2) PowerLeak Density (W/cm2) Power Density (W/cm2) Power Variability (%) (mm2) 1x 1x 1x 1x 1x 6% 40% 1x 1x 1x 1x 1x 1x 1x 50%
Chapter 1: Introduction

65nm 1x 0.7x 0.7x 2x 2x 15% 45% 0.85x 0.7x .85x 3x 1.4x 2.5x 2x 55%

45nm 1x 0.5x 0.5x 4x 5x 35% 50% 0.7x 0.5x .7x 9x 2x 6.5x 4x 60%
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Chapter 1: Introduction

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Design Scaling
Cost of a function decreases by 2x per generation Technology shrinks by 0.7/generation (average) Integrate 2x more functions per chip per generation
How to design chips with more and more functions?

Chip cost does not increase significantly Design engineering population does not double every two years Need for more efficient design methods Solution: Exploit different levels of abstraction

Chapter 1: Introduction

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Design Abstraction Levels

SYSTEM

MODULE GATE
CIRCUIT

DEVICE G S n+ D n+

Chapter 1: Introduction

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Chapter 1: Introduction

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(from) Behavioral Forms Processor (system) - Executable specification - Program - Algorithms - Flowcharts - Instruction sets - FSM 1. Boolean eq.

(Use) Type of Synthesis System synthesis

(to get) Structural Components - Processors - Controllers - ASICs - Memory - Adders - Comparators - Registers - Counters - Datapaths, etc. - Gates - Flip-flops

Final Physical Objects Printed circuit boards

Register (Module)

Architecture/ behavioral/ high-level synthesis 1. Logic synthesis

Microchips (processors, controllers, ASICs, etc.) Modules/units (adders, comparators, registers, counters, etc.) Analog and digital cells (gates, flipflops, etc.)

Gate

2. FSM Transistor

2. Seq. synthesis - Transistors - Resistors - Capacitors

- Differential Several different equations type of synthesis - Current-voltage techniques diagrams

Chapter 1: Introduction

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Design Metrics

How to evaluate performance of a digital circuit (gate, block, )?

Area (yield and packaging cost) Speed (latency/delay, cycle-time) Power consumption/dissipation Throughput (for pipeline applications) Reliability Scalability

Chapter 1: Introduction

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Chapter 1: Introduction

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Behavioral and Structural Views

Behavioral view is an abstract function
Synthesis Architecture level Synthesis Logic level Gate level Physical Design Physical view

Structural view is an interconnection of parts.

Physical view includes physical objects with size and positions

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Chapter 1: Introduction

HDL Waveforms Waveforms Waveforms Testbench Synthesis netlist Library Logic Optimization netlist

RTL Synthesis Flow

Physical Design Layout

Chapter 1: Introduction

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Chapter 1: Introduction

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The Elements of Modern Design

Design Behaviors Representations Blocks Waveforms Gates Truth Tables Boolean Algebra Switches Simulation, Synthesis CMOS TTL Circuit Technologies
Chapter 1: Introduction 19

Rapid Prototyping Technologies PAL, PLA, PLD

ASIC and General Purpose IC

Application Specific Integrated Circuit (ASIC) Designed to perform a particular operation as opposed to General Purpose integrated circuits Is NOT software programmable to perform a wide variety of different tasks Often has an embedded CPU to manage tasks May be implemented as an FPGA General Purpose Integrated Circuits: Programmable microprocessors (e.g. Intel Pentium Series, Motorola HC-11) Programmable Digital Signal Processors (e.g. TI TMS 320 Series) Memory (DRAM, SRAM, etc.)
Chapter 1: Introduction 20

Chapter 1: Introduction

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Full Custom ASICs Every transistor is designed and drawn by hand (placing transistors, sizing transistors, routing wires) Typically only way to design analog portions of ASICs Gives the highest performance but the longest design time Gate-Array Based ASICs Transistors level masks are fully defined and the designer can not change them The design instead programs the wiring to implement the desired function The designs are slower than cell-based designs but the implementation time is faster (less time in the factory) RTL-based methods and synthesis together with other CAD tools are often used for gate arrays.
Chapter 1: Introduction 21

Programmable Logic Devices (PLDs) Off-the-shelf ICs that can be programmed by the user to perform various functions (usually just combinational logic functions) There are no custom mask layers so final design implementation is a few hours instead of a few weeks Mostly are used for simple functions Field Programmable Gate Arrays (FPGAs) Off-the-shelf chips that the user programs to perform simple functions (but more complex than PLDs)
Capable of capturing 100,000+ designed gates Store logic in look-up table (RAM) with programmable interconnect

High power consumption, high (area) cost per-unit

Chapter 1: Introduction 22

Chapter 1: Introduction

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Standard-Cell-Based/Cell Based IC (CBIC)/Semi-custom Standard Cells (AND gates, OR gates, etc...) are custom designed and then inserted into a library. These cells are wired together using place and route CAD tools Some standard cells such as RAM and ROM cells, and some datapath cells (e.g. a multiplier) are tiled together to create macrocells Custom designed blocks (e.g. microprocessors) might be mixed in a library too (sometimes called megacells or hard macros.) The designs are usually synthesized at RTL level Fabrication (and mostly place and route too) are performed by another company (e.g. VLSI, TSMC, etc.).
Chapter 1: Introduction 23

Summary
ASIC Full-custom Semi-custom Family Analog / digital Cell-based (CBIC) Masked gate array (MGA) Programmable Field-programmable gate array (FPGA) Programmable logic device (PLD) Custom masks All All Some Custom cells Some None None

None

None

None

None

Chapter 1: Introduction

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Chapter 1: Introduction

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Cell Libraries
FPGA has library of logic cells in the form of a design kit (have no choice) MGAs (masked gate array) and CBICs (cell based IC) have three choices: o ASIC vendor (company that build ASIC) o Third-party library vendor o Build your own cell library An ASIC vendor library is normally a phantom library (the cells are empty boxes) Third-party library vendor normally:
Develops a cell library using information about a process supplied by an ASIC foundry Include the masks (tooling) that are used to manufacture the ASIC.
Chapter 1: Introduction 25

An ASIC foundry (in contrast to an ASIC vendor) only provides manufacturing, with no design help Each cell in an ASIC cell library must contain the following information:
o o o o o o o o o

A physical layout A behavioral model A Verilog/VHDL model A detailed timing model A test strategy A circuit schematic A cell icon A wire-load model A routing model

Standard Cell designs are usually synthesized from RTL level of the design
Chapter 1: Introduction 26

Chapter 1: Introduction

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ASIC designers also need a detailed timing model for each cell to determine the performance of the critical pieces of an ASIC. It is too difficult, too time-consuming, and too expensive to build every cell in silicon and measure the cell delays. Instead library engineers simulate the delay of each cell, a process known as characterization. The cell schematic (a netlist description) describes each cell so that the cell designer can perform simulation for complex cells. Detailed cell schematic is not necessary for all cells, but enough information is needed to compare the cell schematic with the layout, this called "layout versus schematic (LVS)" check.
Chapter 1: Introduction 27

If schematic entry is used then cell icon together with connector and naming information are needed for each cell Logic synthesis makes moving an ASIC between different cell libraries much easier. In order to estimate the parasitic capacitance of wires, statistical estimate of the capacitance for a net in a given size circuit block is needed. This usually takes the form of a look-up table known as a wire-load model. Routing model for each cell is necessary but large cells are too complex for the physical design or layout tools to handle directly and so there is the need for simpler representation of the physical layout that still contains all the necessary information. Place and route mostly are performed at fabrication companies (VLSI, TSMC, etc.) or with their assistance
Chapter 1: Introduction 28

Chapter 1: Introduction

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Standard Cell Libraries

Standard

cell libraries are tuned for different performance, power and area goals.

For low-power design the choice and mix of libraries may have a significant impact on power, timing and area
One

key characteristic of a cell library is cell height measured in number of tracks, which is the metal one (M1) pitch

Tall track height libraries support more complex routing with larger drive strength transistors and are tuned for performance (but may have higher leakage). A tall track height library has 11 or 12 tracks Low-track height libraries are optimized for area efficiency with lower drive strength transistors (less appropriate for high-speed). A 7 or 8-track library is considered as low track height library Standard track height libraries are designed to give reasonable tradeoff between area efficiency and performance, and are used in most designs. A standard track height library has 9 or 10 tracks
Chapter 1: Introduction 29

Libraries

can be built with compatible footprints using transistors with different threshold voltages:

High-VT libraries exhibit the lowest leakage power at the cost of lower performance, a good choice for non-timing-critical designs, and for non-critical paths in higher performance designs Low-VT libraries are built with high-speed but leaky transistors. They dissipate higher static and dynamic power as a result. Regular- or Standard-VT libraries sit in between these and offer lower performance than the Low-VT transistor versions at reduced leakage and dynamic power
Libraries

can also be further optimized for low static power:

Long channel-length gates can be used to reduce leakage, at some cost in terms of timing and area The stack-effect of series transistors inside gates can be exploited to reduce source-drain leakage across the other transistors for more complex gate structures
Chapter 1: Introduction 30

Chapter 1: Introduction

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Characterization of Standard Cell Libraries

Standard

cells were characterized at a number of process, voltage, and temperature conditions Several copies of the timing models are available: a worst case (slow process, low voltage, high temperature), best case (fast process, high voltage, low temperature) and typical
Worst case timing is used for checking setup times Best case timing is for checking hold times
Characterization

is more challenging for 90nm technology (and below) and for aggressive low power design

At 90nm and below, wires can be more resistive such that network impedance can be higher than the output impedance of driving gate
With

multi-voltage, voltage scaling, and power gating designs, the supply voltage may vary significantly from gate to gate or module to module new library models are needed
Chapter 1: Introduction 31

Temperature Inversion
Larger

saturation current leads to smaller the gate delay

1. Saturation current increases linearly with carrier mobility and quadratically with voltage headroom (VDD VT) 2. Increasing temperature will decrease mobility and increase voltage headroom (since VT drops at higher temperature)
Older

processes: Gate delay always increases with increasing temperature (#2 dominates)

The effect of temperature on mobility dominates due to a large voltage headroom (VDD VT).
90nm

and below: Gate delay decreases with increasing temperature under low VDD or slow signal transitions. This is known as temperature inversion (#1 dominates)

The effect of temperature on voltage headroom dominate the change in mobility (VDD becomes small more sensitive to VT than mobility)
Chapter 1: Introduction 32

Chapter 1: Introduction

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Combinational vs. Sequential Logic

Combinational logic No feedback among inputs and outputs Outputs are a pure function of the inputs
X1 X2 Xn

Circuit

Z1 Z2 Zm

X1 X2 Xn

Circuit

Z1 Z2 Zm

The presence of feedback distinguishes between sequential and combinational circuits.

Chapter 1: Introduction

33

Sequential logic Outputs depend on inputs and the entire history of execution! Network typically has only a limited number of unique configurations, these are called states Need storage elements to remember the current state Output and new state is a function of the inputs and the old states, i.e., the fed back inputs are the states! Synchronous systems: Period reference signal, the clock, causes the storage elements to accept new values and to change state. Asynchronous systems: No single indication of when to change state
Chapter 1: Introduction 34

Chapter 1: Introduction

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Computer-Aid: Simulations
Program which dynamically executes an abstract design description Obtain verification of functional correctness and some timing information before the design is physically constructed Easier to probe and debug a simulation than an implemented design Simulation cannot guarantee that a design will work Only as good as the test cases attempted Does not check electrical errors Abstracts away some of the realities of a real system

Chapter 1: Introduction

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Two Forms of Simulations

Logic Simulation Design described in terms of logic gates Values are 0, 1 (plus others to be introduced) Good for truth table verification Timing Simulation Dynamic Timing Analysis Waveform inputs and outputs Model of gate delays Are the waveform shapes what was expected? Identification of performance bottlenecks
Chapter 1: Introduction 36

Chapter 1: Introduction

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Gate-Level (logic-level) Simulation Simulation driver (input vectors)

Verifies

Netlist (circuit)

Simulation monitor (Waveforms)

Advantages of gate-level simulation: timing and functionality simultaneously well understood by designers
Approach

Disadvantages of gate-level simulation

Computationally

intensive - only 1 - 10 clock cycles of 100K gate design per 1 CPU second - results only as good as your vector set - easy to overlook incorrect timing/behavior
Chapter 1: Introduction 37

Incomplete

Types of Logic Simulators

Logic Simulators

HDL-based

Emulator-based

Schematic-based

Event-driven

Cycle-based

Gate

System

Emulators:

Design is mapped into FPGA hardware for prototype simulation. Used to perform hardware/software co-simulation.
Chapter 1: Introduction 38

Chapter 1: Introduction

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Schematic-based:

Design is entered graphically using a

schematic editor Event-driven (gate/RTL/behavioral) simulations

Verilog: VCS, Silos, NC-Verilog, Turbo-Verilog, etc. VHDL: VSS, MTI, Leapfrog
Cycle-based

(gate/RTL/behavioral) simulations

Since most digital designs are largely synchronous, state elements change value on active edge of clock So only boundary nodes are evaluated and internal nodes are ignored Verilog: Frontline, Speedsim VHDL: Cyclone

Circuit-level Simulations: Software such as Spice, Advice, etc.

Chapter 1: Introduction

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Optimization Trade-off
Combinational Circuits
Area max

Multi-criteria

optimization Multiple objectives.

max

Delay

Chapter 1: Introduction

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Chapter 1: Introduction

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Area max Area max Area max

Sequential Circuits

max max max Delay Delay

Delay

Chapter 1: Introduction

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Chapter 1: Introduction

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