Unipolar Devices III: GaN Electronic Devices

Tutorial in the frame of the TARGET network Joachim Wrfl Ferdinand-Braun-Institut fr Hchstfrequenztechnik Gustav-Kirchhoff-Strae 4 12489 Berlin Participating institutions: Fraunhofer Institut fr angewandte Festkrperphysik, Freiburg, Germany Technical University Vienna, Austria AMS, Rome, Italy

...Translating ideas into innovation

IAF

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Angewandte Festkrperphysik

Outline
GaN electronic devices An introduction Device fabrication Understanding device operation Design of high power microwave GaN devices Future GaN devices Conclusions Comparison to other device families Applications Principles of operation Epitaxy Processing Performance limitations and how to get rid of it Reliability Field plate devices Power bar designs State of the art results Novel epitaxial approaches GaN HBTs

GaN electronic devices An introduction

Semiconductor microwave power devices

1000
maximale Leistung (Watt) Maximum power (W)

Si
100

LD

S iC

MO

Ga

10

Ga

As

HF

HB

ET

T,

HE

M T In P

HB

T,

HE

0,1 0,1 1 10
Frequency (GHz) Frequenz (GHz)

MT
1000

100

Device classes and frequency vs. maximum possible microwave power

Comparison of semiconductor materials

Si Band Gap (eV) Electron mobility (cm/Vs) Electric breakdown field (106 V/cm) Saturation velocity (107 cm/s) Thermal conductivity (W/Kcm) Johnsons Figure of Merit (~VBr x vsat) Maximum estimated operation temperature (C) 1 200 7 300 180 500 260 500 760 500 0.3 1.0 1.5 0.4 2.0 0.46 2.0 2.0 4.9 2.4 2.0 4.9 3.3 2.7 1.3 1.1 ind. 1500 GaAs 1.43 dir. 8500 4H-SiC 3.26 ind. 1000 6H SiC 3.0 ind. 500 GaN/ AlGaN 3.42 dir. 1250*

* 2DEG mobility up to 2000 cm/Vs

Applications
L
ow

no

am is e

p lifie r
s peed com m u ni ca tio fmax n
fT

High

il la t

or

RF noise

O sc

GaAs - HEMT GaAs - HBT Si - BJT GaN - HEMT

te a Ga

AD C

1/f noise

rra y

gm

AS I C

Distortion

V T

Ai r c

ier

f p li

ole d

am r

SI

Breakdown Voltage

Pdiss Power Handling

H ig h po w

GaN high power devices: Applications

Demands from system applications GaN devices for Enabling microwave components
High power microwave amplifier (HPA) Highly linear amplifiers Robust low noise amplifiers (LNA) Power switches

More demanding requirements regarding:

Linearity Output power Efficiency Heat sinking Total system noise factor

Civil applications
Base stations for mobile communications Satellite communication

Military applications
Phased array radar systems

To be expected in future: Realization in GaN technology

Advantages of GaN-HFETs in power amplifiers

conventional technology GaN technology

T
input

T T T T

T T T T

T
output input

output

Higher operation voltage leads to:

Higher power densities Higher impedance level Higher linearity Less complex transformation and power combining networks

Less complex circuit design

Small chip areas Higher reliability

III-Nitride hetero structures for microwave power transistors

Bandgap-Engineering Realization of HEMTs Spontaneous and piezoelectric polarization Advantages: Reduced CoulombScattering in 2DEG Higher mobility Higher carrier concentration in 2DEG

R.J.. Trew, MTT-S 2004

High Electron Mobility Transistors (HEMT): How does it work?

Source AlGaAs GaAs spacer AlGaAs GaAs
Distribution of 2DEG carriers

Gate

Drain

Example: GaAs/AlGaAs HEMTs

Electrons from AlGaAs drift to AlGaAs/GaAs interface There: Formation of 2DEG Extremely high electron mobility along interface 2DEG concentration controllable by Gate electrode

2-DEG

Speciality: GaN/AlGaN HEMT

Parameters controlling 2DEG concentration: -Doping of AlGaN barrier -Spontaneous polarization Additional -Piezoelectric polarization features

Spontaneous and piezoelectric polarization

Relaxed Compressive strain

Substrate

Substrate

Mechanism of spontaneous polarization

Charge distribution of valence electrons (e/) Resulting polarization

Ionic character of Ga-N compound

Deviation from ideal c/a ratio

Spontaneous polarization

c/a-ratio and spontaneous polarization

Spont. polarization (C/m)

c/a ratio

c/a ratio always smaller as in ideal case Spontaneous polarization increases in the order GaN, InN, AlGaN Relevant for high power GaN microwave transistors: Difference between GaN and AlGaN

Principles of 2DEG formation in AlGaN/GaN structures

AlxGa1-xN 2DEG Ppiezo EF P0 GaN Gauss theorem: -total = . (Ppiezo + P0) positive polarization-induced charge total to compensate total polarization doping 2DEG accumulation P0= P0(GaN)- P0(AlGaN) differential spontaneous polarization at the junction Ppiezo tensile strain in the AlGaN lattice-matched to GaN

no intentional doping necessary

2DEG formation in AlGaN/GaN HFET-structures

[0001]

[0001]

GaN AlGaN

PSP PSP PSP PPE

EF

EC

PSP PSP PPE

2DEG

2DEG

PSP

GaN

N Ga O Al

+ -

EF
Ga N O Al

EC

Saphir

Ga-face polarity

N-face polarity

Device fabrication

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Epitaxy on non-lattice matched substrates (1)

Possible substrate solutions for GaN FETs:
Sapphire Lattice mismatch (%) Availability / Price (2, $) Thermal Conductivity (W/cmK) 13 100 0.3 n-type SiC 3.1 500 4 s.i. SiC 3.1 3000 4 0 not available 1.3 17 GaN bulk Si

Angewandte Festkrperphysik

100 1.48

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Epitaxy on non-lattice matched substrates (2)

Analysis of dislocations and epitaxial quality
dislocations

Angewandte Festkrperphysik

TEM image PEC: photo enhanced etching Dislocations are etched slower than defect free areas Dislocation rich area up to a thickness of 500 nm
Non-lattice matched substrate (sapphire)

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Epitaxy on non-lattice matched substrates (3)

Metal Organic Chemical Vapour Deposition (MOCVD) Molecular Beam Epitaxy (MBE)

Angewandte Festkrperphysik

Both types deliver similar epitaxial quality MOCVD: Faster growth Mass production MBE: More options for polarity of interfaces

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Impact of epitaxy on polar heterodevices

Material composition x: Increasing ns while preserving mobility No/little doping required Source Gate Drain
Mobility (cm / Vs)
Sheet Carrier Concentration (1E13 cm )
-2

Angewandte Festkrperphysik

1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 25 30 Al content (%) 35

AlxGa1-xN Si-doping AlxGa1-xN GaN 2-DEG

1600 1400 1200 1000 800 600 400 200 0

HEMT on Sapphire Al=25% Al=30% Al=35%

0.4 0.6 0.8 1.0 1.2 1.4 1.6 -2 Sheet Carrier Concentration (1E13 cm )

Technology of AlGaN/GaN HFETs (1)

Ti-reflector layer on transparent wafer
Structuring of reflector layer Definition of alignment marks S D

Deposition of Source-/Drain contacts (Ti/Al/Ti/Au/WSiN)

Removal of reflector layer Annealing at 850C in N2

On chip isolation:
Dry etching of active layers RIE-process, BCl3:Cl2:Ar

Technology of AlGaN/GaN HFETs (2)

S G D Gate-Technology (Pt-Au):
Electron beam lithography: Gate length 0.3 m

S G

Passivation and dry etching of contact windows 1st interconnect (Ti-Pt-Au, 500nm)

Dielectric passivation

MIM-capacitor Resistor

Passive components: MIM-capacitor NiCr-resistor Electroplated Au air bridge (6 m)

Technology of Power Cells

WSiNx-Diffusionbarrier encapsulats ohmic contact

Power cell with common Source Design (connected by airbridge)

Backend Processing

Wafer thinning

Via etching and metalization Chip dicing

Backend Processing (1)

Thinning of SiC-Substrate to 100 m
Lapping with different diamond pastes Polishing

Via technology
Dry chemical via process Laser micro-machining

Via metallization
Plating base: Ti/Au 30/1000 nm

Electroplating

Backend Processing (2)

Definition of dicing streets

Lithography and etching Laser micro-machining

Wafer dicing
Sawing and cleaving

Chip delivery:
Diced chips on dicing frame

L-Band Powerbars based on laser-vias

Full wafer thickness (Wafer not thinned) Via-diameter 90 m Technological specialty Through-Vias

Chip Dicing

Laser scribe lines

Dicing street

Laser induced removal of Au in dicing streets (focus on backside)

Dicing street after wafer sawing and cleaning (focus on front side)

GaN-HFETs: Power devices on transparent wafers

16x250 m power cells

dB MSG

40 30 20 10 0 0,1 1 f (GHz) 10 100

60

Pout
G
PAE
ID Pmax=12.3W

0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0

Po(dBm); G(dB); PAE (%)

50 40 30 20 10 0 -10

Device data at 2 GHz:

Pmax = 12.3 W PAE = 59% Linear gain: 19 dB Gain at Pmax: 16 dB

10 Pin (dBm)

20

30

ID (A)

Understanding device operation

DC-characteristics
Device:
ID (A)

0.12

0.1

GaN-HFET 2x50 m, Lg = 0.3 m

0.12

0.08

0.06

0.04

0.1

0.02

0.08

0 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2

ID (A)

0.06

VGS (V)

0.04

Typical GaN-HFET I/Vcharacteristics:

IDSS_max = 1.1 A/mm gm = 220 mS/mm Slight hysteresis in output characteristics

0.02

0 0 5 10 15 20 25 30

VDS (V)

Compression of drain current: Gate lag conditions

140 120 100
Vgs= 0.0 V, Vds= 0.0 V Vgs= -3.0 V, Vds= 0.0 V

140 120 100

Vgs= 0.0 V, Vds= 0.0 V Vgs= -3.0 V, Vds= 0.0 V

Ids(mA)

60 40 20 0 0 5 10 15 20 25 30

Ids(mA)

80

80 60 40 20 0 0 5 10 15 20 25 30

Vds(V)

Vds(V)

Biasing point for pulse measurements: VGS = -3 V, (pinch off); VDS = 0 V

Before passivation:
Drain current reduction

After passivation
Slight recovery of drain current

Reduction of power dispersion (3)

5. Field plate structures
Suppressing surface/interface traps Field plate flattens electric field distribution
High electric field Trapped electrons form virtual gate G D Electric field maximum reduced Modulation of carriers due to F.P

AlGaN +++++++++++++++++++ GaN

D AlGaN ++++++++++++++++++ GaN

Without field plate

With field plate

Compression of drain current: Drain lag conditions

140 120 100

Vgs= -3.0 V, Vds= 0.0 V

140 120 100

Vgs= -3.0 V, Vds= 0.0 V

Vgs= -3.0 V, Vds= 26.0 V

Vgs= -3.0 V, Vds= 26.0 V

Ids(mA)

60 40 20 0 0 5 10 15 20 25 30

Ids(mA)

80

80 60 40 20 0 0 5 10 15 20 25 30

Vds(V)

Vds(V)

Biasing point for pulse measurements: VGS = -3 V, (pinch off); VDS = 26 V Before passivation: Very pronounced drain lag After passivation:
Strong recovery of drain lag

Maximum obtainable output power IDS

Imax
VGS=0

I gm VGS
VGS=VP

VP

VK Ohmic

VDD Saturation

VDSmax

VDS

Breakdown Optimum output impedance for max. output amplitude given by: Voltage knee VK Breakdown onset Saturation current

Ropt= (VDSmax VK ) / Imax Pmax= 1/2 (VDSmax VK ) Imax

If current compression: Strong reduction of maximum obtainable output power IDS

Imax
Not accessible I VGS VK Ohmic Saturation VDSmax VDS

gm

VP

Breakdown Maximum power swing reduced by: Surface traps Buffer layer traps

Therefore: Current compression has to reduced by any means

Dependency of output power density on current compression

120 100 80

Static Dynamic

0 0 0 0 0 0 0

Static Dynamic

0 0 0 0 0 0 0 30 0

Static Dynamic

Ids(mA)

60 40 20 0

10

15

20

25

30

10

15

20

25

10

15

20

25

30

V ds(V)

V ds(V)

Vds(V)

Pout = 5.2 W/mm

Pout = 3.9 W/mm

Pout = 1.8 W/mm

RF-power performance
Transistor geometry: 2x50 m Frequency: 2 GHz

Physical background of current compression

Main cause of current compression
Electron/hole traps due to surface/interface states & material defects

Location of traps
AlGaN surface / interface AlGaN layer GaN buffer Interface substrate / buffer (I) (II) (III) (IV)

S (I)

G (I) AlGaN GaN IV Substrate (II) (III)

Causes of trap formation

Impurity addition during growth Threading dislocation due to lattice mismatch & defects Excess of carrier gasses & uncontrolled growth parameters Increasing Al mole fraction and AlGaN relaxation Surface exposure & damage during device processing

Current compression: An analogue from every days world

A parallelism could be made for a choked tap, that cannot modulate the flowing liquid (the Drain current) because of a throttling (the virtual Gate due to the charged traps) in the tube (the channel) before and/or after it.

Gate lag
Experimental observation
70 60 50

Explanation
Open channel: Vds = 0.0 V ; Vgs = 0.0 V
S G
AlGaN GaN

Ids(mA)

++++++++++++++++++++++++++++

40 30 20 10 0 0 5 10 15 20

Depleted channel: Vds = 0.0 V ; Vgs = -7.0 V

V d s (V )

Pulsing the gate: are trapped in surface states, negative charging.

Traps S G
AlGaN

Bias points:

Vds = 0.0 V; Vgs = 0.0 V Vds = 0.0 V; Vgs = -7.0 V

++++++++++++++++++++++++++++
GaN

Drain lag
Experimental observation
70 60 50

Explanation
Depleted channel: Vds = 0.0 V ; Vgs = -7.0 V
Traps S G
AlGaN

Ids(mA)

40 30 20 10 0 0 5 10 15 20

++++++++++++++++++++++++++++
GaN

More Depleted channel: Vds = 20.0 V ; Vgs = -7.0 V Pulsing the drain: are also trapped in buffer traps due to high Vds.
S G
AlGaN

V d s (V )

Bias points:

Vds = 0.0 V; Vgs = -7.0 V Vds = 20.0 V; Vgs = -7.0 V

++++++++++++++++++++++++++++

Traps

Reduction of power dispersion (1)

1. Surface passivation 2. n- type GaN cap Mechanism:
Neutralizing surface / interface traps by n+-donors (n-doped GaN cap) & shallow donors (SiNx ) Therefore: No virtual gate formation
Trapped electrons form virtual gate
G
AlGaN

Removal of virtual gate due to SiNx

AlGaN

Removal of virtual gate due to n-doped cap

G D

G
AlGaN

+++++++++++++++++++
GaN

+++++++++++++++++++
GaN

+++++++++++++++++++
GaN

Reduction of power dispersion (2)

3. Recessed gate process 4. Light stimulation
Suppression of surface/interface traps No effective charging of surface states and therefore removal of virtual gate De-trapping of carriers
Trapped electrons form virtual gate G D G AlGaN +++++++++++++++++++ GaN
Ev

No trapping of electrons leaking from the gate D

Ec Electron h

AlGaN +++++++++++++++++++ GaN

Traps
hole

Design and realization of high power microwave GaN devices

Field plates: Output power increase

Field plate
8,0 7,5 7,0 6,5
A2: G-D=2m A6: G-D=6m A6L: G-D=6m, FP=1m A6M: G-D=6m, FP=2m A6N: G-D=6m, FP=3m

Psat [W/mm]

6,0 5,5 5,0 4,5 4,0 3,5 3,0 24 26

FP

30

36

42

48

54

60

Field plate connected to gate at gate pad

Vds [V]

GaN 707-4 (Wg=2*125m)

Power density vs. bias voltage Systematically higher output power level Power density can be increased by 100%

Field plates: Trade-offs

24 22 20

MSG [dB]

18 16 14 12 10 24 26 30 36 42
GaN 707-4 (Wg=2*125m) A2: G-D=2m A6: G-D=6m A6L: G-D=6m, FP=1m A6M: G-D=6m, FP=2m A6N: G-D=6m, FP=3m

Reduced gain (MSG) due to field plate. Increase of - Base/collector capacitance - Effective gate length Trade-off between maximum achievable power level and speed

Vds [V]

Maximum stable gain (MSG) vs. bias voltage

High power transistors: Power bar structures

S G S S G S S G S S G S S G S S D S S D S S D S S D S S D S

Bonding areas according to device current and mounting requirements Sub-cells separated on chip - Avoid odd mode oscillations - On chip measurability Inter sub-cell connection by power bar bonding

Thermal management
Flip chip technology:
Flip chip bonding of GaN HEMT discrete devices on AlN substrates could be used to improve devices thermal management. It can be be also used as an alternative solution to via holes for MMIC ground connection. AlN Carrier Substrate Au/Sn bumps GaN Chip

Breakdown in GaN HEMTs

S G +
breakdowns

D AlGaN GaN

S-D breakdown
Complex avalanche-injection process - Highly resistive buffer layer needed !

G-D breakdown
Through the surface Impact ionisation in the channel Schottky barrier breakdown

+ EF

Literature Reduction of break down:

Vaschenko et.al.; Microelectron. Reliab. 37 (1997), 1137-1141 Kuzmik et.al.; Appl. Phys. Letters 83 (2003), 4655-4657) Nakano et.al; phys. stat. sol. (c) 0 (2003) 2335 Dayakonova et.al; Appl. Phys. Lett. 72 (1998) 2562

Highly resistive buffer Dislocation-free surface field plate (eliminates impact ionisation in the channel)

GaN-Amplifier Module
45 40 Pout (dBm) 35 30 25 20 0 5 10 15
28VD , 1A , 1.87GHz
N0713-1 5x8X250 _16R10_4S3

22.4 W

50 PAE (%), Gain (dB) 40

Pout PAE Gain

30 20 10 0 35

20

25

30

Pin (dBm)

Single stage amplifier In- and output matching 10 mm Gate width 43,5dBm (22.4 W) @ 1.87GHz

Power bar devices: Performance

45 45 40 35 30 40
Gain
Output Power
PAE

Gain (dB) /Output Power (dBm)

35

PAE (%)

30

25 20 15

25

2 GHz test fixture

20 10 15 5 0 0 5 10 15 20 25 30 35

10

Input Power (dBm)

Device in test fixture Pmax = 32 W PAE = 42% Linear gain: 17 dB Gain at Pmax: 15 dB

Bench marking of GaN power devices

1000
Fujitsu NEC

Europe

World wide

P (W) bzw. P/WG (W/mm)

100
FBH Cree DC

10

FBH

IAF

Cree

IAF

TRW Triquint

0,1

10 Frequenz (GHz)

100

Future GaN devices

New structures for high-power performance

7

Energy gap at 300 K (eV)

6 5 4 3 2 3,1

AlN In0.17Al0.83N
AlGaN InAlN

Goals:
Better carrier confinement in 2DEG Increase 2 DEG concentration

Conventional approach: Increase of Al mole-fraction in AlGaN

InN
Increase of strain in AlGaN Increase of spontaneous polarization Increase of 2DEG density

GaN

InGaN

3,2

3,3

3,4

3,5

3,6

Lattice constant, at 300 K (Angstrom)

Problem:
Relaxation of the AlGaN layer

Therefore: InAlN/(In)GaN QW new approach

New structures for high-power performance

InxAl1-xN (lattice matched, x= 0.17, or tensile strain) GaN 2DEG Ppiezo EF DP0 DP Ppiezo 0 InyGa1-yN (lattice matched (y= 0) or compressive strain)

P0 (Ccm-2) Al0.2Ga0.8N/GaN (conventional) In0.17Al0.83N/GaN In0.17Al0.83N/ In0.10Ga0.90N -1.04 x 10-6 -4.37 x 10-6 -4.34 x 10-6

Ppiezo (Ccm-2) -6.9 x 10-7 0 1.6 x 10-6

ntotal (cm-2) 1.08 x 1013 2.73 x 1013 3.71 x 1013

EC (eV) 0.3 (0.75Eg) 0.68 >0.68

New structures for high-power performance

Advantages
Very high 2 DEG density expected ( strain high power HEMTs), controlled

Disadvantages
InAlN growth is difficult

Literature
J. Kuzmik; IEEE El.Dev.Letters 22, 510-512 (2001) M. Higashiwaki; Jap. J. Applied Physics 43, L768-770 (2004)

MOS GaN HEMT

Advantages of MOS/MIS-Structures:
Low gate leakage reduced current collapse lower noise positive sweep on gate (higher power, normally off device possible)

Requirements on dielectric layers:

High electrical strength, no bulk traps Good insulation, Low interface state density

Literature:
Khan et.al.; IEEE Trans. On Microw. Th. and Tech.51 (2003) 624-633. Khan et.al.; phys. stat. sol. (a) 200 (2003) 155. Adivarahan et.al.; IEEE Electron Dev. Lett. 24 (2003) 541

GaN-HBT: Main advantages

Property Eg (eV) vsat (cm/s) Ecrit (MV/cm) (W/cmK) GaN 3.4 3x107 3.3 1.3 4H-SiC 3.3 2x107 2.0 4.9 GaAs 1.4 2x107 0.4 0.5 Si 1.1 0.6x107 0.3 1.5

GaN wide-band-gap-material (Eg) as collector layer:

High RF-power High operating voltage Operation at high temperatures (300 - 500C)

GaN HBTs: Extremely high power at high frequency

Advantages of GaN:
Highest saturation velocity vsat gives lowest transit time Highest breakdown field Ecrit allows highest bias voltage Good thermal conductivity (SiC better!)

GaN-HBT: Comparison with GaAs-HBT [2,3]

Breakdown voltage (V) Structure: GaN-HBT
50 nm base 100 nm collector

Current gain cut-off frequency fT

Power gain cut-off frequency fmax

15 1000 70

200 6 20

200 300 ~100

GaN-HBT
200 nm base 7000 nm collector

GaAs-HBT
100 nm base 3000 nm collector

Superior RF-power performance expected for GaN-HBTs!

GaN-HBT: Main world-wide activities

Research group: J. Pankove Astralux Inc., USA [4,5] U.K. Mishra, et.al., UCSB USA [2,6,7,8] T. Makimoto, et.al., NTT Japan [9,10] S. Estrada, et.al., UCSB USA [11] Structure: emtter/base/ collector n-GaN/p-SiC/ n-SiC n-AlGaN/p-GaN/ n-GaN n-GaN/p-InGaN/ n-GaN n-AlGaAs/ p-GaAs/n-GaN ~ 0.2 - 0.5 (RT) ~ 20 - 2000 (RT) Current gain at room or higher temperature ~10000000 (RT) ~100 (535C) ~ 3 - 35 (RT) Remarks, drawbacks
Differential current gain due to high leakage SiC-purity issue first GaN-HBT in 1998 base doping issue processing issues double hetorojunction base regrowth optimized 4 W DC-power obtained GaAs-GaN-heterointerface by wafer fusion (1 h at 750C and 2 Mpa)

GaN-HBT: Technological challenges (a few)

Highly p-doped and high quality p-GaN base not yet available:
shallowest acceptor Mg is a deep acceptor (EA-EV~110-200 meV) low activation at RT: NA~5x1019 cm-3 gives p~8x1017 cm-3 (2 % activation!) high base sheet resistance: 100 k/ for 100 nm base (200 / for GaAs) Mg-dopant memory effect during growth and out-diffusion of Mg into emitter high density of point defects in the base leads to low minority lifetime and thus low current gain

Lack of GaN-substrates: heteroepitaxy on sapphire or SiC

large lattice mismatch leads to high dislocation density in grown layers threading dislocations identified as source of collector-emitter leakage current GaN templates or LEO/ELO growth as possible improvements

GaN-emitter definition:
Cl2 RIE is primarily physical etching causing damage to extrinsic base high contact resistance on RIE etched base leads to high offset voltage (~10 V) selective extrinsic base regrowth as possible solution or selective area emitter growth using AlN or SiN mask

AlGaN/GaN-HBT: Towards an RF device

Development of the UCSB AlGaN/GaN-HBT device:

Offset voltage reduced from >10 V to 1-5 V by using regrown extrinsic base Current gain increased from 3 to 10 due to improvement in dislocation density (LEO substrate) Main issues: current leakage due to threading dislocations and low minority carrier lifetime in the base Current gain cut-off frequency of 2 GHz reported

GaN/InGaN-DHBT: Better epi gives a better device

Improvements of the NTT GaN/InGaN-HBT device:

p-InGaN: 10% base dopant activation (NA~2x1019 cm-3 gives p~2x1018 cm-3) Offset voltage reduced from 5 V to 1 V due to improved base contacts (optimized regrown extrinsic base): high current gain > 2000 obtained Output characteristics indicates electron blocking "spike" at base-collector junction Current limitation due to Kirk-effect at 7 kA/cm2 (70 kA/cm2 for GaAs-HBT [13]) 50x30 m2 DHBT operating up to 50 V gives 4 W of DC-power corresponding to DC power density of 270 kW/cm2 (375 kW/cm2 for GaAs-HBT [13])

GaN/SiC-HBT: Pankoves approach

Cross section of the GaN/SiC transistor

Common-base I-V-characteristics

Pankoves (Astralux, Univ. of Colorado, USA) GaN/SiC-HBT device:

LPE grown SiC base and MBE grown GaN emitter 100,000 of differential current gain obtained from common base characteristics Poor RIE etch selectivity GaN-to-SiC causing high leakage current at VCB> 10V Improvement with selectively grown GaN emitter: current gain of 1,000,000 at RT and 100 at 535C reported Not reproduced due to parasitic deep level defects in p-type 6H-SiC Work in progress using purer 4H-SiC (~15@ RT) but lack of production quantities

AlGaAs/GaAs/GaN-HBT: Fused-wafer approach

Development of the UCSB fused-HBT device:

Joining the best of two worlds: high quality and highly doped p-GaAs base with high breakdown voltage of n-GaN collector AlGaAs/GaAs fused with GaN: 1 h at 750C in N2 under 2 MPa pressure giving mechanically stable junction with good structural quality (<1 nm disordered layer) Good fused GaAs-GaN diode: n~2.5 and ~ 50V breakdown voltage Degradation of AlGaAs/GaAs junction during high temperature fusion and electronic traps at fused interface cause current gains < 1 Future: fusion at < 500C and shifting fused interface into collector

GaN-HBT: Perspectives
Show-stoppers: a number of outstanding material and processing issues
Base layer: large acceptor ionization energies and low hole mobilities Growth of GaN layers: still a high defect density Base ohmic contacts: high resistance causes high offset voltage Emitter definition: etching damage or base regrowth to be further optimized

Possible solutions:
Improved substrates for GaN growth like HVPE-grown GaN templates Further optimization of base layer regrowth Direct wafer bonding (wafer-fusion): structural improvement

References GaN-HBTs
[1] S.J. Pearton et.al., Mater. Sci. Eng. 250 (2000) 1-158 [2] L.S. McCarthy et.al., Trans. Electron Dev. 48 (2001) 543-551 [3] P. Kurpas et.al., Technical Digest IEDM 2002 (2002) 682-684 [4] http://www.mdatechnology.net/ (Tech Search, Spinoff Technology: #321) [5] L.S. McCarthy et.al., Electron Dev. Lett. 20 (1999) 277-279 [6] H. Xing et.al., J. Phys.: Condens. Matter. 13 (2001) 7139-7157 [7] T. Makimoto et.al., Proc. Int. Workshop on Nitride Semic. 2000 (2000) 969-972 [8] http://www2.electrochem.org/cgi-bin/ abs?mtg=206&abs=1255&type=pdf [9] S. Estrada et.al., Appl. Phys. Lett. 82 (2003) 820-822

Conclusions

Conclusions (1)
Material and manufacturing Material continuously improves
High mobility structures Reduced power compression High voltage capability GaN on Si substrates

Established device processes available

Special process modules for suppression of power dispersion Via and backside technology Developments towards higher bias voltages

Transition to larger wafers 2 Device results

3, 4

Promising results from S- to Q-Band

Power cells and power bars up to 250 W (L-Band) GaN MMICs Low noise applications

Conclusions (2)
Present Challenges Still a problem: Power dispersion
Adapted technological solutions

High voltage operation Reliability issues unsolved

Required: >106 h at 125 C and 48 V

Future perspectives

Further optimization of conventional approaches New technologies on the horizon:

GaN-MOS devices GaN HBTs