COMBINATION LOGIC CIRCUIT LAB JOURNAL

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Combination Logic Circuit Lab Journal Digital Electronics (EEE 1313) Raefi Azrani Bin Ropee Adman 1006q78842 Mr. Lee Sem 1/SEP intake 2011

COMBINATION LOGIC CIRCUIT LAB JOURNAL

TABLE CONTENT No. 1 2 3 4 5 6 Executive Summary Introduction: Methodology Procedure Learning Outcome Conclusion CONTENTS PAGE 3 4 5 6-15 15 15

COMBINATION LOGIC CIRCUIT LAB JOURNAL

Executive Summary This journal is mainly aiming to discuss about the designing a combinational logic circuit for the Output Logic Block that get input of 3-Bit Asynchronous Up counter which counts in specific order. The sequence is 3>0>1>6>7>4>5>2. It is a continues repeated sequence which mean it will repeated again after the last number. Generally, the combination of logic circuit using a D flip-flop and NAND gates The method that is use are: i. ii. iii. iv. Expressing the sequence in binary form Expressing sequence in Boolean equation Use Karnaugh Map (K map) to simplified Use NAND gates as a universal gate

COMBINATION LOGIC CIRCUIT LAB JOURNAL

Introduction: The objectives of the report are: 1. To design, build and test a 3-bit Asynchronous Counter that counts in a specific order by using the D flip-flops and NAND gates. 2. To construct and troubleshoot a 3-bit Asynchronous Up Counter.

This journal is about designing the combination of digital circuit that count in specific sequence. Each individual has been assigned with different order. For this report the order is 3>0>1>6>7>4>5>2.

List of tool and parts Hardware Tools: 1. DC Power Supply 2. Wire Stripper/Cutter 3. Component bender (pliers) No. 1 2 3 4 5 6 Part Light Emitting Diodes, LEDs Resistors:10k,1/4 W Resistors:560,1/4 W IC:74HC00,4 units of 2-input NAND gate IC:74HC10,3 units of 3-input NAND gate IC:74HC74,2 units of D Flip-Flop gate Quantity 7 2 7 1 1 2

COMBINATION LOGIC CIRCUIT LAB JOURNAL

Methodology The method of designing the circuit is as follow: 1. Generate the truth table for Out-2,Out-1 and Out-0 by building a clock generator 2. Derive the Boolean equation for Out-2,Out-1 and Out-0 3. Plot Karnoughs map to simplified the Boolean equation 4. Draw the schematic diagram of logic implementation of the Boolean equation for Out2,Out-1 and Out-0 5. Convert the logic implementation of Out-2,Out-1 and Out-0 into all NAND gate

Flow diagram of the entire circuit

Bit-0

Clock Generator

CLOCK

3-bit Asynchronous up Counter

Bit-1 Bit-2

Output Logic Block

OUT-0

OUT-2 OUT-1

Procedure

DIAGRAM 1: Block Diagram of the `Out-of-Sequence Asynchronous

Counter

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Procedure
V2 5V
10 ~2PR 12 2D 2Q 9 12 2D

V3 5V U2B
10 ~2PR 2Q 9

V4 5V U1B
2 1D 4 ~1PR 1Q 5

4 ~1PR 2 1D 1Q

U1A
5

U2A

1CLK

~1Q

11

2CLK

~2Q

11

2CLK

~2Q

1CLK

~1Q

~1CLR 1

~2CLR

~2CLR

~1CLR

74HC74N_6V Bit-0

13

74HC74N_6V

13

74HC74N_6V

74HC74N_6V

BIt-1

Bit-2

R1 10k

R2 10k R6 560 R3 560 X1 LED R4 560 X2 LED

V1 5V X4 LED J1 Key = A J2 Key = A

R5 560 X3 LED

Diagram 2: Clock Generator and 3-Bit bit Asynchronous Up Counter

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1. Diagram 2 shows the design for the clock generator with 3-bit Asynchronous Up Counter. 2. All the integrated circuits are connected to the 5V power supply. 3. Attach the LED with a 560 resistor to the Q and Q output of the D-flip flop once the clock generator is wired up. 4. The LEDs should alternately light up every time the wire from the ground is touch one of the 10k resistor. 5. The LEDs determined whether the circuit is functional or not by lightning up accordingly to the binary sequence from 000 to 111 and it will repeat itself after the last number of the order 6. Wire up the clock generator output (CLK) to the D-flip flop of bit-0. 7. Next, the counter is connected as shown in the diagram using the LEDs to test the output. 8. The LEDs sequence will light in binary. In the decimal sequence is equal to 0>1>2>3>4>5>6>7 Circuit uses 3 D-flip flop from 2 74HC74

Note: In order the LED to light up and off respectively, you have to touch the wire respectively between the two resistors.

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9) Sequence assigned; (Group 9) is changed to binary and compared to the 3-bit Asynchronous Up Counter. As shown in table below, Output Logic Block,Group 9 sequence 3,0,1,6,7,4,5,2 Bit-2 Bit-1 Bit-0 Sequence in decimal 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 0 1 6 7 4 5 2 Logic Table Decimal number in Binary OUTPUT-2 OUTPUT-1 OUTPUT-0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0

10) Use K arnaugh map for simplification the logic gates: OUTPUT-2 (OUT-2)
Bit-2 ,Bit-1 Bit-0

00

01

11

10

0 1

0 0

0 1

1 0

1 1

Output Equation: (Bit-2)(Bit-1)(Bit-0) + (Bit-2)(Bit-0) + (Bit-2)(Bit-1)

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OUTPUT -1 (OUT-1)
Bit-2 ,Bit-1 Bit-0

00

01

11

10

0 1

1 0

0 1

0 1

1 0

Output Equation: (Bit-1)(Bit-0) + (Bit-1)(Bit-0)

OUTPUT-0 (OUT-0)
Bit-2 ,Bit-1 Bit-0

00

01

11

10

0 1

1 0

1 0

1 0

1 0

Output Equation :( Bit-0)

Diagram representing the outputs from Karnaugh Map according to it gates

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Output -2
U5 Bit-0 NOT AND2 U1

U6 Bit-1 NOT

U2

U4 OUTPUT OR3

AND3

U7 Bit-2 NOT

U3 AND2

Output-1

U1 Bit-0 NOT

U3 AND2 U5 OUTPUT OR2

U2 Bit-1 NOT

U4 AND2

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Output -0 Legend
U1 Bit-0 NOT Output

Symbol
U1 OR2
U2 AND2

Explanation OR-Gate

AND-Gate

U3 OR2

Inveter

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COMBINATION LOGIC CIRCUIT LAB JOURNAL

To simplify all gates to NAND gates Aim: To reduce the number of gates used

1. The universal NAND gate as an OR gate

A

U1 NAND2 U2 NAND2

U3 NAND2

AB= A + B

A
A+B

2. The Universal NAND gate as AND gate

A B

U4
AB

U5
AB

NAND2

NAND2

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COMBINATION LOGIC CIRCUIT LAB JOURNAL

11) Knowing the universal properties of NAND gates. Circuit for output-2, output-1 and output0 can be simplified. The diagram is shown as follow:

Output-2
U1

NAND3

U2 NAND2

U4

Output
NAND3

U3 NAND2

Output-1
U1 NAND2

U3

Output
U2 NAND2 NAND2

Output-0
U1 Bit-0 NOT Output

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COMBINATION LOGIC CIRCUIT LAB JOURNAL

Final Circuit

4 ~1PR 2 1D 1Q

U1A
5

V2 5V
10 ~2PR

V3 5V U2B
2Q 9 2 1D 4 ~1PR 1Q 5

V4 5V U2A
12 2D 10 ~2PR 2Q 9

1CLK

~1Q

U1B

~1CLR 1

74HC74N_6V

12

2D

11

2CLK

~2Q

1CLK

~1Q

11

2CLK

~2Q

~2CLR 13

~1CLR

~2CLR

74HC74N_6V R3 560 X1 LED

74HC74N_6V R4 560

13

74HC74N_6V R5 560 X3 LED

R1 10k

R2 10k

R6 560 X4 LED

Bit-0

BIt-1

Bit-2

X2 LED

V1 5V

J1 Key = A

J2 Key = A

U5 NAND2 R7 560 X5 LED

U4 NAND2

U3 NAND3 R8 560 X6 LED

U8 NAND2

U7 NAND2

U6 NAND3

U9 NAND2

Diagram-3 - The complete circuit design

In Diagram-3, this is the final circuit of the 3-Bit Asynchronous counter that counts according to the sequence of 3>0>1>6>7>4>5>2 in binary form.

11) Finally, the counter is connected to output-2, output-1 and output-0 which are connected to the LEDs light in order to determine it is a working circuit.

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Actual Circuit

Learning Experience
1) Make sure that every component polarities are connected correctly. 2) The 5V power supply and the ground are connected accordingly in order to prevent the circuit from short circuit

Conclusion
The final circuit design as shown in the diagram-3 is an Asynchronous Counter which counts according to a specific sequence repeatedly, which is 3>0>1>6>7>4>5>2 in binary form.

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Appendix

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COMBINATION LOGIC CIRCUIT LAB JOURNAL

74HC/HCT10

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