EE141-Fall 2010 Digital Integrated Circuits

Lecture 2 Integrated Circuit Basics: Manufacturing and Cost

1

EE141 EECS141

Lecture #2

Administrative Stuff
Discussions start this Friday Labs start next week Homework #1 is due this Thursday
Everyone should have an EECS instructional account Use cory, quasar, pulsar

EE141 EECS141

Lecture #2

HSPICE Syntax
Simple CMOS inverter .include '/home/ff/ee141/MODELS/gpdk090_mos.sp TT_s1v * netlist Vdd vdd 0 1.2 VIN in 0 PULSE 0 1.2 200ps 100ps 100ps 2ns 4ns M0 out in vdd vdd gpdk090_pmos1V L=100e-9 W=120e-9 M1 out in gnd gnd gpdk090_nmos1V L=100e-9 W=120e-9 R1 in gnd 10K R2 out vdd 100K * extra control information .options post=2 nomod * analysis .op .TRAN .01ns 3ns .DC VIN 0 1.2 .001 .END
EE141 EECS141

Lecture #2

Last Lecture
Last lecture
Introduction, Moores law, future of ICs

Todays lecture
Introduce basics of integrated circuit manufacturing and cost

Reading: Ch 2.1, 2.2

EE141 EECS141

Lecture #2

CMOS Manufacturing Process

EE141 EECS141

Lecture #2

The MOS Transistor

Polysilicon Aluminum

EE141 EECS141

Lecture #2

The Manufacturing Process

For a complete walk-through of the process (64 steps), check the Book web-page

http://bwrc.eecs.berkeley.edu/IcBook

EE141 EECS141

Lecture #2

Photo-Lithographic Process
optical mask oxidation

photoresist removal (ashing)

photoresist coating stepper exposure

Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development process step acid etch spin, rinse, dry

EE141 EECS141

Lecture #2

Patterning of SiO2
Chemical or plasma etch Si-substrate (a) Silicon base material Photoresist SiO 2 Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask Exposed resist Si-substrate (c) Stepper exposure Si-substrate (f) Final result after removal of resist (e) After etching Hardened resist SiO 2 Si-substrate

(d) After development and etching of resist, chemical or plasma etch of SiO 2 Hardened resist SiO 2

SiO 2

EE141 EECS141

Lecture #2

Advanced Metallization

EE141 EECS141

Lecture #2

10

10

A Modern CMOS Process

gate-oxide TiSi2 AlCu SiO2 Tungsten
poly
p-well n-well

SiO2 p+

n+

p-epi p+

Dual-Well Shallow-Trench-Isolated CMOS Process DualShallow- Trench11

EE141 EECS141

Lecture #2

11

Transistor Layout
Cross-Sectional View
poly
p-well

SiO2

SiO2
n+

poly

Layout View

p-well

EE141 EECS141

Lecture #2

12

12

Cost

EE141 EECS141

Lecture #2

13

13

Cost of Integrated Circuits

NRE (non-recurrent engineering) costs - fixed
Independent of volume (i.e., number of units made/sold) Examples: design time and effort, mask generation, equipment, etc.

Recurrent costs - variable

proportional to volume Examples: silicon processing, packaging, test Most of these proportional to chip area
EE141 EECS141

Lecture #2

14

14

NRE Cost is Increasing

EE141 EECS141

Lecture #2

15

15

Total Cost
Cost per IC
cost per IC = variable cost per IC + fixed cost volume

Variable cost
variable cost = cost of die + cost of die test + cost of packaging final test yield

EE141 EECS141

Lecture #2

16

16

Die Cost
Wafer Single die
cost of wafer dies per wafer * die yield

cost of die =

From: http://www.amd.com
EE141 EECS141

Lecture #2

17

17

Wafer size
AMD Athlon

8 (200mm) 90nm CMOS

EE141 EECS141

12 (300mm) 90nm CMOS

Lecture #2

12 (300mm) 65nm CMOS

18
18

From: http://www.sandpile.org

Yield
Y= No. of good chips per wafer 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield

Dies per wafer =

(wafer diameter/2 )2 wafer diameter die area 2 die area

EE141 EECS141

Lecture #2

19

19

Defects
Yield = 1/4 Yield = 19/24

defects per unit area die area die yield = 1 + , where is approximately 3
die cost
EE141 EECS141

( die/wafer die area

1
-1

)( yield

die area

-3

die area 4
20
20

Lecture #2

Cost per Transistor

cost:
-per-transistor per-

1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985

Fabrication cost per transistor

1988

1991

1994

1997

2000

2003

2006

2009

2012

EE141 EECS141

Lecture #2

21

21

Next Lecture
CMOS transistors as switches How to build an inverter Design metrics

EE141 EECS141

Lecture #2

22

22