Advanced PCB Routing Technologies

Agenda
Challenges in PCB routing Core PCB design Bus path design Advanced fabrication technologies Team collaboration

Advanced PCB Routing, EDA Tech Forum 2007

Interconnect Routing Challenges

Design constraints
Too many; sometimes conflicting; limit flexibility Must understand rules to know when they can be bent

Bus path design

Parallel and serial structures Impact of HDI, flex, embedded passives Need for team collaboration and design reuse

Advanced fabrication technologies

Emphasis on reduced design time

Advanced PCB Routing, EDA Tech Forum 2007

Current State of PCB Design

Many designs involve significant interactive labor

Interactive labor for the sake of art is diminishing Use of automation within interactive tasks is evolving

Auto-routers often used for place/routing strategy evals Designers iterate between automatic & interactive tasks

Auto route typically not a push-button solution

High volume of design constraints demand a high level of creativity from designers Engineering and layout designer roles are blending The traditional one layout, one designer methodology is being challenged

Advanced PCB Routing, EDA Tech Forum 2007

Agenda
Challenges in PCB routing Core PCB design Bus path design Advanced fabrication technologies Team collaboration

Advanced PCB Routing, EDA Tech Forum 2007

PCB Layout
AutoActive environment is a next-generation, best-in-class solution that enables designers to break through the technology wall and create todays most challenging and complex PCB designs Ease of use + advanced technology support + superior routing performance
= Increased designer productivity = Increased design quality = Decreased design times
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PCB Layout
AutoActive design environment

Auto-routing technology combined with interactive editing capabilities Correct-by-construction methodology Single layout environment

Supports constraints for advanced interconnect and high-speed design technologies Common user interface Integrated design process Superior router setup and performance
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Productivity, Power and Value

Increased productivity reduces time to market
Single PCB editing environment (no translation) No artificial limits to constrain design Ease of use (common Windows GUI, usage model) Tight integration with system design environment Router performance (speed, completion rates)

Improved design quality / manufacturability Advanced technology support facilitates stateof-the-art designs

Upgrade path as design complexity increases

Advanced PCB Routing, EDA Tech Forum 2007

Agenda
Challenges in PCB routing Core PCB design Bus path design Advanced fabrication technologies Team collaboration

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Advanced PCB Routing, EDA Tech Forum 2007

Differential Pairs and Multi-Gigabit

I/O I/O
+ rx -

CORE

CORE

CORE

+ tx -

C1

C2
C1 C2

Synchronously clocked parallel architectures (primarily single-ended)

Asynchronously clocked serial architectures (primarily differential pair) SERDES (serializer at driver; deserializer at load)
Frequency

~ 10 MHz

0.5 GHz

Multi-GHz

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Advanced PCB Routing, EDA Tech Forum 2007

CORE

Traditional Parallel Buses Still Exist!

Serial interconnect only make up 10-20% of designs Parallel structures have long been associated with the artistry of PCBs

Improved performance (matched timing & impedance) Improved ECO-ability Above 1GHz; low power; high noise immunity; high data rates; telecom, networking, mil/aero Below 500MHz; cheap; high noise margins; simpler device architecture; consumer electronics, automotive, industrial

Serial usage

Parallel usage

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Advanced PCB Routing, EDA Tech Forum 2007

Parallel Bus Routing

Without adequate constraints, auto routers do this but designers would prefer this

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Advanced PCB Routing, EDA Tech Forum 2007

Parallel Bus Routing

Typical Design Process Design engineer
Typically sketches the physical bus systems and sub-systems architecture on paper Specific placement and bus interconnect guidelines remain in hard copy form with little automation

Board designer
Looks for potential routing patterns that flow from component to component Plans ahead, knowing why a particular group of traces must route in a certain path on a specific layer

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Parallel Bus Routing

Old methodology
Planning

Topology-Driven Design
Routing

New methodology
Planning Routing

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Advanced PCB Routing, EDA Tech Forum 2007

Parallel Bus Routing

Special Routing Controls
Bus with shielding Designated high-speed tuning areas

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Advanced PCB Routing, EDA Tech Forum 2007

Design Iterations and Reuse

Topology plan and routing becomes part of design database

Design database

Design team can iterate to best solution without re-entry performance and cost optimization ECOs are easily implemented reduced design cycle time Database can be re-used in future products, design reuse productivity and quality

Schematic

Layout
Topology Plan and Routing

Constraints

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Advanced PCB Routing, EDA Tech Forum 2007

Benefits of Topology Routing

Reduced product design cycle time

Capitalize on auto-routing speed Mimics the expertise of an experienced designer More functionality in smaller spaces Manufacturability Performance

More compact designs

Higher quality designs

Efficient re-use of design databases in future products Engineer to designer communication

No more paper or over the shoulder!

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Advanced PCB Routing, EDA Tech Forum 2007

Agenda
Challenges in PCB routing Core PCB design Bus path design Advanced fabrication technologies Team collaboration

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Advanced PCB Routing, EDA Tech Forum 2007

High-Density Interconnect
Benefits
Product size reduction Increased wiring density Higher density at a lower cost Improved electrical performance Improved thermal efficiency Greater design efficiency Increased flexibility Improved design time Lower RFI/EMI Layer reduction Improved yield
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1.6 mm (.064")

0.05 mm (.002")

High-Density Interconnect
Things to Consider
Creation of complex BGA packages Via structure

High pin-count ball grid array (BGA)

HDI / microvia layers

Stacked, adjacent Combo with vias through laminate

Laminate layers

Localized rules under components to facilitate escape paths

Adjacent

Coincident

Inset

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Advanced PCB Routing, EDA Tech Forum 2007

High-Density Interconnect
Things to Consider
Via fanout

Via-in-pad; patterns Routing schemes

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Advanced PCB Routing, EDA Tech Forum 2007

Embedded Passives
Benefits
Increased design density Reduced system cost Reduced system weight Reduced board area Increased performance Improved reliability Increased board yield Increased value flexibility Increased functionality Reduced assembly time
Source: Ohmega Technologies, Inc.
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Embedded Passive Design

Things to Consider
Parameter-driven device synthesis

Automatic geometry creation Input via design kits

Material characteristics library

Trade-off tools for discrete vs. embedded

Multiple materials Design optimization

Manufacturing data generation Value of automation

Increase throughput Minimize risks, increase quality Optimize cost, materials

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Advanced PCB Routing, EDA Tech Forum 2007

Agenda
Challenges in PCB routing Core PCB design Bus path design Advanced fabrication technologies Team collaboration

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Advanced PCB Routing, EDA Tech Forum 2007

Collaboration Drivers
Optimize system performance

Efficiently leverage unique skill sets of team Leverage local or globally dispersed teams for parallel / concurrent design

Reduce design cycle time

Increase resource management flexibility

Design entry PCB layout

Design entry Analog layout

Digital layout

RF layout

Design entry PCB layout PCB layout PCB layout

Design entry Analog layout Digital layout RF layout

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Advanced PCB Routing, EDA Tech Forum 2007

Layout Collaboration Methodologies

Outsourcing

Design must be partitioned (isolated), then merged when complete

Expanded team
Traditionally done with multiple shifts (at single location or follow-the-sun) Can also use the Drafter partitioning model

Digital Designer

Analog Designer

Electrical Engineer

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Advanced PCB Routing, EDA Tech Forum 2007

Layout Collaboration Challenges

Most layout designers are used to driving start to finish

Consistent planning and ownership Undisciplined teamwork may actually be redesign

Managing design partitioning and collisions

Joe

Bill

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Advanced PCB Routing, EDA Tech Forum 2007

Evolving Collaboration
Resource Management True simultaneous design
Link designers over local or global networks Dynamically display peer results Automatically keep database current Reduce design times proportionally with the number of designers working concurrently Share design tasks and pressures across the team Use any time in the design flow

Pre-placement, ECOs, documentation, etc.

Design review by specialists, management, manufacturing

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Advanced PCB Routing, EDA Tech Forum 2007

Evolving Collaboration
Resource Management Utilize networked computing resources
Single designer harnessing the power of multiple CPUs to accelerate auto-routing Geographically distributed computational resources Evaluate multiple placement / routing strategies Automated distribution process not efficient for smaller designs

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Advanced PCB Routing, EDA Tech Forum 2007

Conclusion
Design challenges
Increasing and conflicting constraints for performance and manufacturing Drive to reduce design time

Designers and their tools are evolving

Continued iteration between interactive & automatic tasks Blending of engineering and layout designer roles

New breed of planning (design abstraction) tools emerging

Concept of resource management is changing

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Advanced PCB Routing, EDA Tech Forum 2007