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DATA CONDITIONING & CARRIER MODULATION TRANSMITTER & DATA RECONDITIONING & CARRIER DEMODULATION RECEIVER

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CHAPTERS
1. To study theory of Carrier modulation & demodulation techniques 2. To study theory of line coding and decoding techniques 3. To study complete circuit

EXPERIMENTS
1. 2. 3. 4. 5. To generate ASK (Amplitude Shift Keying) signal and demodulate it by Diode detector To generate FSK (Frequency Shift Keying) signal and demodulate it by PLL detector To generate PSK (Phase Shift Keying) signal and demodulate it by product detector To generate QPSK (Quadrature phase Shift Keying) signal and demodulate it. To generate different line coding (formatting) signals and decode (reformat) them.

FEATURES AND SPECIFICATIONS This trainer has been designed with a view to provide practical/experimental knowledge of different types of Carrier modulation & demodulation techniques and line coding - decoding as practically implemented in Digital Communication systems on a two SINGLE P.C.B. of size 15 x 12. 1. Power supply requirement 2. Built in IC based power supply. 3. On Board Modulating Digital Data signal generator to generate any binary input word with Bit clock & Word clock. Word Length : 8 Bits. Word Clock Frequency :10 KHz. Data Format : NRZ 4. On Board synchronized RF carrier signal generators. Frequencies : 320 KHz, 640KHz, 1.2 MHz 5. Modulator Type 6. Demodulator Type 7. Standard Accessories : ASK, FSK, PSK, QPSK. : ASK, FSK, PSK, QPSK : 1. A Training Manual. 2. Connecting Patch cords. : 230V AC, 50 Hz.

CHAPTER-1
CIRCIUT DETAILS OF TRANSMITTER SECTION
(1) Modulating NRZ data Signal Generator section:This section generates this digital data signal. It consists of many digital ICs. The carrier clock of 1.28 MHz is generated by IC 74HC04. The 1K pot is used to vary the carrier clock (Ck) frequency. This Ck frequency is divided by 16 to produce bit clock (Bk) of 80 KHz. This Bit clock frequency is divided by 8 to generate Word clock (Wk) of 10 KHz. Then a word of 8 bit data is generated using D-FFs and eight data generating push switches. By pushing different push switches different data word can be generated. This data word is called as NRZ data. This NRZ data is inverted to produce inverted NRZ signal. It is also splitted in to odd and even data bit stream, which are known as In-phase (I) and 90 out of phase (Q) data by IC 4013, 4027 and 4052. Each push switch controls one bit from LSB to MSB viz. D1 to D8. (2) RF Carrier Generators: The function of this section is to generate phase synchronized carrier signal with respect to modulating digital NRZ input. It converts 1.28 MHz TTL clock signal Ck into 1.28 MHz sinewave carrier signal using pie filter made of 100uH coil and two 100 pf capacitor. It converts 640KHz TTL clock signal Ck into 640KHz sinewave carrier signal using pie filter made of 100uH coil and two 100pf capacitor. It converts 320KHz TTL clock signal Ck into 320KHz sinewave carrier signal using pie filter made of 100uH coil and two 100pf capacitor. (3) Carrier Generator Splitter: (a) Generator at switch position QPSK For the switch position at QPSK, this section generates two 90out of phase sine wave signal referred as 1 (0) and 2 (90). These 1 (0) and 2 (90) signals are generated from data carrier signal for synchronization. The carrier signal (1.28 MHz) is applied at the input of this section from data generator section. Its phase is shifted by phase splitter coil. The phase control pot controls the degree of phase shift of from carrier phase. The gain control controls the amplitudes of 1 and 2 signals. (b) Generator at switch position PSK For the switch position at PSK, this generates 180 out of phase sine wave signal referred as 1 is generated by transformer circuit. This signal is given as carrier signal to balanced modulator as one input. The phase control preset pot controls the degree of phase shift of this signal from carrier phase. The gain control controls the amplitudes of carrier signal 1. (4) Balanced Modulator sections: There are two balanced modulators used in transmitter side while two balanced modulators are used at receiver side. The function and circuit is same for all balanced modulators. IC 1496 is used as balanced modulator This IC has two inputs as it works as balanced modulator. The modulating signal is connected at pin 1 through buffer transistor BC548B. The Second input can be connected at pin 4 through buffer transistor BC548B. The RF carrier signal is connected at pin 8 through coupling capacitor from RF carrier oscillator section. The modulated outputs are available at pin 12 and 6 of this IC, which are then balanced amplified by transistor pairs -BC548B and BC558B. The final balanced modulated output is available at O/P terminal.100K preset is used to balance carrier signal while 1K preset is used to balance input audio signal. Output 1K preset is used to adjust output zero DC level. Output 2K2 preset is used to vary output level..

(5) Variable Bias generating section: This section provides +5 to 5V Dc voltage which given as bias to 2 n d input of balanced modulator to insert or remove carrier in output. There two separate bias supplies which vary from +5 to 5V Dc voltage (6) Adder section:This section adds two input signals with unity gain. This is used to add to ASK signals to converts into FSK signal. (7) Line Coding section :The function of this section is to produce different types of formatted signals form NRZ data. (8) Power supply section:The regulated power supply is used for different supply voltages. Following output D.C. Voltages are required to operate the trainer system. +15V, 250mA, -15V, 250mA, + 5V, 250mA + 5V, 250mA Three terminal regulators are used for different output voltages i.e. IC 7805 for + 5V, IC 7815 for +15V, IC 7915 for 15V, 7905 for 5V These ICs are supplied different dc input voltages by two Bridge rectifiers consisting of D1-D4 and D5-D8 & two 1000/25 EC and 1000/10 EC. The capacitors at each input & each output are for filtering purpose. ******************

CHAPTER-2
CIRCIUT DETAILS OF RECEIVER SECTION
(1) Balanced Modulator sections: There are two balanced modulators are used in receiver side. The function and circuit is same for all balanced modulators as explained in transmitter section. (2). Carrier Clock Recovery section: (a) PSK: The carrier clock signal is required for PSK demodulation. This carrier clock signal R1 must be same as carrier signal 1. Here a balanced modulator is used as squarer. The PSK modulated signal from modulator section is applied at both input of the balanced modulator. The output is square of input PSK signal, which has carrier clock frequency multiplied by 2 of original carrier signal. Then this signal is given to PLL circuit for phase and frequency locking. The recovered signal is frequency divided by 2 to generate original carrier signal. The recovered carrier signal is given to phase splitter section to generate Carrier clock signals R1. (b) QPSK The carrier clock signals are required for QPSK demodulation. These carrier clock signals R1 (0) and R2 (90) must be same as carrier signals 1 (0) and 2 (90). Here two balanced modulators are used as squarer. The QPSK modulated signal from modulator section is applied at both input of First balanced modulator. The output is square of input signal. Then the output signal is applied at both input of second balanced modulator. The output of second modulator is quadruple of QPSK signal, which has carrier clock frequency multiplied by 4 of original carrier signal. Then this signal is given to PLL circuit for phase and frequency locking. The recovered signal is frequency divided by 4 to generate original carrier signal. The recovered carrier signal is given to phase splitter section to generate Carrier clock signals R1 (0) and R2 (90). (3) ASK Demodulator:This circuit consists of Diode OA79 and Capacitors C1, C2 and Load resistor R. It works as an envelope detector circuit. R & the capacitor C forms a low pass filter meant to reduce the carrier frequency ripple in the output. The values of R & C are chosen so as to remove even the modulating signal frequency components. The magnitude of this dc voltage should vary as the carrier amplitude in the input signal and should be independent of the depth of modulation and the modulating signal frequency. C1, C2 can be selected through switch. (4) FSK Demodulator:This circuit is based on PLL made of IC 4046. The free running frequency of PLL is set at 320KHz value. Hence when FSK signal having two frequency 320KHz and 640Khz is given to it input, it produced demodulated signal locked to 320Khz. Hence output is raw data signal. This signal is then given to squarer circuit. (5) Data Squarer circuit:The two data squarer circuits are provided. The circuit of each squarer consists of Comparator. The Raw data signal available from detector is applied positive terminal of comparator while a variable bias voltage -5 to + 5 V is applied at negative terminal. The output of comparator is pure digital signal with sharp rising and falling edges similar to input digital data. The Zero bias can be varied by 10K pot. (7) Data Decoder section Here two ICs are used to sample input data at different pulse positions of bit clock to recover formatted data. (8) Bit Clock recovery section This section recovers bit clock from formatted data. It is based on PLL circuit. The free running frequency of PLL is set at 80KHz, which is bit frequency value. Hence formatted data is applied at input, the PLL frequency is locked exactly at bit frequency. Hence output is recovered bit clock.

(8). Data summer (QPSK MUX) section: This section adds two I and Q decoded outputs and generates NRZ data. (9) Power supply section:The regulated power supply is used for different supply voltages. Following output D.C. Voltages are required to operate the trainer system. +15V, 250mA, -15V, 250mA, + 5V, 250mA + 5V, 250mA Three terminal regulators are used for different output voltages i.e. IC 7805 for + 5V, IC 7815 for +15V, IC 7915 for 15V, 7905 for 5V These ICs are supplied different dc input voltages by two Bridge rectifiers consisting of D1-D4 and D5-D8 & two 1000/25 EC and 1000/10 EC. The capacitors at each input & each output are for filtering purpose.

EXPERIMENT 1
AMPLITUDE SHIFT KEYING MODULATION/ DEMODULATION

(A) BLOCK DIAGRAM OF ASK MODULATION/DEMODULATION

Balanced modulator (with Bias) ASK Signal DG NRZ Digital Data Generator
Diode Detector

Raw Data

Data Squarer

Variable R-C Constant

Recovered Data

RF

RF Carrier Generator

Modulator

Demodulator (B) Experiment Procedure:(See connection diagram CN1)

1. 2.

Connect circuit as per connection diagram using connectors. Connect CRO channel-1 at NRZ DATA terminal of Digital Data generator (T1). Apply any digital word by pushing push switches in data generator section. e.g. 11110000. ______ Waveform (T1) Connect CRO channel-2 at 320 KHz RF carrier and observe RF carrier.. _____Waveform (T2) Now Connect CRO Channel 2 at O/P terminal of balanced modulator. Trigger CRO by channel-1. The ASK Modulated wave will be observed. Vary bias pot to set zero level in ASK waveform.

3. 4.

______Waveform (T3)

5. 6. 7. 8. 9.

See the effect on the ASK Modulator output by varying the bits in NRZ data by push switches. Observe the Demodulated Raw NRZ data wave at the Diode Detector output. ______Waveform (T4) Vary zero bias pot in squarer section and observe pure NRZ data at the output of Data squarer. _______Waveform (T5) Vary RC time constant in the Diode Detector by selecting different capacitor C1,C2 by switch and by varying Pot and observe raw data. Apply different digital word by pusing push switches in data generator and observe recovered signal.

TEST POINT WAVEFORMS T1. NRZ Data at NRZ Terminal of Digital data generator:+5 V

T2. RF Carrier signal at RF Carrier terminal of RF Oscillator: -

+5V

-5V
T3. ASK Modulated signal at ASK O/P Terminal of Balance Modulator: -

T4. RAW ASK DATA signal at output of Diode detector

T5. Recovered NRZ SIGNAL at output of DATA Squarer:+5 V

EXPERIMENT 2
FREQUENCY SHIFT KEYING MODULATION/ DEMODULATION

(A) BLOCK DIAGRAM OF FSK MODULATION/DEMODULATION Modulator

Digital Data Generator DG NRZ Balanced modulator (with Bias) ASK Signal

RF ADDER RF Carrier Generator - 320KHZ Balanced modulator (with Bias) ____ NRZ FSK Output

RF RF Carrier Generator 640KHz

FSK Mod Input

FSK
Demodulator

Raw Data

Data Squarer

Recovered Data

Demodulator
10

(B) Experiment Procedure:(See connection diagram CN2) 1. 2. Connect circuit as per connection diagram using connectors. Connect CRO channel-1 at NRZ DATA terminal of Digital Data generator. First apply any digital word by pushing push switches in data generator section. e.g. 11110000. ______ Waveform (T1) Connect CRO channel-2 at 320 KHz RF carrier and observe RF carrier-1 Now Connect CRO Channel 2 at O/P terminal of balanced modulator-1. Trigger CRO by channel-1. The ASK Modulated wave -1 will be observed. Vary bias pot to set zero level in ASK waveform. ____ Connect CRO channel-1 at NRZ DATA terminal of Digital Data generator. Connect CRO channel-2 at 640 KHz RF carrier and observe RF carrier-2. Now Connect CRO Channel 2 at O/P terminal of balanced modulator-2. Trigger CRO by channel-1. The ASK Modulated wave-2 will be observed. Vary bias pot to set zero level in ASK waveform. Connect CRO channel-1 at NRZ DATA terminal of Digital Data generator. Now Connect CRO Channel 2 at O/P of Adder. Two ASK waveforms will be added and FSK output will be observed. ______ Waveform (T2) Observe the Demodulated Raw NRZ data wave at the FSK demodulator output ._____Waveform (T3) Vary zero bias pot in squarer section and observe pure NRZ data at the output of Data squarer. _______Waveform (T4) Apply different digital word by pusing push switches in data generator and observe recovered signal.

3. 4.

5. 6. 7.

8.

9. 7. 8.

11

TEST POINT WAVEFORMS T1. NRZ Signal at NRZ terminal of Digital data generator:-

4v TTL

-10V 10us T2. FSK modulated output signal at FSK O/P: +10V

-10V T3 FSK demodulated Raw Data at o/p of Resonant phase shift detector:-

T4 Recovered NRZ data at o/p of square Circuit: -

4v TTL

12

EXPERIMENT 3
PHASE SHIFT KEYING MODULATION/ DEMODULATION (A) BLOCK DIAGRAM OF PSK MODULATION / DEMODULATION
(A) PSK MODULATOR NRZ Balanced Modulator Bipolar NRZ DG Digital Data Generator RF Carrier Generator 180 Out of Phase Carrier RF Carrier PSK Signal

Carrier clock

(B) PSK DEMODULATOR

PSK Signal

Squarer PLL F / 2 Clock Recovery

TT L t o S in e Co n v ert er

Recovered RF carrier

RF Carrier PSK Signal Raw data

Squarer

Received Data

S a mp l i ng

Recovered Data

Balanced Modulator
Bi t Cl o ck Reco v ery

13

(B) Experiment Procedure:(See connection diagram CN3) 1. 2. Connect circuit as per connection diagram using connectors. Connect CRO channel-1 at NRZ DATA terminal of Digital Data generator. First apply any digital word by pushing push switches in data generator section. e.g. 11110000. ______Waveform (T1) Connect CRO Channel-2 at RF Carrier socket (in Carrier generator section) and observe it. Connect CRO Channel 1 at RF Carrier and CRO Channel 2 at 1 signal and Observe their 180 out of phase relationship. Connect CRO Channel-1 at Bipolar NRZ socket and observe it. Now Connect CRO Channel 2 at the PSK output of PSK modulator. Connect CRO channel 1 at Bipolar NRZ terminal. Observe PSK output. Observe recovered raw data signal at output of PSK demodulator. _______Waveform (T2) _______Waveform (T3) _______Waveform (T4) _______Waveform (T5) ______Waveform (T6) ______Waveform (T7)

3. 4. 5. 6. 7.

8. Observe received pure NRZ data at the output data squarer. 9.

Apply different digital word by pusing push switches in data generator and observe recovered signal.

14

TEST POINT WAVEFORMS T1. NRZ Signal at NRZ terminal of Digital data generator:-

4v TTL

T2. R.F. Carrier signal at RF carrier terminal :+0.6V

-6V
T3. 180 out of phase signal 1 in RF carrier generator :+0.6V

-6V
T4. Bipolar NRZ data: +5V

-5V

15

T5. PSK modulated signal with reference to Bipolar NRZ data: 4v TTL

T6. Raw data recovered signal at o/p of PSK demodulator: -

T7. Recovered NRZ data RCD at o/p of Squarer Circuit: 4v TTL

16

EXPERIMENT 4
(A) BLOCK DIAGRAM OF QPSK MODULATION / DEMODULATION
(A) QPSK MODULATOR

NRZ Even Bit Data I

In phase Carrier 1 Sin (w o t) I

Digital Data Generator Carrier Clock

Odd Bit Data Q Q

Adder

QPSK Signal

Phase Shifter

0 Carrier 90 Carrier

Quadrature Carrier 2 Cos (wot)

17

(B) QPSK DEMODULATOR

QPSK Signal

Squarer-1

Squarer-2 PLL F / 4 Recovered Carrier Phase Shift Quadrature Carrier

Carrier Recovery

In phase Carrier

Sin (w o t) QPSK Raw Data-1

Data S qu a r e r

Received Data RCD1

Bi t Cl o ck Reco v er

Bit Sampling Clock

S a mp l i ng

Received Data

QPSK

Raw Data-2

Data S qu a r e r

Received Data RCD2

Cos (wot)

18

(B) Experiment Procedure:(See connection diagram CN4) 1. 2. Connect circuit as per connection diagram using connectors. Connect CRO channel-1 at NRZ DATA terminal of Digital Data generator. First apply any digital word by pushing push switches in data generator section. e.g. 11110000. ______Waveform (T1) Connect CRO Channel-1 at I signal and CRO Channel-2 at Q signal and observe there relationship. Prove that these are even and odd bit data by applying different data by push switches. _______Waveform (T2) _______Waveform (T3) Connect CRO Channel-1 at RF Carrier socket (in Carrier generator section) and observe it. _______Waveform (T4) Connect CRO Channel 1 and 2 at 1 and 2 signal respectively (in carrier generator section) and Observe their 90 out of phase relationship. _______Waveform (T5) _______Waveform (T6) Now Connect CRO Channel 2 at the QPSK output of QPSK modulator. Connect CRO channel 1 and RF carrier. Observe the relationship of QPSK signal with RF carrier signal . _______Waveform (T7a) Observe QPSK output of respect to In phase (I) signal by triggering channel 1 by I signal. _______Waveform (T7b) Observe recovered raw data RI and RQ at the output of balanced demodulators ___ Waveform (T8a) ______ Waveform (T8b) Observe received pure digital I and Q data at the output of data squarer. Observe recovered bit clock. ______ Waveform (T9a) ______ Waveform (T9b) ______ Waveform (T10)

3.

4. 5.

6.

7. 8. 9. 10. 11. 12.

Finally observe recovered NRZ data at NRZ O/P of data combiner section. _______Waveform (T11) Apply different digital word by pusing push switches in data generator and observe recovered signal.

19

TEST POINT WAVEFORMS

T1. NRZ Signal at NRZ terminal of Digital data generator:4v TTL

T2. I Signal of Digital data generator: 4v TTL

T3. Q Signal of Digital data generator: 4v TTL

T4. R.F. Carrier signal at RF carrier terminal: +0.6V

-6V

20

T5 and T6. 0 In phase signal - 1 and 90 out of phase signal 2 in RF carrier generator :-

T7a. QPSK modulated signal with reference to Input Digital data :-

T7b. PSK modulated signal with reference to I signal:-

21

T8a and T8b. Raw data recovered signal RI and RQ at o/p of PSK demodulator: -

T9a and T9b. Received I and Q signals (RCD-I and RCD-Q) at o/p of Squarer Circuit: 4v TTL

4v TTL

T10. Recovered Bit Clock: -

12.5 us T11. Final Recovered NRZ Signal at NRZ O/P of Data Multiplexer section: 4v TTL

******************** 22

EXPERIMENT 5
STUDY OF THEORY OF DATA FORMATTING
The symbols `0 and `1 in digital system can be represented in various formats with different levels and waveforms. The selection of particular format for communication depends on the system bandwidth, systemss ability to pass DC level information, error checking facility, ease of clock regeneration & Synchronization at receiver, system complexity and cost etc. The most widely used formats of data representation are given below. They are also available on ST2106 trainer. Every data format has specific advantages and disadvantages associated with them. We will study one by one. See Fig. 1. (1) NON RETURN TO ZERO (LEVEL) NRZ (L) :It is the simplest form of data representation. The NRZ (L) waveform simply goes low for one bit time to represent a data `0 and high for one bit time to represent a data `1; Thus the signal alternates only when there is a data change. See Figure 2.

23

CLOCK REGENERATION: Since the level transition takes place at a predetermined moment (e.g. at Rising/Falling edge of the data clock), it is possible to extract clock information at the receiver. However the synchronization & clock information is sparse & sometimes even lost when a long stream of zero or ones are encountered. The clock regeneration is very difficult in such cases. This make the clock regeneration design more complex. BANDWIDTH :The maximum rate at which the NRZ (L) waveform can change is half the data clock. This happens when the data stream consists of an alternate 0s and 1s. As it is known, it is the maximum signal frequency which determines the bandwidth occur-pied by the NRZ (L) code. As you will study other data formats you will appreciate that the NRZ (L) waveform requires comparatively narrow bandwidth. DC LEVELS :Another problem with NRZ (L) code is that it contains DC Level & hence cannot be used for communication systems which cannot pass DC, e.g. transmission paths involving transformers AC Coupled amplifiers or series capacitors filters etc. This happens particularly in Telephone.

(2) NON RETURN TO ZERO (MARK) NRZ (M) :The NRZ (M) code is very much similar to the NRZ (L) code. Here if logic 1 is to be transmitted. The new level is inverse of the previous level i.e. change in level occurs. If a data `0 is to be transmitted the level remains unchanged. Thus in the case of NRZ (M) waveform the present level is related to the previous levels. See Fig. 3. Thus, no longer the absol3ute value of signal is necessary instead it is the change in the level for which we look now. Remember, -------------------A change mean a logic `1 No change mean a logic `0

Figure 3 NRZ(M) FORMAT

24

CLOCK RECOVERY: The receiver can extract the timing information from the NRZ (M) waveform unless there are long periods of no level changes corresponding to long streams of 0s. Here long stream of 1s are not a problem as in NRZ (L) because now it causes a level change continuously and the receiver can easily extract the clock information. This is a slight improvement over NRZ (L) waveform. BAND WIDTH & DC LEVEL :The NRZ (M) is similar to NRZ (L) waveform in respect of the bandwidth utilized and the passing of DC Levels. A considerable advantage of NRZ (M) is that it is independent of the absolute level of the incoming data. The receiver simply has to know the level changes. This is an advantage in phase shift keying as will be 3discussed later on, where the receiver looks for a change in phase of the incoming signal. DECODING :The NRZ (M) can be converted to NRZ (L) code by a Bit Decoder. The bit decoder samples the incoming data bit, holds it for a moment, takes a new sample and compare the two to see whether the changes has occurred. If it has occurred gives it output a logic `1 and if not it gives output a logic `0 This is the required NRZ (L) code. (3) RETURN TO ZERO (RZ) FORMAT: The RZ code provides a partial solution to overcome the receiver clock regeneration problem with NRZ (L) code. It is similar to NRZ (L) code, except that the information is contained in the first half of the bit interval while the level during the second half of each period is always 0 volts. The comparision of the two waveforms for a given data is shown in Fig. 4. The change may not be seen much, but it has two main effects as will be discussed in following paragraphs.

Figure 4 RZ FORMAT

25

RECEIVER CLOCK: One advantage of RZ signal is that now it has rising and falling transitions for every data `1 sent. This leads to a greater no of transitions. These extra transitions tend to make the receiver clock generation circuit more simpler than in case of NRZ (L) code. Even if we utilize only the rising edge, RZ will produce two rising transitions for two consecutive 1s instead of one as in case of NRZ (L) code. BANDWIDTH :The maximum signal frequency of RZ signal occurs when a string of a data `1 is transmitted. It is equivalent to sending two logic levels in each clock period i.e. in most case, the maximum signal frequency is same as the data clock rate. This is twice as many changes per second as for the NRZ (L) code. There fore the bandwidth required is twice as that required for the NRZ waveforms. DC LEVEL :Another problem with RZ is that like NRZ (L) it has DC Component and hence it can not be utilized for systems / Links. Which cannot pass DC In NRZ (L) decoding the level is read by the receiver halfway through each bit interval to let the data settle down after transitions. Otherwise the level may be wrongly read. In RZ code, to catch the mid-point of the data the receiver must be clocked at quarter way through the bit inter-val. The data is read on the rising edge of the regenerated clock in the receiver. In spite of its deficiencies RZ is often used because it is simple to generate and yet produces more transitions than NRZ, there by making the receiver clock regeneration some what easier.

Figure- 5

26

INTRODUCTION TO BIPHASE CODES The main disadvantage with all the previous formats has been their inability to provide reliable clock synchronization information to the receiver clock. Biphase codes overcome this problem by providing the transition in both 0s and ones. The two most common biphase codes in practice are Biphase (Manchester) & Biphase (Mark) codes. Also these codes are independent of the DC Levels i.e. they have zero d.c. component. (5) BIPHASE (MANCHESTER) CODING: The encoding rules for Biphase (Manchester) code are as follows A data `0 is encoded as a low level during first half of the bit time and a high level during the second half. A data `1 is encoded as a high level during first half of the bit time and a low level during the second half. Thus string of 1s or 0s as well as any mixture of them will not pass any synchronization problem at receiver. Fig 6 shows the Biphase (Manchester) waveform for a given data stream.

BIPHASE (MANCHESTER) FORMAT Figure 6 BANDWIDTH :The Biphase (Manchester) code always contain at least one transition per bit time, irrespective of the data being transmitted. Hence the maximum frequency of the Biphase (Manchester) code is equal to the data clock rate when a stream of consecutive data `1 and `0s is transmitted. Thus the required bandwidth is same at that of the RZ code and double as that of the NRZ (L) code. 27

DC LEVEL :Since the Biphase (Manchester) code has a high level for half of each data bit time and low level for second half irrespective of the data, the effective d.c. level of the Biphase coded waveform is zero. This allows it to be used in a.c. coupled communication systems. PROBLEM IN DECODING: This form of coding certainly provides plenty of rising edges for clock synchronization but they do not all occur at same time e.g. we have a rising transition at the start of code for data `1 where as for data `0 we have it at the midway of the data bit time. This causes confusion in the clock regeneration circuit. To overcome this, we employ a special Biphase Clock Recovery Circuit which can be synchronized by the rising edge occurring at either time. Rest of the decoding is same as for the Rz code. Since the valid data is carried for in first half of each clock period, we ensure that the regenerated receiver clocks rising edge occurs at this time. (6) BIPHASE (MARK) The Biphase (Mark) is yet another form of Biphase formats. In this coding also, the data is coded as two levels in each bit time. Here, the sequence of transmitted levels (low succeeded by high) or (high succeeded by low) depends on the order of sequence in previous bit time and the present data. The encoding laws followed by this format are (A) If a data `0 is to be transmitted, the sequence of the transmitted levels will remain same as for the previous bit interval. (B) If a data `1 is to be transmitted, the sequence of the transmitted levels will reverse i.e. phase reversal will occur. Thus, LOGIC `0 LOGIC `1 BIT PATTERN STAYS THE SAME PHASE REVERSAL

The Fig 7 would make it very clear.

28

BIPHASE (MARK) FORMAT Figure 7 BANDWIDTH :The Biphase (Mark) code being very similar to the Biphase (Manchester) coding requires same amount of bandwidth i.e. double as that of the NRZ (L) Code. This is the required bandwidth in worst case when a series of consecutive `1s occur. DC LEVEL :Similar, to the Biphase (Manchester) code, this code too is independent of the DC Level. This is so because for every bit time the level is high for a half period and low for other half. This feature makes it useful in applications & systems supporting only the A.C. Coupling. RECEIVER CLOCK REGENERATION :This coding provides plenty of rising edges for clock synchronization. But as with Biphase (Manchester) these do not all occur at the same time e.g. in one the rising edge may occur at the start of the bit interval where as it may occur mid way between the bit interval in other. Again to over come this problem Biphase Clock Recovery Circuit is used which can be synchronized by rising edge occurring at either time, as we have studied earlier. Rest of decoding is same as that for Biphase (Manchester) But since the output gives the information about the changes rather than the actual levels, it needs to be further processed in Bit Decoder as has been studied in NRZ (M) decoding. In this circuit each sample is compared with the previous one. If they are same, a logic `0 is produced if different, a logic `1. The advantage of this system over Biphase (Manchester) is that it is suitable for the systems where it is easier to spot the changes in sequence than the actual level e.g. in PSK modulation system.

29

INTRODUCTION TO THREE LEVEL CODES The three level codes, as the name suggest have three levels. Generally, they are two bipolar voltage & a 0 volt. The two important codes in this category are Return to Bias (RB) and alternate Mark Inversion (A M I). The Return to Bias coding method provides easy clock synchronization and the Alternate Mark Inversion coding is particularly suitable for the AC Coupled communication systems. (7) RETURN TO BIAS (R B) :R. B. Code is a three level code. The levels used are a positive voltage level, a negative voltage level and an intermediate (or bias) level (Usually 0 volts). There is no restriction on the value of bias level. It can be above or below the logic 0 and 1 voltages, or it can be between them. During the first half period of each clock bit, a positive level is transmitted for data `1 and a negative level for a data `0. During the second half, the waveform just returns to the bias level. Fig 8 shows the coded waveform for the given data.

RB FORMAT - Figure 8 BANDWIDTH REQUIREMENT: Since the maximum signal frequency is equal to the data clock frequency, the bandwidth requirement is same as that for RZ, Biphase codes and double that for the NRZ codes.

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DC LEVEL: As it can be seen from the above Figure the waveform at the output is not balanced with respect to the means level. The DC Level of the waveform depends on the strings of 1s and 0s. Thus, We cannot use it in an a.c. coupled communication link. CLOCK RECOVERY :The Most significant advantage of RB coding is that the timing information is very easily obtained. The magnitude of the transmitted waveform itself is the original data clock signal. The system is even referred to as `Self Clocking system. The other disadvantage of RB signal is that since the transmitter must generate three levels, a more complex transmitter is required. DECODING: A simple comparator decodes the RB signal into RZ waveform. The comparator for outputs a logic 1 (+5V) if the signal is greater than the bias voltage (threshold voltage) applied to the other input and a logic 0 (0.V) output if the input voltage is less. The rest of decoding is same as that for the RZ. Code. See Fig. 9. The clock can be simply extracted by a circuit that gives a positive output when RB signal is not at 0 volts (polarity doesnt matter) and provides a zero voltage whenever the RB waveform is at Bias level.

Figure 9

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(8) ALTERNATE MARK INVERSION (AMI) :AMI being a three level code uses three levels namely, a positive voltage level, a negative voltage level and a bias level of 0 volts. Like RB waveform, the AMI always returns to the bias level during second half of the bit time interval during the first half the transmitted level can be a positive level a negative level or a bias level, according to following coding rules. (A) A data `0 is always represented by the bias level. (B) A data `1 may be represented by either a positive level or negative level, the level being chose opposite to what it was used to represent the previous data `1. Thus we have alternating positive level and negative level. This justifies its name alternate Mark Inversion Mark is a telegraphers word for logic `1. The fig 18 shows the AMI waveform for the given data. The AMI waveform can be thought of as a gradual development from NRZ (L) to RZ and then finally to AMI. In NRZ (L) Code the pulse simply goes to the required level for one bit clock. In Rz, the pulse goes to the required level for first half and then returns to zero during the second half. In AMI, first logic `1 go to a positive voltage level and then the second 1 goes a negative level alternating and so on. The development can be seen from the Fig. 10.

VARIOUS FORMATS REPRESENTING ARBITRARY DATA Figure 10

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BANDWIDTH REQUIREMENT: Since the maximum transition rate for AMI can only occur during a stream of all `1s, we have maximum number of two transitions per data bit time. thus the bandwidth required is twice that required for the NRZ codes and equal to the other codes mentioned earlier. DC LEVEL :The main advantage of AMI code is that it is independent of DC level. This happens because the `1s are represented by alternating positive levels and negative levels with 0 volts for data `0. Thus the average DC Level is always zero volts for any combination of `1s & `0s. This renders it very useful in a.c. coupled communication systems/link e.g. in telephony PCM This makes it very popular for use in PCM telephone systems. CLOCK REGENERATION :The disadvantage of AMI is that there are no transitions if a long string of 0s is transmitted. Thus the receiver may slip out of synchronization in such cases. Since AMI is a three-bit code, the transmitter is more complex. An advantage associated with AMI is that if due to noise the voltage level of `1s is reduced/enhanced so much that it acquires the polarity of the previous bit, the receiver will take it as a violation of coding rule and may ask the transmitter to send the string again. Thus the transmission reliability can be increased.

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TEST POINT WAVEFORMS 1. Carrier Clock Signal CK (1.28 MHz): 4V TTL

H = 0.2 us V = 2 V Trig = CRO-1

0.78 us 2. Bit Clock Signal BK (80 KHz): 4V TTL H = 5 us V = 2 V Trig = CRO-1

12.5 us 3. Word clock WK (10KHz): 4V TTL

H = 20 us V = 2 V Trig = CRO-1

100 us
4. NRZ Signal at NRZ terminal of Digital data generator for 11110000 data:-

4v TTL
H = 20 us V = 2 V Trig = CRO-1

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EXP-1 ASK MODULATION/DEMODULATION

EXP-2 FSK MODULATION/DEMODULATION

EXP-3 PSK MODULATION/DEMODULATION

EXP-4 QPSK MODULATION/DEMODULATION

EXP-5 (a) LINE CODING/DECODING (NRZ-L)

EXP-5 (b) R-Z CODING/DECODING

EXP-5 (c) Bipolar R-Z CODING/DECODING (i) Bipolar RZ to RZ (ii) RZ to NRZ

EXP-5 (d) Bipolar NRZ

EXP-5 (e) RB CODING/DECODING (i) RB to RZ (ii) RZ to NRZ

EXP-5 (f) AMI CODING/DECODING (i) AMI to RZ (ii) RZ to NRZ

10

EXP-5 (g) TERNARY CODING/DECODING (i) Ternary to RZ (ii) RZ to Ternary

11

EXP-5 (h) NRZ (M) CODING/DECODING

12

EXP-5 (i) BIPHASE MARK CODING/DECODING

13

EXP-5 (j) BIPHASE SPACE RECOVERY

14

EXP-5 (k) NRZ (S)

15