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Definition
A register is a digital circuit with two basic functions: Data Storage and Data Movement
A shift register provides the data movement function A shift register shifts its output once every clock cycle
A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs connected together in such a way that the data is shifted from one device to another when the circuit is active
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converting between serial data and parallel data temporary storage in a processor
scratch-pad memories
Direction
Left shift Right shift Rotate (right or left) Bidirectional
Data Movement
The bits in a shift register can move in any of the following manners
Data Movement
Block diagrams for shift registers with various input/output options:
Serial-In Serial-Out
Data bits come in one at a time and leave one at a time One Flip-Flop for each bit to be handled Movement can be left or right, but is usually only a single direction in a given register Asynchronous preset and clear inputs are used to set initial values
n-bit shift register
Serial-In Serial-Out
The logic circuit diagram below shows a generalized serial-in serial-out shift register
SR Flip-Flops are shown Connected to behave as D Flip-Flops Input values moved to outputs of each Flip-Flop with the clock (shift) pulse
Shift Registers
The simplest shift register is one that uses only Flip-Flops The output of a given Flip-Flop is connected to the D input of the Flip-Flop at its right. Each clock pulse shifts the contents of the register one bit position to the right. The Serial input (SI) determines what goes into the leftmost FlipFlop during the shift. The Serial output (SO) is taken from the output of the rightmost Flip-Flop.
Serial-In Serial-Out
A simple way of looking at the serial shifting operation, with a focus on the data bits, is illustrated at right The 4-bit data word 1011 is to be shifted into a 4-bit shift register One shift per clock pulse Data is shown entering at left and shifting right
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Serial-In Serial-Out
The diagram at right shows the 4-bit sequence 1010 being loaded into the 4-bit serial-in serialout shift register Each bit moves one position to the right each time the clocks leading edge occurs Four clock pulses loads the register
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Serial-In Serial-Out
This diagram shows the 4-bit sequence 1010 as it is unloaded from the 4bit serial-in serial-out shift register Each bit moves one position to the right each time the clocks leading edge occurs Four clock pulses unloads the register
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Serial-In Serial-Out
Serial-in, serial-out shift registers are often used for data communications
such as RS-232 modem transmission and reception Ethernet links SONET etc.
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Serial-to-Parallel Conversion
We often need to convert from serial to parallel
e.g., after receiving a series transmission
n-bit shift register
The diagrams at right illustrate a 4-bit serial-in parallel-out shift register Note that we could also use the Q of the right-most FlipFlop as a serial-out output
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Serial-to-Parallel Conversion
We would use a serial-in parallel-out shift register of arbitrary length N to convert an N-bit word from serial to parallel It would require N clock pulse to LOAD and one clock pulse to UNLOAD
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Serial-to-Parallel Conversion
These two shift registers are used to convert serial data to parallel data The upper shift register would grab the data once it was shifted into the lower register
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Parallel-to-Serial Conversion
We usa a Parallel-in Serial-out Shift Register The DATA is applied in parallel form to the parallel input pins PA to PD of the register It is then read out sequentially from the register one bit at a time from PA to PD on each clock cycle in a serial format One clock pulse to load Four pulses to unload
n-bit shift register
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Parallel-to-Serial Conversion
Logic circuit for a parallel-in, serial-out shift register
0 1 0 1
Mux-like
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Parallel-In Parallel-Out
Parallel-in Parallel-out Shift Registers can serve as a temporary storage device or as a time delay device The DATA is presented in a parallel format to the parallel input pins PA to PD and then shifted to the corresponding output pins QA to QD when the registers are clocked One clock pulse to load One pulse to unload
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L/S A B
L/S
0 1
A B
0 1
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0
1
0
1
Mux-like
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A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.
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01
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00
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00
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00
01
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00
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right left circular right circular left arithmetic right arithmetic left
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S0 S1
CP CD
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Serial Communications
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Source module
Destination module
Each channel gets a timeslot in a frame where it can send 8 bits every 125 sec.
8000 frames/sec
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Timeslot details
count = 255
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256
Parallel-to-serial conversion
LSBs are bit number
count = 255
Serial data to destination
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Serial-toparallel conversion
Detect that a complete byte has been received Holding register for complete byte
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Note: loads 00
Destination timing
Grab complete byte when available Holding-register outputs Serial-in, parallel-out shift register outputs
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Or use a phase-locked loop (analog circuit) to extract clock from the data:
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PLL clock recovery -- what if too many zeroes are transmitted? PLL cant stay in sync.
Solution: Use a code that guarantees a minimum number of ones Phone system: Map 00000000 --> 00000010 (creating slight voice distortion)
Assignments
Completed Part 2 Midterm problems due Wednesday Continue working on the MIPS project
Description available on the course web page
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