ELE655 LAB MANUAL FPGA Design Flow for Xilinx

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ELE655 LAB MANUAL 1. Design Entry may have two alternatives: a) Performing HDL coding for synthesis as the target (Xilinx HDL Editor) b) Using Cores (Xilinx Core Generator) 2. Functional Simulation of Synthesizable HDL code (MTI Model Sim) 3. Design Synthesis (Xilinx project navigator) 4. Design implementation (Xilinx Design Manager) The stages are linked as follows:

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VERILOG HDL/VERILOG CODE DESIGN ENTRY

FUNCTIONAL SIMULATION

SYNTHESIS

POST SYNTHESIS SIMULATION

IMPLEMENTATION

TIMING SIMULATION

PROGRAM ONTO FPGA

Design Entry The first stage of Xilinx design flow is a design entry process. A design must be specified either a schematic editor or HDL text-based tool

Functional Simulation The functional simulation of the design is used to verify functionality of the design assuming zero delay in simulation. The simulation is performed before the design is implemented as hardware. Testbenches (Verilog HDL) or text fixtures are used to specify circuit stimuli and responses. Simulation can be divided as functional and timing simulation. Functional simulation verifies that the designs specifications are correctly coded . Timing simulation operates with real delays (results of Page | 2

ELE655 LAB MANUAL

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device implementation) and is used for verification of implemented design. Timing data are given in an .sdf file (Standard Delay Format) . Xilinx supports functional and timing simulations at different points of the design flow: Register Transfer Level (RTL) simulation Post-synthesis functional simulation (Pre-NGDBuild) Post-implementation back-annotated timing simulation.

Design Synthesis After simulation, synthesis is performed and the target technology (choice of a particular FPGA device family) is selected. The output of the synthesis process is creation of gate level netlist (Electronic Design Interchange Format - EDIF). The EDIF netlist is used as input file to Xilinx Implementation tool and specifies how the core will be implemented.

Design Implementation Design implementation includes the following steps: i) ii) Translate - EDIF netlist must be converted into Native Generic Database file (NGD) Map the UCF(User Constraint File) file is an input into a MAP program that maps logical design to Xilinx FPGA. Place and Route(PAR) the mapped design is ready to be placed and routed. The output is a fully routed NCD file.

iii)

The implement design process generated review reports such as Map report and PAR report. To improve the design, changes can be made at process properties, constraints and source files.

Program onto FPGA Programming on the Xilinx device can be made as follows: Creation of a programming file (BIT) to program FPGA Generate a PROM, ACE, JTAG file for debugging or to download to device Use iMPACT to program the device through programming cable.

Xilinx FPGA, as an SRAM-based programmable PLD, must be configured with the configuration bitstream. The configuration bitstream is generated from the fully routed NCD file, by means of a BitGen program.

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ELE655 LAB MANUAL

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EXPERIMENT 1: COMBINATIONAL LOGIC BLOCKS (MULTIPLEXER AND INCREMENTER)

Objective: To implement and test multiplexer and incrementer in Instruction Fetch (IF) of MIPS. The series of labs will be conducted in this course and it has ultimate objective to implement and simulate in Verilog the MIPS pipeline datapath.

(a)Multipler

(b) Incrementer by 1

IF Stage Figure 1 IF Stage in MIPS and its components (a) multiplexer (b) incrementer

In lab #1, you are required to write modules for multiplexer and incrementer as given in Figure 2.. Once these modules have been written, write their test benches to simulate possible inputs as provided in Figure 3. Synthesize the modules and capture the RTL schematic of the modules.

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ELE655 LAB MANUAL

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Source files

module mux ( a , b , s e l , y ) ; input[31:0]a,b; inputsel; output[31:0]y; assigny=sel?a:b; endmodule

module incr ( pcin , pcout ) ; i n p u t [ 3 1 : 0 ] pcin ; o u t p u t [ 3 1 : 0 ] pcout ; a s s i g n y = pcin + 1 ; endmodule

(a) (b) Figure 2 (a) Verilog Code for multiplexer Testbenches:

i n c l u d e mux . v module t e s t mu x ; / / Wire P o r t s wi r e [ 3 1 : 0 ] Y; / / Re g i s t e r De c l a r a t i o n s r e g [ 3 1 : 0 ] A, B; regsel; MUX mux1 ( Y, A, B, s e l ) ; / / i n s t a n t i a t e t h e mux initialbegin A = 32 hAAAAAAAA; B = 32 h55555555 ; s e l = 1 b1 ; #10 ; A = 32 h00000000 ; #10 s e l = 1 b1 ; #10 ; B = 32 hFFFFFFFF ; #5 ; A = 32 hA5A5A5A5 ; #5 ; s e l = 1 b0 ; B = 32 hDDDDDDDD; #5 ; s e l = 1 bx ; end a lways @(A or B or s e l ) #1 $ d i s p l a y ( At t = %0d s e l = %b A = %h B = %h Y = %h , $ t ime , s e l , A, B, Y) ; endmodule / / t e s t includeincr.v module t e s t ( ) ; / / P o r t Wi res wi r e [ 3 1 : 0 ] IncrOu t ; / / Re g i s t e r De c l a r a t i o n s r e g [ 3 1 : 0 ] A; INCR i n c r 1 ( I n c rOu t , A) ; / / i n s t a n t i a t e t h e i n c r eme n t e r initialbegin #10 A=3; #10 ; A=15; #10 A=64; #5 ; end a lways @(A) #1 $ d i s p l a y ( Time = %0d\tA=%0d\ t I n c rOu t=%0d , $ t ime , A, I n c rOu t ) ; endmodule / / t e s t

(b) Verilog Code for incrementer

Figure 3 Testbench for multiplexer and incrementer

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