EXPERIMENT 3 ALGORITHMIC STATE MACHINES (ASM) PURPOSE: Getting acquainted with ASM charts

1. BACKGROUND INFORMATION: An Algorithmic State Machine (ASM) chart is a special type of flowchart developed to define digital hardware algorithms. It has three main elements:

A state box with all the decisions and conditional boxes connected to its exit path are called and ASM block. All the operations in an ASM block are carried out simultaneously within one clock cycle. Here, this is the most important point to pay attention. The operations are not handled one by one as in the usual flowchart process; the operations take place in the same time period. 1.1 DESIGN PROCEDURE Data processor design: The elements needed to design the data processor are directly seen from the state and conditional boxes. Control circuit design: The control logic is determined from the decision boxes and required state transitions. For 2n states in ASM chart, we need n ffs in control circuit. First a state table is constructed depending upon the ASM chart. Then some different techniques may be used: 1) With the JK ffs: Looking at the sequence of states we implement that sequence by determining the necessary values for J and K inputs of ffs. From the outputs of ffs, the binary states are supplied. 2) With D ffs: Same operations done by D ffs. In both JK and D cases, we may insert a decoder at the output of ffs, to obtain the binary states (T0 T1, etc.).

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3) One ff/state: Here, we spend more ffs but the design is straight-forward by looking at the ASM chart. 4) With MUX: Implementation with MUX brings a more systematic solution to the problem. Here there are levels, the MUX level determines the next state, the register level (may be implemented by ffs) holds the present state and the decoder provides the binary states. Example: (Mano, Digital Design, Question 8.12) Design a digital system with three 4-bit registers, A, B, and C, to perform the following operations: 1. 2. 3. 4. Transfer two binary numbers to A and B when a start signal (S) is enabled. If A<B, shift-left the contents of A and transfer the result to register C. If A>B, shift-right the contents of B and transfer the result to register C. If A=B, transfer the number to register C unchanged.

Available Hardware: - one 4-bit register with shift-left, output-enable, and load inputs. - one 4-bit register with shift-right, output-enable, and load inputs. - one 4-bit register with load input. - one 4-bit comparator. - one 2x1 4-bit MUX. Solution: Sm means A<B L means A>B LOADA = T0S LOADB = T0S SHLA = T1Sm SHRB = T1Sm*L LOADC = T2 + T3 SEL = T3 OEA = T2 OEB = T3

Present State Name T0 T0 T1 T2 T1 T3

G1G2 00 00 01 10 01 11

condition S Sm L 0 - 1 - - 1 - - - 0 - - -

G1G2 00 01 10 00 11 00

Next State Name T0 T1 T2 T0 T3 T0

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Data Processor

Control Unit implementation: 1) with JK ffs:

S 0 1 Sm 1 0 L G1G2 00 00 01 10 01 11 G 1G 2 00 01 10 00 11 00 JG1 0 0 1 X 1 X KG1 X X X 1 X 1 JG2 0 1 X 0 X X KG2 X X 1 X 0 1

JG1 = G2 JG2 = G1S

KG1=1 KG2= G1+ G2Sm

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2) with D ffs: DG1 = G2G1 DG2 = SG1G2+ SmG1G2 3) one ff/state: DT0= T0S+ T3 + T2 DT1= T0S DT2= T1Sm DT3= T1Sm 4) with MUX & decoder:

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2. PRELIMINARY WORK: A system which tests 4-input NAND gates is to be designed. There is a START signal which should appear as a pulse. There will be two outputs, OK and FAULT, to display whether the tested gate operates well or not. The system operation will be as follows: 1. Wait for the START signal to go high. 2. Wait for the start signal to go low after high (i.e. complete the pulse); initialize the OK and FAULT ffs to zero. 3. Test the connected NAND gate, and turn on the OK ff if the gate operates well. If not then turn on the FAULT ff. 4. Go to step 1. The test (step 3) will take place as follows: All 16-input combinations will be generated by a 4-bit counter (74161), and applied to the gate to be tested. These input combinations will be applied to a reference NAND gate at the same time. The outputs of these two gates will be compared by using an equivalence gate which generates a signal called SAME. It is seen that the SAME signal will be high if the response of the tested NAND gate to an input is true, low otherwise. After all the combinations are tested, if all 16 combinations have worked well, the OK ff will be set. During the trial of input combinations, if a fault occurs (i.e. the SAME signal is low) the FAULT ff is immediately set and the control returns to the initial state (step 1) without trying the rest of the input combinations. The block structure of the system will be as follows:
CLK CLEAR START CONTROLLER ENDCNT Reference NAND SAME CONTROLLER NAND gate to be tested CLK COUNT

T0 T1 T2

J-OK CLK K-OK

OK

SET

J-FAULT CLK

FAULT

SET

CLR

K-FAULT

CLR

DATA PROCESSOR

The functions of the signals are as follows: CLK: The system clock. START: The signal to start the test procedure. It should go high and then low to start the procedure. CLEAR: To set the counter to zero. (active low) COUNT: To advance the counter, i.e. pass to a new input combination. (This signal can be connected to one of the ENABLE inputs of the counter.) ENDCNT: To indicate that all input combinations are applied. (The CARRY-OUTPUT of the counter may be used for this purpose.) J, K-OK, J,K-FAULT: To set and reset the OK and FAULT outputs when necessary. SAME : High when the outputs of the test gate and the reference gate are same, low otherwise.

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IMPORTANT NOTICES! The system may be implemented in three states. Your design should not exceed four states. The control circuits should be designed by using a MUX and a decoder. Your MUX will be 74153. It is a dual 4-to-1 MUX with common select signals. Decoder will be 74138. Although it is a 3-to-8 decoder, you will use it as a 2-to-4 decoder. Please have a look at the catalog for them.

3. EXPERIMENTAL PROCEDURE: 1. Construct and test only the control circuit for your design by supplying the necessary signals manually. 2. Construct the data processor, too, and test the system as a whole. Parts List: -

74153 74138 74161 7474 7476 7404, 7400, 7410, 7420, 7486