Testing - LAB 1

Goal Learn 1) 2) 3) 4) ho to use TetraMAX for: Reading the circuit. Generating the fault list. Generating test patterns. Running fault simulation.

Assignment Part 1 Given the 32-bit adder in lab1/add32_gate.v you are asked to use TetraMAX for computing the circuits testability. Part 2 Given the 32-bit adder in lab1/pipeline_gate.v you are asked to use TetraMAX for computing the circuits testability. Hints Introduction Before starting a new lab experiments using TetraMAX the following steps MUST be performed. 1) Connect to the server via SSH (use the password provided by the lab instructor):
ssh X test_02NPBOV@viona.polito.it 2) Set the proper environment by running: source /lab1/source.me 3) Create a new directory by running: mkdir <student ID>_lab1 4) Enter the newly created directory by running: cd <student ID>_lab1

5) Link the TetraMAX library by running the following command (mind the full stop at the end of the command line):
ln s ../lab1/tmax_pdt2002.v .

Part 1 After the introductory steps as detailed above, run the following commands: 1) Link the source file needed by the assignment by running: 2) 3) Load a. b. c. d. e. f. 4) Load a. b.
ln s ../lab1/add32_gate.v . Run TetraMAX by running: tmax &

the TetraMAXs library as follows: Click on tab NetList Click on tab Browse Select tmax_pdt2002.v and click on Open Select Library modules Select in the Case sensitivity menu the option Insensitive Click on Run the circuit as follows: Click on tab NetList Click on tab Browse

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c. Select add32_gate.v and click on Open d. Select in the Case sensitivity menu the option Insensitive e. Click on Run Generate the TetraMAX internal database, by clicking on Build and on Run Run the design rule checking by clocking on DRC and Run. In case all the steps are performed correctly the following message is displayed: No violations occurred during DRC process. Generate the fault list as follows: a. Select in the Faults menu the Set Fault Options b. Select the Stuck fault model and click on OK c. Select in the Faults menu the option Add Faults d. Select the option All and click on OK. In case everything is performed correctly the following message is displayed 2824 faults were added to fault list. Generate the test patterns as follows: a. Click on ATPG b. Click on Run. After few seconds the program displays a log message listing the number of detected faults, which should be 100.00% for the considered circuit. Save the test patterns as follows: a. Select in the Patterns menu the option Write Patterns b. Type in the Pattern file name field, the name of the file that will store the generated test vectors c. Select in File format list the option STIL d. Click on OK.

It is now possible to run the fault simulation as follows: 10) If not performed yet, executed the steps from 1) to 6) described above 11) Select in the Pattern menu the option Set Pattern Options 12) In the Pattern Source section, select External and in the Pattern file name field select the file name previously used to save the test vectors 13) Click on OK 14) Click on Fault Sim 15) Select Combinationa/Fast-Seq 16) Select in the Fault source section the option Add all faults 17) Click on Run. TetraMAX will fault simulate the generated test vectors and will display the attained fault coverage. Parte 2 After having setting-up the directory as descrive before, you are asked to execute circuit reading and build as done in part 1. Since the design is a sequential design, the DRC should be performed as follows: 1) Click on DRC for defining clock and reset signal of the considered design. 2) Click on Quick STIL 3) In the Port name: list select clk as circuits clock 4) In the Off: list select 0 for specifying that the signal is inactive when low, then click on Add 5) In the Port name: list select rstn as clock signal for the circuit.

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In the Off: list select 1 for indicating that the signal is inactive when high (for the adopted library the reset of memory element is active when low), then click on Add Click on OK Click again on DRC, select the DRC tab In the Init. DFF/DLATs to: list select 0 as initial value for the memory elements of the circuit Click on RUN Click on ATPG In the Fault source section select Add all faults In the General ATPG Settings tab, enable Enable Full-Seq ATPG Click on Full-Seq for running the sequential ATPG.