EMT 351 Digital IC Design

SA 2011/2012

Solution In-class Exercise Question 1

codes = 9h1E5 final = 1h0

Question 2

a b

0 1 0 S0 1 y

c d

0 1 S1

S0

Question 3 4-to-1 mux, 2-bit input, 2-bit selector, select

module mux41 (Z, A, B, C, D, select); input [1:0] A, B, C, D; input [1:0] select;

EMT 351 Digital IC Design

SA 2011/2012

output [1:0] Z; ... endmodule

(i)

case statement
reg [1:0] Z; always@(A or B or C or D or select) case (select) 0: Z = A; 1: Z = B; 2: Z = C; 3: Z = D; default: Z = 2bx; endcase

(ii)

conditional if-else statement

reg [1:0] Z; always@(A or B or C if (select == if (select == if (select == if (select == or D or select) 2b00) Z = A; else 2b01) Z = B; else 2b10) Z = C; else 2b11) Z = D; else Z = 2bx;

(iii)

conditional operator (? .. :)
wire [1:0] Z; assign Z = (select == 2b00) ? A : (select == 2b01) ? B : (select == 2b10) ? C : (select == 2b11) ? D : 2bx;

Question 4 8-to-3 encoder with output ERROR (ERROR = 1 for invalid inputs)
module encoder38 (A, B, C, D, E, F, G, H, Code, ERROR); input A, B, C, D, E, F, G, H; output [2:0] Code; output ERROR; reg [2:0] Code; reg ERROR; always@(A or B or begin ERROR = 0; case ({A, B, C, 8'b0000_0001: 8'b0000_0010: C or D or E or F or G or H)

D, E, F, G, H}) Code = 0; Code = 1;

EMT 351 Digital IC Design

SA 2011/2012

8'b0000_0100: Code = 2; 8'b0000_1000: Code = 3; 8'b0001_0000: Code = 4; 8'b0010_0000: Code = 5; 8'b0100_0000: Code = 6; 8'b1000_0000: Code = 7; default: begin Code = 3'bxxx; ERROR = 1; end endcase end endmodule

Question 5

Question 6 Rewrite the function block as: (i) another module

module next_count (count, direction); output [3:0] count; input direction; reg [3:0] int_count; always@(direction) begin if (direction) int_count = count + 1; else int_count = count 1; end assign count = int_count; endmodule

(ii)

task
task next_count; output [3:0] count; input direction; reg [3:0] count; begin if (direction) count = count + 1; else count = count 1; end endtask

EMT 351 Digital IC Design

SA 2011/2012

Question 7 State transition diagram of 110/101 sequence detector

reset got0 [0] 0

got1 [0] 0 1 got11 [0] 0 1

got10 [0] 1 0

got101 [1]

got110 [1]

module detector (clk, m, reset, out); input clk, m, reset; output out; reg [5:0] state, nextstate; parameter parameter parameter parameter parameter parameter got0 = 6b000001; got1 = 6b000010; got11 = 6b000100; got110 = 6b001000; got10 = 6b010000; got101 = 6b100000;

always@(posedge clk or posedge reset) if (reset) state <= got0; else state <= nextstate; always@(state or in) case(state) got0 : if (m) nextstate <= got1; else nextstate <= got0; got1 : if (m) nextstate <= got11; else nextstate <= got10;

EMT 351 Digital IC Design

SA 2011/2012

got11 : if else got110 else got10 else got101 else default endcase

(m) nextstate <= got11; nextstate <= got110; : if (m) nextstate <= got101; nextstate <= got0; : if (m) nextstate <= got101; nextstate <= got0; : if (m) nextstate <= got11; nextstate <= got10; : nextstate <= got0;

assign out = (state ==got110) || (state == got101)? 1 : 0; endmodule

Question 8 (i) Design of 5-to-1 multiplexer, Mux51

module Mux51 (Temp_A, Temp_B, Temp_C, Temp_D, Temp_E, Selector, Sel_Temp); input [7:0] Temp_A, Temp_B, Temp_C, Temp_D, Temp_E; input [2:0] Selector; output [7:0] Sel_Temp; reg [7:0] Sel_Temp; always@(*) case(Selector) 0: Sel_Temp = Temp_A; 1: Sel_Temp = Temp_B; 2: Sel_Temp = Temp_C; 3: Sel_Temp = Temp_D; 4: Sel_Temp = Temp_E; default: Sel_Temp = 8bx; endcase endmodule

(ii)

Design of comparator, Compare2.

module Compare2 (Sel_temp, Tref, Green, Yellow, Red, Alarm); input [7:0] Sel_temp, Tref; output Green, Yellow, Red, Alarm; reg Green, Yellow, Red, Alarm; always@(*) begin Tref = 30; if (Sel_Temp < Tref) {Green, yellow, Red, Alarm} = 4b1000;

EMT 351 Digital IC Design

SA 2011/2012

else if (Sel_Temp == Tref || Sel_Temp < 50) {Green, yellow, Red, Alarm} = 4b0100; else if (Sel_Temp == 50 || Sel_Temp > 50) {Green, yellow, Red, Alarm} = 4b0011; else {Green, yellow, Red, Alarm} = 4b0000; end endmodule

(iii)

Complete (top-level) design of the alarm system, Alarm_System

module Alarm_System (Temp_A, Temp_B, Temp_C, Temp_D, Temp_E, Tref, Selector, Green, Yellow, Red, Alarm); input [7:0] Temp_A, Temp_B, Temp_C, Temp_D, Temp_E, Tref; input [2:0] Selector; output Green, Yellow, Red, Alarm; wire [7:0] Sel_Temp; Mux51 DUT1 (Temp_A, Temp_B, Temp_C, Temp_D, Temp_E, Selector, Sel_Temp); Compare2 DUT2 (Sel_temp, Tref, Green, Yellow, Red, Alarm); endmodule