510

A new Mixed-Mode Programming in PWM

Controllers
G.C. Ioannidis
*
, G. Charokopos
**
, P. Marabeas
**
and S.N. Manias
**
*
Technical Institute of Piraeus/Department of Electrical Engineering, Egaleo, Greece
**
National Technical University of Athens/Department of Electrical & Computer Engineering, Athens, Greece
AbstractIn this paper a new mixed (voltage and
current)-mode programming PWM controller is presented.
The proposed controller compares a control signal to the
error amplifier signal in order to command the switch to
turn off, while a constant frequency clock signal is utilized
to turn the switch on. In the case of peak current-mode
controller, the control signal is a combination of inductor or
most often switch current and a suitable compensation
ramp which in the most common applications is constant. In
the proposed controller, the constant compensation ramp
has been replaced by a ramp voltage which is derived,
charging an appropriate RC circuit from the output voltage
of the converter. The output impedance and audio
susceptibility transfer functions have been plotted and
presented for both controllers revealing the improved
behavior of the mixed-mode controller. Furthermore, like in
peak current-mode control, sub-harmonic oscillations
inherent to these control schemes, are predicted and avoided
using an appropriate condition and extended validity Bode
diagrams taking into consideration the well known sampling
effect. To verify the theoretical analysis and conclusions, the
two control schemes have been simulated considering step
load and reference changes.
I. INTRODUCTION
Up to a significant point, the dynamic characteristics of
a DC to DC converter are determined by the design of its
controller. The basic aim of control engineers is to design
a stable and a fast in response closed-loop converter. The
designers need a simple and intuitive model, enhanced
with the critical features from sampled-data modeling
which are easy to apply. This will allow
a) to model and predict control transfer functions with
greater accuracy,
b) to select the proper compensation ramp,
c) to use a single small-signal model for both the
control transfer functions and current loop
stabilization and
d) to decide if it is needed to add a ramp to the power
circuit, and how much to add.
Voltage and current programmed switching power
supplies have been used for many years in the industry
([1]-[6]). The procedure of modeling voltage and current
programmed converters have been presented in a
significant number of papers ([7]-[11]) in the past and
today as well.
The peak current mode control method was and still is
very popular among power supply designers. It is a
control technique which uses two control loops, an inner
current control loop and an outer loop for voltage control.
The outer voltage control loop defines the level at which
the inner loop regulates peak current through the switch
and the filter inductor. This method presents many
advantages like:
a) Input voltage feed-forward, resulting in good open-
loop line regulation.
b) Simplified loop as inductor pole and 2nd order
characteristic are eliminated.
c) Optimum large-signal behavior.
d) No conditional loop stability problems.
e) Automatic pulse-by-pulse current limiting.
f) Less complexity/cost (current sense/amplifier is not
an added complication).
On the other hand, certain disadvantages are:
a) The peak current error and instability, which is
solved with the well known slope compensation.
b) Worse noise immunity because of shallower ramp.
The noise immunity problem is solved by using care in
circuit layout and proper location of ground returns to
avoid pulses generated by fast switched high currents
through wiring inductance, using differential input current
sense amplifiers, using a small filter inductor (consistent
with keeping out of the discontinuous mode at minimum
load current), and by filtering out any remaining noise
spikes with a simple RC filter at the input of the current
sense amplifier.
In the classic peak current-mode controller, the current
programming signal is compared to the voltage error
signal to command the switch off, resetting an appropriate
S-R latch. The switching frequency is kept constant using
a clock signal, which initiates the on time of the switch.
On the other hand, the proposed mixed-mode PWM
controller uses a ramp voltage, which is produced by the
charge of an R-C circuit from the output voltage of the
converter. The values of R and C are chosen in such way
so that the produced ramp is almost linear. As in peak
current-mode control, an S-R latch and a clock signal are
utilized to keep the switching frequency constant.
The phenomenon of sub-harmonic oscillations inherent
to peak current mode control is well known and many
authors have proposed methods of analysis and actions to
avoid it ([1], [7], [12], [13] and [14]). At duty cycles
approaching 50% and beyond, the peak current is
regulated at a fixed value, but the current will oscillate
back and forth on subsequent switching cycles. Current-
mode oscillation, like any other undamped oscillation, will
continue to ring and grow in amplitude under some
conditions. If it is damped, as it is achieved through slope
compensation, the oscillations decrease and die out.
The intermittent operation of converters using peak
978-1-4244-1668-4/08/$25.00 2008 IEEE
511
current-mode control has been examined in [16].
According to this reference the phenomenon that
incorporates a coupling process through which a spurious
signal is coupled to the current sensing and ramp
compensation circuitry, results in a modulation of the
compensation slope, which causes the system to become
unstable intermittently. When the spurious signal
frequency is sufficiently close to an integer multiple of
the switching frequency and the spurious signal is strong
enough, intermittent operation occurs.
According to [15] switching instabilities in peak-
current controlled PWM converters can be predicted in
averaged models without the inclusion of the sample-and-
hold effect. In the proposed control technique the
previous finding is not confirmed for the averaged model
used for analysis purposes while inserting a sampling
effect block in the current-loop, a reliable and confirmed
(using simulation results) stability condition is derived.
The proposed new mixed-mode controller is applied for
the case of the buck converter and using accurate Bode
diagrams, in which the sampling effect inherent to current
mode control is included, the sub-harmonic oscillations
are predicted and avoided. The new controller is compared
to the classical peak current-mode controller in terms of
load and reference transient conditions.
II. SMALL-SIGNAL LINEAR MODEL
The application of either the classical control method or
the proposed one requires a linear system. For this reason,
the nonlinear system of the buck converter is linearized
around a working point considering perturbations for the
time depended variables. The small-signal linear averaged
model for the buck converter is given by the next set of
equations in matrix form ([17]):
( ) ( )
( )
1 1
1
1 1 1
0 0
0
m C m
L
m C m C L L
C m
C
m C m C
m C
in in
m C
o
m
m C
L m C m m
o
m C m C C
R R R
R
L R R L R R i i
v R
v
R R C R R C
R R
D V v
L L R R L
i
R
d
R R C
i R R R R
v
R R R R v
-
-
( | |
+
( ( |
+ + (
\ . ( (
= +
(
( (

( (

+ +
(

(
(
(
+
(
(
+
(
(
(
(

+

( (
= +
( (
+ +

0
in
C
o
m C
v
R
i
R R
d
(
( (
( (
+

(

(1)
where
C
v = the perturbation of the output capacitor voltage
around the DC value V
C
;
L
i

= the perturbation of the inductor current around the

DC value I
L
;
d

= the perturbation of the duty cycle around the DC

value D;
in
v = the perturbation of the input voltage around the DC
value V
in
;
In order to compare the conventional and the new
control scheme the following parameters for the buck
converter are given:
DC input voltage V
in
= 24 V;
DC output voltage V
o
= 15 V;
Switching frequency f
s
= 100 kHz;
C = 470F
L = 33H;
R
c
= 50 m
R
L
= 60m
R
m
=3 to 15.
Current sense resistor r
f
= 0.1
III. PEAK CURRENT-MODE PROGRAMMING
CONTROLLER
The classical peak current-mode programming (PCMP)
controller is presented in Fig. 1. The current programming
signal v
c
is compared to the error signal v
e
to command the
switch off resetting the S-R latch. A constant frequency
clock initiates the on time of the switch. Furthermore, an
external ramp is added to the current waveform in order to
stabilize the current loop and to improve the dynamic
behavior of the converter.
Equating the v
c
signal to the error signal v
e
and
separating the dc and ac components, the small signal duty
ratio of the proposed controller is estimated and given in
the next equation:
( ) /
m e f e L o in
d F v r H i H v v ( = +


(2)
where
( )
2
1
m
s o
LD
F
nTV D
=

( )
2
D
1
o
H
nV D
=

T
s
= 1/f
s
2
s s
2
1 (sampling effect block, [8]);
e
n z n
H
Q e e
= + +
/
n s
T e t =
2/
z
Q t =
1 2 /
c I
n M M = +
M
I
= on-time slope of the sensed inductor current
M
C
= the compensation slope.
The block diagram of the PCMP controller for the buck
converter is presented in Fig. 2.
512
Figure 1. PCMP controller
The sub-harmonic oscillations inherent to peak current
mode control are avoided if the next inequality is valid
([1]):
1
(1 )
D
n D
<

(3)
The PCMP voltage controller is designed and
optimized, in terms of phase and gain margin achieving a
crossover frequency of 10.3 kHz and a phase margin of
80
o
. The amount of slope compensation is set to 100% of
the inductor current downslope in order to diminish the
peaking of the loop-gain ([8]). The derived controller is
given in the next equation:
( )
( )
1 / 2 156
2878
1 / 2 7230
PCMP
s
K
s s
t
t
+
=
+
(4)
The voltage loop controller includes integral action to
improve the steady-state behavior of the power converter
and a low-frequency zero to limit the action of the
integrator, increasing the magnitude and the phase lag of
the loop gain and consequently, better dynamic response
is achieved. Finally, a medium frequency pole has been
added to diminish the crossover frequency and increase
the rate that the loop-gain transfer function is attenuated,
reducing high-frequency noise as well.
IV. MIXED-MODE PROGRAMMING
CONTROLLER
In Fig.3, the new mixed (voltage and current)-mode
programming (MMP) controller is presented. In this
controller, the signal compared to the voltage error is a
combination of the inductor current and an almost linear
ramp derived from the output voltage. This ramp (saw-
tooth) is produced using an appropriate RC circuit in
which the time constant is assumed to be much greater
than the switching period. During the time interval in
which the output of the controller is high, the capacitor is
charged from the output voltage of the converter. As soon
as the output of the controller becomes low, the capacitor
is discharged through the diode D. The inductor current is
turned into a voltage through a sense resistor R
s
, and is
added to the saw-tooth ramp to generate the control
voltage v
c.
According to Fig. 3, the mixed programming signal v
c
is
given by the following equation:
Figure 2. Block diagram of PCMP controller for the buck converter
1 2
1 2 3
( )
( )
( )
1 1 1
r s
L
c
v t R
I t
R R
v t
R R R
+
=
+ +
(5)
By setting
o 1
(6) /
v
k R R =
3
1 / 1 / 1 / 1 /
1 2 o
R R R R + +
2
/ r R R R
(7) =
f o s
= (8)
M 1 /
v
RC =
S
(9)
equation 5 becomes:
( )
( ) ( )
/ 2
c v r f L
v v o f L I s
v k v t r i t
k M v d r I m dT
= + =
= + +
(10)
where
0
( )
r V
v t M V dT =
0 in
I
V V
m
L

=
Equating the v
c
signal to the error signal v
e
and
separating the dc and ac components, the small signal duty
ratio of the proposed controller is estimated and given in
the next equation
/
m e f e L m o i
d F v r H i H v H v (
n
= +


(11)
Figure 3. MMP controller
513
where
F
m
, H
e
and are the same blocks as in peak current-
mode programming while
( )
2
1 2
1
m v
o f
D L
v
H k M
nV D r
| |
= |
|

\ .
1 2
(1 )
v v
f
n k M
r D
= +

L D
V
)
The block diagram of the MMP controller for the buck
converter is presented in Fig. 4.
The stability of the MMP controller for the buck
converter is examined applying the Ruth stability
criterion to the current closed-loop system of Fig.4. The
sampling effect block plays a significant role in
generating a stability criterion. In case the sampling effect
is not included, the derived formula does not predict the
sub-harmonic instabilities which occur as the simulation
results denote.
For the derivation of the stability criterion, the error
voltage to output voltage open-loop transfer function
0
has to be estimated. By setting
the denominator D(s) to zero, the characteristic
polynomial is formed as follows:
( ) / ( ) / ( )
e
G s v v N s D s = =
3 3
3 2 1 0
0 p s p s p s p + + + = (12)
where
3
2
m m f in
p C F R r =
2
2
2 ( 2
f m in s m s m in
p r F V Cf R f L F V t ( = + +

| | { }
2
1
2 (
s f m in s C L m in m C in m
p f r FV f L CR R R FV H R V t = + + )
1 (

( )
2 2
0
2
s f C L m in m C in m in m
p f r R R F V H R V R H V t = + + + +

The coefficients of the characteristic polynomial form

the following array known as Rouths array.
3 1 3
2 2
2 1 0 3
1
2
0
0
0
0
0
p p
s
p p
s
p p p p
s
p
s
p

(13)
According to the Routh-Hurwitz stability criterion, the
system is stable if the elements of the first column of the
above array have the same sign. Since p
3
is always
negative, p
2
, (p
2
p
1
p
0
p
3
)/p
2
and p
0
should be also
negative.
Algebraic process of the above formulas leads to the
following approximate stability criterion:
2
s s
m
in in
f L f L
F
V V
<~ <~
D
(14)
The specific controller presented in Fig. 3, is designed
using the following parameters:
Figure 4. Block diagram of MMP controller for the buck converter
R
1
= 10k
R
2
= 1k
R
3
= 10k
R
s
= 0.1
R
r
= 4.1k
C
r
= 10nF,
Using the above numerical values, equation 14 yields:
0.1070 0.1991 0.2200 <~ <~
The value of F
m
is well inside the limits of stability
therefore, the proposed controller is stable.
Next, the MMP voltage controller is designed and
optimized again in terms of phase and gain margin
achieving a crossover frequency of 16.5 kHz and a phase
margin of 80
o
.
( )
( )
1 / 2 156
3511
1 / 2 7374
MMP
s
K
s s
t
t
+
=
+
(15)
The Bode diagrams of the voltage loop-gain transfer
functions for both the control schemes are presented in
Fig. 5. The output impedance and audio susceptibly
transfer functions for both control schemes closing only
the current-loop are presented in Fig. 6 and Fig. 7
respectively. By inspection of these figures, it is evident
the improvement of MMP controller compared to PCMP
controller, as it presents better line rejection ratio and
smaller output impedance at low frequencies.
V. SIMULATED RESULTS
The buck converter employing the two control schemes
was simulated in order to confirm the results of the above
analysis and conclusions. The simulated transient
response of the buck converter employing the PCMP
controller and the proposed MMP controller for a step
change of the load, from 5 to 3 , is presented in Fig. 8
and Fig. 9. Furthermore, the response of the two
controllers concerning a step change of the reference
voltage, from 15V to 15.5V, is presented in Fig. 10 and
Fig. 11.
By inspection of these four figures, it is evident that the
proposed controller yields to a system exhibiting better
dynamic characteristics like: low output impedance and
high bandwidth. At the same time, there is neither ringing
nor excessive overshoot on the voltage and current
waveforms.
514

MMP
MMP
PCMP
PCMP
Figure 5. Bode diagrams of the voltage loop-gain transfer function for
PCMP and MMP controllers
10
0
10
1
10
2
10
3
10
4
10
5
-30
-20
-10
0
10
frequency in Hz
v
o
(
s
)

/

i
o
(
s
)

i
n

d
b
- PCMP - - - - - -
_______
MMP
Figure 6. Output impedances for PCMP and MMP controllers with the
current-loop closed and the voltage-loop open

frequency in Hz
v
o
(
s
)

/

v
i
n
(
s
)

i
n

d
b
- - - - - - - PCMP
MMP
_______
Figure 7. Line rejection transfer functions for PCMP and MMP
controllers with the current-loop closed and the voltage-loop open
Figure 8. Simulated waveforms for output voltage v
o
for a step change
of the output load (from 5 to 3) of the buck converter using PCMP
and the proposed MMP controllers
Figure 9. Simulated waveforms for inductor current i
L
for a step change
of the output load (from 5 to 3) of the buck converter using PCMP
and the proposed MMP controllers
Figure 10. Simulated waveforms for output voltage v
o
for a step change
of the reference voltage (from 15V to 15.5V) of the buck converter
using PCMP and the proposed MMP controllers
F
igure 11. Simulated waveforms for inductor current i
L
for a step change
of the reference voltage (from 15V to 15.5V) of the buck converter
using PCMP and the proposed MMP controllers
VI. CONCLUSION
A new mixed (voltage and current)-mode
programming PWM controller is presented in this paper.
The proposed controller is compared to the classical peak
current mode one. The two control methods are suitably
applied to the buck converter so that almost the same
phase margin is achieved. From the simulated results, it is
evident that the proposed MMP controller is faster in
response for reference voltage and load changes as well.
515
The stability of the proposed controller is also
examined and a simplified stability criterion has been
estimated. Furthermore, the application of the new
controller leads to a converter which exhibits better audio
susceptibility and smaller output impedance, especially in
the low frequency region. Finally, the implementation of
the proposed method is simple while its cost is kept low.
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