European Journal of Scientific Research ISSN 1450-216X Vol.26 No.2 (2009), pp.305-314 EuroJournals Publishing, Inc. 2009 http://www.eurojournals.com/ejsr.

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Design and VLSI Implementation of 8 Mb Low Power SRAM in 90nm

Sreerama Reddy G.M Professor and HOD, ECE Department Sri Venkateshwara College of Engineering and Technology RVS Nagar, Chitoor, AP, India - 517127 E-mail: sreeramareddy90@gmail.com Tel: +91-08572-233779, +91-9885888273 P. Chandrashekara Reddy Professor, ECE Department, JNTU College of Engineering Kukatapally, Hyderabad E-mail: csrputha@yahoo.com Tel: +91-4023052595 Abstract This paper deals with the design and analysis of 8Mb Static Random Access Memory (SRAM) at 90nm, focusing on optimizing power and delay. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). Techniques to optimize both of these paths are investigated and implemented. In this work the existing SRAM architectures are investigated, and then a basic 6T SRAM structure was chosen. The decoder, excluding the predecoder, which constitutes the path from address input to the word line rise, is implemented as a binary structure by implementing a multi-stage path. For fast lower power solutions, the heuristic of reducing the sizes of the input stage in the higher levels of the decode tree allows for good trade-offs between delay and power. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines. While designing the SRAM, techniques such as circuit partitioning, gate oxide thickness variations and low power layout techniques are made use of to minimize the power dissipation. The mask design of the constituent memory blocks is done using virtuoso tool, the DRC & LVS verified through Hercules/Calibre and finally, the characterization is done on single bit SRAM cell to determine the cell characteristics (mainly power) in static as well as dynamic modes. The results obtained after performing the characterization of a single bit SRAM cell are presented in this paper.

Keywords: Low power, SRAM, 90 nm, 6T SRAM cell.

1. Introduction
Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and,

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consequently, toward higher storage densities. This project deals with design of low power static random-access memory (RAM) cells and peripheral circuits for standalone RAMs, in 90nm focusing on stable operation and reduced leakage current and power dissipation in standby and active modes.
Figure 1: Detailed view of 8Mb SRAM memory

The detailed view of the designed 8Mb SRAM memory block is as shown in Fig 1, this total block is built up of two 4Mb memory cuts along with decoding sections and control logics for proper operation of the memory. In this project work, emphasis is laid on minimizing power consumption. The decoding logic is implemented as a tree (multi-stage path) to reduce power dissipation in active mode. To reduce the power in standby mode, adopting a multi-Vth technique reduces the leakage current [2]. As the technology shrinks (in Sub-micron technologies), the power issue becomes very prominent due to high transistor density, increased leakage currents and increase in interconnect parasitics. In spite of the cropping up of power issues, the power consumption can be reduced by adopting suitable techniques, such as circuit partitioning, increasing gate oxide thickness in non-critical paths, reducing Vth (dual Vth) etc. According to Benton H. Calhoun, Anantha Chandrakasan [2] a 90nm SRAM can be designed that functions into the sub-threshold region and examines the impact of process variation for low-voltage operation is described. He also depicts the impact of no: of transistors and their structure on the leakage power of the memory bit cell. The circuit partitioning technique also improves the speed of our memory. The control block, the decoders and IO blocks are all in low Vth, whereas the memory cells, the dummy column and dummy row along with the sense amplifier are in high Vth [1]. Having this kind of configuration has helped in gaining in speed and also reducing the dynamic and static power consumption by a considerable amount. The concepts of variation of threshold voltages and increased gate-oxide thickness [4], for reduced leakage currents due to subthreshold conduction and gate tunnel current are included, which assure the design of low-voltage random-access memory (RAM) cells and peripheral circuits for standalone SRAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. A number of researchers have studied the low power design of SRAM memories; they concluded that by circuit partitioning, variable Vth techniques and reducing capacitance along word lines, the power consumed in SRAM memories can be minimized.

307 1.1. Advantages and Uses of Low Power SRAM

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1.1.1. SRAMs are Basically used as Embedded memory, e.g.: First and second level caches in processors Data buffers in various DSP chips Standalone SRAMs: which can be integrated as an external memory during board design stage? Caches in computer systems Main memory in low power applications 1.1.2 Advantages of SRAM Memories Faster Data Access speeds. Standby power of SRAM memories is very low inspite of high density of transistors. SRAM cells have high noise immunity due to larger noise margins, and have ability to operate at lower power supplies.

2. Memory Architecture
The preferred organization for Random access memories is shown in Fig 2. This organization is random-access architecture which is an Asynchronous design. The name is derived from the fact that memory locations (addresses) can be accessed in random order at a fixed rate, independent of physical location, for reading or writing. The storage array, or core, is made up of simple cell circuits arranged to share connections in horizontal rows and vertical columns. The horizontal lines, which are driven only from outside the storage array, are called wordlines, while the vertical lines, along which data flow into and out of cells, are called bitlines. A cell is accessed for reading or writing by selecting its row and column. Each Cell can store 0 or 1. Memories may simultaneously select 4, 8, 16, 32, or 64 columns in one row depending on the application. The row and column (or group of columns) to be selected are determined by decoding binary address information. For example, consider a row decoder that has 2 n out-put lines, a different one of which is enabled for each different n-bit input code. The column decoder takes m inputs and produces 2 m bit line access signals, of which any of them can be enabled at one time. The bit selection is done using a multiplexer circuit to direct the corresponding cell outputs to data registers. In total, 2 n X 2 m cells are stored in the core array [9]. In this design, the number of rows and columns, both are equal to 64 for 4Mb memory cut. Using two such memory cuts, a 8Mb SRAM memory is designed.
Figure 2: SRAM Memory Architecture [1]

Design and VLSI Implementation of 8 Mb Low Power SRAM in 90nm 2.1. Details of Memory Design Flow
Figure 3: Design flow for 8Mb SRAM

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The design flow for the memory design is as shown in Fig 3 The design specification is obtained first and after the W/L values of the transistors are decided upon, the schematic entry is done in virtuoso schematic editor and the .cdl is streamed out to carryout pre-layout simulations. Through the Hspice pre-layout simulations, the W value for various transistors in the SRAM bitcell are determined and thereby the W/L values are now conformed and the mask design is done for the entire design, this procedure may require several small iterations to satisfy the DRC rules for 90nm and the leaf cells are designed in such a manner, that it will facilitate the higher level integration of the instances at top level or in the higher level hierarchies. Finally, all the blocks of the memory design are integrated to form a single memory cut and GDSII, parasitic extraction file and .CDL files are extracted and DRC is verified using CALIBRE and HERCULES along with performing the postlayout simulation of the design. And finally, the characterization is done for a single bit SRAM cell using HSPICE/Nanosim.

3. Low Power Design Techniques

In order to significantly reduce the power consumption in SRAMs all contributors to the total power must be targeted. The most efficient techniques used in recent memories are: Circuit Partitioning Techniques: In the circuit partitioning technique, a concept called divided word line is used by which the 64X64 memory array is partitioned into four 32X32 arrays, by this the capacitance along the wordlines reduces greatly and by the Capacitance reduction of wordlines, the number of cells connected to them, data lines, I/O lines and decoders act under reduced capacitance causing lesser power dissipation [1]. AC current reduction by using tree-decoding techniques (i.e. multi-stage static CMOS decoding) [7] under low voltage power supplies, In this technique, the decoder is implemented in a tree structure by which only specific paths along the decoder will be active, this technique reduces active power consumption. Leakage current reduction (in active and standby mode) by utilizing multiple threshold voltage (MT-CMOS) [2].In this low power technique, the decoder section is designed for high Vth operation, by which the leakage currents can be reduced, but the speed gets adversely affected.

309 3.1. Low Power Layout Guidelines [12]

Sreerama Reddy G.M and P. Chandrashekara Reddy

When beginning a cell layout, identify critical speed paths. These paths should be prioritized when designing the layout. Critical paths should follow these rules: 1 Run signals in metal. 2 Use poly only when necessary (as poly adds on lot of resistance). 3 Do not jump signals in diffusion. Analog circuits, such as sense amplifiers, need to have matched layout in critical areas. Generally, any metal line adjacent to a wide bus should have greater than minimum spacing to avoid lithography problems. Also, signal lines running a long distance should have greater than minimum width to reduce series resistance. Do not place contacts across the width of power bus metal line. Doing so reduces the effective width on the bus. Calculate the effective metal line width by subtracting the width of contacts placed in the paths. All cells should be DRC and LVS clean (except for recommended rules) before they are called complete. To reduce edge capacitance on the output node, divide wide gates into an even number of legs with the output node to the inside and power to the outside. Each leg should be kept short in order to minimize series gate resistance. The supply connections from IO ring or supply pad to the core must be wide. Metal width for routing should not be less than the width of the pin given in one core macro and filler connect cell in IO ring. If metal width for connections can be increased, it is an added advantage.

4. Results and Discussions

The schematic entry and the layout of the 8Mb SRAM is done using Virtuoso tool, this procedure may require several small iterations to satisfy the DRC rules for 90nm and the leaf cells are designed in such a manner, that it will facilitate the higher level integration of top cells. The schematic entry and the layout of the basic 2:4 decoder block is as shown in figure 4., which are done using virtuoso schematic editor and virtuoso layout editor, here the decoder layout is done on fixed frames to guarantee uniformity and ease of connections when used at higher hierarchies at top level design
Figure 4: Schematic and Layout level view of 2:4 decoder

The schematic entry and the layout of the basic SRAM bitcell is as shown in figure 5., which are done using virtuoso schematic editor and virtuoso layout editor, here the memory cells are stacked at the layout level, to form memory arrays.

Design and VLSI Implementation of 8 Mb Low Power SRAM in 90nm

Figure 5: Schematic and Layout level view of SRAM bitcell

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After the layout and schematic designs, the DRC and LVS procedures are verified on the designs along with the seal ring insertion and dummy layer inclusion in the total design.
Figure 6: Full Chip Layout level view of 8Mb SRAM

The full chip layout view of a 8Mb memory is as shown in Fig 6, the total memory is divided into two 4Mb memory cuts which are formed using stacked SRAM bit cells, of a single column, and many such columns are formed (64 columns for 4Mb memory cut) to constitute a 4Mb memory cut and integrating two such cuts, a 8Mb memory is built. The decoder section consists of decoding logics implemented in a tree structure and control block provides with precoded signal to support circuitpartitioning technique. 4.2. Characterization of SRAM Bitcell The characterization of cells can be defined as determining several cell attributes such as output transition times, propagation delays, switching power, leakage power, input pin capacitances in standby and dynamic modes. Power dissipation can be handled in terms of static power and dynamic power. Static power is the power that is dissipated when the cell is stable, that is, there is no signal transition on any inputs or outputs of the cell. Static power is dissipated in a number of ways. The largest consumption of static power results from source to drain subthreshold leakage. This leakage is caused by reduced threshold voltage that prevents the gate from turning off completely. Static power dissipation also occurs when current leaks between the diffusion layers and substrate. For this reason, static power is often called leakage power. Dynamic power is the power dissipated when a circuit is active. Dynamic power is divided into switching power and internal power. Switching power results from charging/discharging of load capacitance. Switching power is calculated by a gate level power analysis tool where the

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interconnect parasitic is known. Therefore, switching power is excluded from power characterization of cells. While input or output signals switch, power is also dissipated by internal capacitive charging/discharging and short circuit dissipation. Since this kind of power is dissipated in the cell during signal switching, it is called internal power. Here, the SRAM bitcell is characterized for mainly power, transition and delay times along with determination of static noise margin of SRAM bitcell.The SNM value is determined most easily from simulation by forcing the voltage on one of the internal nodes of the cell (q) from ground to the power supply and recording the response of the other node (qbar). The setup of the simulation should be constructed with the worst-case contact resistances, including the cells ground path. Repeating the measurement with the other side to generate two inverter transfer curves, which can be overlaid together on the same graph with one curve on the Xaxis and the other on the Y-axis. This diagram is referred to as Butterfly curve for the memory cell as shown in the below Fig 7.
Figure 7: Butterfly Structure for SRAM

Figure 8: Operation of SRAM Circuit.

As shown in Fig 8, the dynamic operation of SRAM circuit depends upon the inputs that need to be stored, here an input pulse is given as an input and the output transitions, delay and dynamic power are measured using Hspice simulations.
Figure 9: Bitline Voltage Swings

In the dynamic operating mode, the data content stored in the 6T SRAM is retrieved during the read operation, if its a zero stored in the bitcell, then the potential swing will be reducing to 916mV as

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shown in Fig 9. If a 0 is stored in the SRAM bitcell, the precharged potential vdd flows to the bitcell, this reduces the bitline voltages by few 100mv [10] as shown in Fig 9.
Figure 10: Leakage current in Standby mode

Standby Power = 7.76 microwatts/bitcell

To determine the leakage current in standby mode, the ground path is cut-off from the circuit, and two inputs a logic 1 and 0 are provided as input and currents at intermediate nodes is measured and average of these values is taken to find the value of leakage current.
Figure 11: Dynamic Power Characteristics

Peak power = 3.3704E-04watts/bitcell

The dynamic power dissipation characteristics for SRAM bit cell (both Average power and Peak power) are as plotted in Figure 5.5 using Hspice simulations. Dynamic power is the power dissipated when a circuit is active. Dynamic power is caused because of switching power and internal power. Switching power results from charging/discharging of load capacitance. Here in the above analysis, the peak-to-peak power of single bit SRAM cell is determined which shows at maximum switching and various parameters like, tphl, tplh, tr and tf are determined under dynamic conditions. After the SRAM bitcell characterization, the standby power, which is dissipated when there is no switching activity, is found to be 7.76 microwatts/bitcell and dynamic power dissipated during switching activity is determined as 3.3704E-04watts/bitcell.The results obtained after performing the characterization of a single bit SRAM cell are as mentioned in the table 1 and table 2, they exhibit the static and dynamic characteristics respectively,
Table 1:
Symbol Ileakage

Static Characteristics of SRAM Bitcell

Parameter leakage Current Conditions T 25C, 1.2v Value in uA 6.463

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Table 2:
Symbol talk tPHL tR tF Ppeak

Sreerama Reddy G.M and P. Chandrashekara Reddy

Dynamic Characteristics of SRAM Bitcell
Parameter Propagation delay from low to high Propagation delay from high low Rise time Fall time Peak Power Conditions 1.2 v supply mode 1.2 v supply mode 1.2 v supply mode 1.2 v supply mode 1.2 v supply mode Value 7.8503E-11seconds 5.6596E-11 seconds 1.3453E-11 seconds 1.6596E-11 seconds 3.3704E-04watts

5. Conclusions
This paper presents a 6T-based SRAM, which addresses the critical issues in designing a low power static RAM in deep sub micron technologies along with the design techniques used to overcome them. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). Techniques to optimize both of these paths are investigated and implemented. With appropriate circuit partitioning, transistor sizing, choice of a suitable Sense Amplifier, it was possible to achieve a high speed SRAM memory that doesnt dissipate too much power. A basic 6T SRAM structure is chosen for designing the SRAM bitcell, after this, the Layout optimization techniques are identified and low power design techniques such as circuit partitioning and multi-stage decoder are implemented in the SRAM design. After the mask design procedure, the GDSII and .CDL files are extracted for the physical verification (DRC/LVS) purpose using CALIBRE/HERCULES, after this the dummy layers and seal ring are inserted into the design, to clear density rules and recommended rules and protect the chip from moisture and other adverse effects. The layout design procedure is performed on the blocks of the memory design, whereas W/L is designed only for 6T SRAM block. From the transient analysis the delay, power for SRAM memory at nominal corners were determined and the results are discussed in previous sections of this paper. The SNM for the SRAM structure is determined using the butterfly structure for SRAM bitcell, and the bitcell operates properly for static noise margin of 0.63volts. It can be concluded, that characterization procedure is performed on the 6T SRAM bitcell. After the SRAM bitcell characterization, the standby power, which is dissipated when there is no switching activity, is found to be 7.76 microwatts/bitcell and dynamic power dissipated during switching activity is determined as 3.3704E-04watts/bitcell.

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