Solid-State Electronics 54 (2010) 8689

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Solid-State Electronics
journal homepage: www.elsevier.com/locate/sse

SOI versus bulk-silicon nanoscale FinFETs

Jerry G. Fossum a,*, Zhenming Zhou a, Leo Mathew b, Bich-Yen Nguyen c
a

Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611-6130, USA Applied Novel Devices, Inc., Austin, TX 78717, USA c Soitec USA, Inc., Austin, TX 78746, USA
b

a r t i c l e

i n f o

a b s t r a c t
Our previously proposed concept of pragmatic FinFET design is overviewed, with new insights given, prior to presenting results of an assessment of nanoscale FinFETs on SOI versus bulk silicon (Si). The assessment is supported by 3-D numerical simulations of FinFETs for a comparison of the electrical properties of the SOI and bulk-Si FinFETs, and it includes a discussion of serious processing issues for the latter. The SOI FinFET is thereby suggested to be viable, whereas the bulk-Si FinFET (as currently dened) is not. 2009 Elsevier Ltd. All rights reserved.

Article history: Received 20 April 2009 Received in revised form 4 July 2009 Accepted 20 August 2009 Available online 23 December 2009 The review of this paper was arranged by Prof. O. Engstrm Keywords: Double-gate MOSFET Nanoscale CMOS Pragmatic FinFET

1. Introduction The quasi-planar FinFET, illustrated in Fig. 1 on SOI, will most likely become the mainstream CMOS device in the future, enabling the technology to be scaled to the end of the SIA ITRS (roadmap) [1] where gate lengths (Lg) are projected to be <10 nm. FinFETs, with the gate wrapped around the thin-n body, enable elimination of channel doping, and thus the problem of threshold-voltage (Vt) variation that plagues conventional nanoscale (bulk-Si and PD/ SOI) MOSFETs. We have previously put forth the idea of pragmatic nanoscale FinFET design [2,3], which we believe is viable now. In this paper, we overview the pragmatic FinFET, including new insights we have recently gained, and we examine the question of FinFETs on bulk Si [4,5], as opposed to the pragmatic fabrication on SOI. 2. Pragmatic FinFET design As we have detailed before [3], pragmatic FinFETs are designed to simplify the fabrication process while enabling scalability and good CMOS performance. The pragmatic FinFET is dened as follows. (a) On SOI. Rationale for SOI, as opposed to bulk Si, is the main contribution of this paper.
* Corresponding author. E-mail address: fossum@tec.u.edu (J.G. Fossum). 0038-1101/$ - see front matter 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.12.002

(b) Undoped, ultra-thin Si-n body/channel (UTB). Undoped channels mean no effects of random dopant uctuations, high carrier mobilities [6], and signicant (benecial) draininduced charge/current enhancement (DICE) [7]. (c) Double-gate (DG). A top, third gate is not benecial (nor practical) due to strong (as well as weak) bulk (a.k.a. volume) inversion in the undoped FinFET [8]. This is true even for short ns, and especially true when the third dimension is used effectively via ns with heights approaching the technology pitch. (d) One, near-midgap metal gate for both CMOS devices. As opposed to dual metal gates with more process complexity, this means much lower Ioff (higher Vt) with some Ion sacrice, but the speed performance can be still very good [3]. (e) Relatively thick SiON dielectric. Thick oxide, with little Ion penalty due to the bulk inversion as discussed later, avoids a high-k dielectric, which adds process complexity and can actually be detrimental to performance [9]. (f) Optimal gate-source/drain underlap, which denes a benecial, VGS-dependent effective channel length that can yield good Ion/Ioff [10]. (g) No channel strain. Carrier mobilities can be high enough without it [6], provided potential excessive scattering near the source/drain ends of the channel [11] is, via processing, avoided for short Lg. (h) Source/drain engineering for Vt control, via limited dopants in the channel [12], as well as for the underlap and the mobility control.

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Gate
1020

Lext y

Lgate

Lext

1019

N SD [cm -3 ]

n+ n+ Source Source

n+ n+ Drain Drain
BOX

Abrupt NSD(y) w/ LeSD=0 NSD(y)

L LeSD

1018

Fig. 1. The basic quasi-planar nFinFET structure on SOI.

1017

The noted bulk inversion is signicant for strong- as well as weak-inversion conditions [8]. It is a result of the (relatively) low transverse electric eld in the undoped (symmetric) DG FinFET. Whereas it can thus lead to increased mobilities, it is predominantly a negative effect in undoped channels since it reduces the effective gate capacitance (CG) in strong inversion, and hence lowers Ion. This effect can be characterized (classically, for low VDS) by integrating Poissons equation over half of the Si body/channel thickness (tSi), and expressing the (total) inversion charge density (for an n-channel DG FinFET) as [13]

1016

Abrupt NSD(y) w/ effective LeSD0 LeSD

Leff LeSD

1015 25

35

45

55

65

75

85

95

y [nm]
Fig. 2. Illustration of how varying the lateral doping density prole NSD(y) in the S/D extensions of the undoped DG FinFET changes the weak-inversion effective channel length, as characterized by the effective GS/D underlap LeSD indicated. The SCEs are governed by LeSD, which is dened (implicitly) by the peak doping density in the S/ D, the (gaussian) NSD(y) straggle rL (that denes the degree of penetration of S/D dopants into the extensions), the extension length Lext, and the n width wSi, as described in [10] and [15].

2 6 Q i 26 4 C ox

3 x eox i 5V GS V t 1 eSi tox 7 7 1

where Cox = ox/tox is the oxide capacitance (per unit area) and i is x the average depth of the inversion electrons in each half of the channel. Bulk inversion increases i and thereby lowers the inversionx layer capacitance, yielding lower Qi, CG [the (VGS Vt) coefcient x in (1)], and Ion. And, energy-quantization further increases i . We note from (1) that bulk inversion in the FinFET also renders Qi less dependent on the oxide thickness tox. This is why keeping tox pragmatically thick, and avoiding a high-k dielectric [9], is not so detrimental to CG and Ion, and is thus feasible for the nanoscale FinFET. Further, thicker SiON reduces parasitic GS/D fringe capacitance [14], which can improve speed performance signicantly [3,9]. The GS/D underlap [10], which yields Leff > Lg in weak inversion for control of short-channel effects (SCEs), while Leff Lg in strong inversion, is crucial for ultimate undoped FinFET-CMOS scaling. Further, it reduces parasitic GS/D fringe capacitance [14], and can enable device design exibility for different applications, e.g., SRAM [15]. As illustrated and explained in Fig. 2, the underlap is effected by design of the lateral doping prole in the S/D extensions, NSD(y), which must be controlled in the S/D processing. This processing must also be dened to retain high mobilities for short Lg [11]. And, we note a third signicance of this processing and NSD(y). Limited S/D dopants can be allowed in the channel, near the S/D extensions, for Vt adjustment [12]. The key to such design is that the weak-inversion Vt, which correlates with Ioff, depends on NSD near the center of the channel, whereas the strong-inversion Vt, which correlates with Ion, depends on the average of NSD over the entire channel. Thus, a low-power FinFET design, with negligible NSD throughout the channel, would give high Vt and long Leff for low Ioff, all relative to a high-performance FinFET design, with negligible NSD near the center of the channel but signicant NSD near the ends of the channel, for lower Vt, shorter Leff, and higher Ion, without signicant Ioff sensitivity to NSD [12]. 3. SOI versus bulk Si Future FinFETs on bulk Si [4,5] are of interest mainly because of lower wafer cost. However, this advantage must be traded-off with

possible disadvantages of the bulk-Si FinFET associated with the fabrication process as well as the electrical performance. To assess the viability of bulk-Si FinFETs, we rst use 3-D numerical simulations to compare their electrical properties with those of SOI FinFETs, assuming quasi-controlled processing, and then we check the effects of the real, non-pragmatic processing on bulk Si. 3.1. Electrical properties We use Taurus [16] for 3-D simulations of nanoscale SOI and bulk-Si nFinFETs (Lg = 28 nm, wSi = 14 nm, hSi = 56 nm, tox = 1 nm, undoped UTB, midgap gate), as illustrated in Fig. 3. For the bulkSi device, we use the Taurus domain shown in Fig. 4, and we focus on the lower, ungated part of the Si n, which can result in significant SD punch-through if left undoped (like the upper n-channel). For punch-through stopping (PTS), we assume a uniform

SOI FinFET
Gate SiO2

Bulk-Si FinFET
Gate SiO2
x z

Si Fin hSi

wSi

BOX Si Substrate

Lower Fin Si Substrate

Isolation Oxide

Fig. 3. The basic structures of the SOI and bulk Si FinFETs, viewed along the channels. The lower, ungated portion of the bulk-Si n is indicated, as are the dimensions of the gated n (which are the same for both devices).

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100

120

NAL=1e18cm-3 NAL=1e19cm-3
80 100

Ion(bulk)/Ion(SOI) (%)

Vt (mV)

60

80

40

60

20

40

0 0 5 10

20 15

V (nm)
Fig. 6. Taurus-predicted increase in threshold voltage and decrease in on-state current in the bulk-Si FinFET, relative to Vt and Ion of the SOI FinFET, versus the vertical straggle rV of the PTS doping for two different underlying peak doping densities. The values of NAL indicated are the peak, uniform densities in the underlying PTS region, and rV denes the assumed gaussian upward fall-off of the doping density in the n-channel.

Fig. 4. The Taurus 3-D domain assumed for the bulk-Si FinFET. The lower n is doped uniformly (NAL for PTS, which is p-type for the nFinFET) everywhere under the S-UTB-D structure. The possible S/D-junction over-diffusion (Dzj) into the PTS region is indicated; under-diffusion is also possible, for which Dzj < 0.

p-type doping density (NAL) in the lower n, under the S-UTB-D structure as noted in Fig. 4. Also, we allow for possible over-diffusion of the S/D junctions (Dzj) into the PTS region as indicated in Fig. 4. The Ioff predictions plotted in Fig. 5, versus NAL for varying Dzj, reect the signicance of punch-through leakage current for low NAL and nite Dzj. A realistic, nite Dzj > 0, which results in a direct SD punch-through path under the channel, clearly necessitates an optimal NAL $ 1018 cm3 to stop the punch-through. However, the PTS doping, assumed to underlie the S/D regions as well as the n-UTB as noted, results in signicant drain-junction tunneling current for NAL > 1018 cm3 as evident in the gure. Control of NAL is thus crucial, and this portends a signicant doping-sensitivity issue for the bulk-Si FinFET. Of course, this is not an issue for SOI FinFETs because of the underlying BOX. Another issue for the bulk-Si FinFET is the possible up-diffusion of the underlying PTS doping into the n-channel. Simulations, based on assumed gaussian NAL(z) proles, show, in Fig. 6, that the up-diffusion, for typical vertical straggle (rV), effectively reduces hSi (the gate width), and hence increases Vt and lowers Ion

relative to the SOI FinFET. Note also that similar effects will occur for under-diffusion of the S/D junctions, i.e., if Dzj < 0. Further, updiffusion of the PTS doping into the S/D extensions, as well as the channel, can undermine control of NSD(y), and hence of the GS/D underlap, the adjusted Vt, and possibly carrier mobility as we discussed in Section 2. The speed performance of bulk-Si-FinFET CMOS is degraded by the added S/D-junction capacitance due to the PTS doping, but not excessively. For 28 nm devices designed as noted, with optimal PTS doping, UFDG [17]/Spice3 ring-oscillator simulations predict only about a 5% increase in delay relative to the counterpart SOI-FinFET CMOS. 3.2. Processing issues Whereas the noted electrical properties (at least for assumed quasi-controlled processing) of the bulk-Si FinFET do not clearly negate its viability, we believe that the processing issues do. Control of the n and isolation-oxide heights require multiple processes not needed for the SOI FinFET. And, clearly, the processing needed to get optimal NAL (Fig. 5) in the lower n, with minimal Dzj and the needed isolation oxide (Figs. 3 and 4), is very complex relative to that of the pragmatic SOI FinFET. For the current implementation proposed for the bulk-Si FinFET [4,5], the PTS implant should be nearly vertical for tight n pitch, necessitating subsequent lateral dopant diffusion under the n and up the lower n during anneal. Direct implant to the base of the n through the channel results in prohibitive doping in the channel due to subsequent anneals and nite straggle in the prole. Clearly, the reliability of the noted multi-directional PTS diffusion in a nanoscale structure is questionable (like that of the channel doping which is now stopping conventional bulk-Si CMOS scaling); the resulting NAL in the lower n, and in the n-channel, will be random. Further, this randomness is exacerbated by varying n features for different applications on a CMOS chip (e.g., for SOC design). For example, Fig. 7 illustrates how the efcacy of the PTS implant/diffusion process depends on the n width (wSi). Clearly, the same process, which is hardly viable for xed wSi, cannot be used for different wSi. Thus, since varying wSi is desirable (and even essential) in different applications to enable different oxide thickness (without undermining tSi) or variable SCE control (via wSi/Lg) for Vt and

10-5

10-6

zj=0nm zj=6nm zj=10nm

Ioff (A/fin)

10-7

10-8

10-9

10-10 1015 1016 1017 1018

1019

NAL (cm -3)

Fig. 5. Taurus-predicted off-state current in the 28 nm bulk-Si nFinFET, versus the underlying PTS doping density and the S/D over-diffusion.

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Ion/Ioff adjustment, SOC design with bulk-Si FinFETs is severely limited. Other bulk-Si-FinFET processing issues relate to etching the n and the deposited isolation oxide, and its effects on the device performance. The bulk-n height must exceed the SOI-n hSi signicantly because of the need for the isolation oxide (Figs. 3 and 4). The n is thus unavoidably tapered, implying uncontrolled wSi, and control of the gated n height (hSi) is undermined by tapering of the oxide up the n, as illustrated in Fig. 8. Control of hSi and wSi in SOI FinFETs is much easier. 4. Summary We summarize briey with two educated, personal opinions that follow from our study described herein. (1) The pragmatic DG FinFET on SOI is viable, and is potentially scalable to the end of the SIA roadmap (where Lg < 10 nm). (2) The bulk-Si FinFET (as currently dened) is not viable. (3) We further note that the FinFET-on-SOI technology, as opposed to on bulk Si, will enable integration of oatingbody (e.g., 1T) DRAM [18], which can be a viable, essential embedded memory technology in the future.

Fig. 7. Illustrations of how the efcacy of the PTS implant/diffusion in a bulk-Si FinFET depends on n width (wSi), showing that a universal process for different applications on a chip (i.e., SOC) cannot be utilized.

Acknowledgment This work was supported in part by Soitec. References

[1] The international technology roadmap for semiconductors. Austin (TX): Semiconductor Industry Assoc.; 2005. [2] Fossum JG. Physical insights on nanoscale multi-gate CMOS design. In: EUROSOI 2006 Conf Proc; March 2006. p. 112. [3] Fossum JG. Physical insights on nanoscale multi-gate cmos design. Solid-State Electron 2007;51(February):18894. [4] Okano K et al. Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm n width and 20 nm gate length. IEDM Tech Dig 2005(December):73942. [5] Inaba S et al. Direct evaluation of DC characteristic variability in FinFET SRAM cell for 32 nm node and beyond. IEDM Tech Dig 2007(December):48790. [6] Chowdhury MM, Trivedi VP, Fossum JG, Mathew L. Carrier mobility/transport in undoped-UTB DG FinFETs. IEEE Trans Electron Dev 2007;54(May):112531. [7] Chouksey S, Fossum JG. DICE: a benecial short-channel effect in nanoscale double-gate MOSFETs. IEEE Trans Electron Dev 2008;55(March):796802. [8] Kim S-H, Fossum JG, Trivedi VP. Bulk inversion in FinFETs and implied insights on effective gate width. IEEE Trans Electron Dev 2005;52(September):19937. [9] Agrawal S, Fossum JG. On the suitability of a high-k gate dielectric in nanoscale FinFET-CMOS technology. IEEE Trans Electron Dev 2008;55(July):17149. [10] Trivedi V, Fossum JG, Chowdhury MM. Nanoscale FinFETs with gate-source/ drain underlap. IEEE Trans Electron Dev 2005;52(January):5662. [11] Cros A et al. Unexpected mobility degradation for very short devices: a new challenge for CMOS scaling. IEDM Tech Dig 2006(December):6636. [12] Chouksey S et al. Threshold voltage adjustment in nanoscale DG FinFETs via limited source/drain dopants in the channel. IEEE Trans Electron Dev 2009;56(October):234853. [13] Lpez-Villanueva JA et al. Effects of inversion-layer centroid on the performance of double-gate MOSFETs. IEEE Trans Electron Dev 2000;47(January):1416. [14] Kim S-H, Fossum JG, Yang J-W. Modeling and signicance of fringe capacitance in nonclassical CMOS Devices with gate-source/drain underlap. IEEE Trans Electron Dev 2006;53(September):214350. [15] Kim S-H, Fossum JG. Design optimization and performance projections of double-gate FinFETs with gate-source/drain underlap for SRAM application. IEEE Trans Electron Dev 2007;54(August):193442. [16] Taurus-2006. Users manual. Durham (NC): Synopsys, Inc.; 2006. [17] UFDG-3.7. Users guide. Florida: SOI group, Univ.; 2007. [18] Okhonin S et al. Ultra-scaled Z-RAM cell. IEEE Int SOI Conf Proc 2008:1578.

Fig. 8. Illustration of issues relating to etching the n and the isolation oxide of the bulk-Si FinFET. Control of the gated n is undermined by variations in the isolation oxide between ns and by tapering of the oxide up the n.