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A junction is the region where the silicon changes from n-type to p-type material where n-type and p-type materials are brought together. By arranging junction in certain physical structures and combining these with other physical structures, various semiconductor devices may be constructed.
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3.1.2 Oxidation
Forming silicon dioxide (SiO2) Two common approaches to oxidation of silicon: Wet oxidation: when the oxidizing atmosphere contains wafer vapor. The temperature is usually between 900 oC and 1000 oC. This is a rapid process. Dry oxidation: when the oxidizing atmosphere is pure oxygen. Temperatures are in the region of 1200 oC to achieve an acceptable growth rate. Since SiO2 has approximately twice the volume of silicon, the SiO2 layer grows almost equally in both vertical directions. (see Figure 3.2)
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How much impurity used is determined by the energy and time of the ion-implantation or the time and temperature of the deposition and diffusion step. Where it is used is determined by using special materials as masks.
The common materials used as mask include: photoresist polysilicon silicon dioxide (SiO2) silicon nitride (Si3N4)
Selective diffusion entails: Patterning windows in a mask material on the surface of the wafer. Subjecting exposed area to a dopant source. Removing any unrequired mask material.
Example: The process of creating an oxide mask: Step 1: Covering the surface of the oxide with an acid resistant coating (called photoresist), and on top of this covering a mask which contains desired oxide windows. Step 2: Polymerizing the acid resistant coating by passing the coated silicon through the UV light. Step 3: Removing the polymerized areas with an organic solvent. This is called a positive resist. Step 3:Removing the unexposed photoresist area by the solvent (either Step 3 or 3 is done). This is called a negative resist..
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Step 4: Etching of exposed SiO2. Figure 3.3 shows an example of negative resist process.
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Using photoresist in conjunction with UV light sources, diffraction around the edges of the mask patterns and alignment tolerances limit line widths to around 0.8 um. Electron beam lithography (EBL) can produce line widths smaller than 0.5 um. Main advantages of EBL: Patterns are derived directly from digital data. No intermediate hardware image such as masks is needed (i.e., masks are stored as the form of data). Different patterns may be accommodated in different sections of wafers. Changes to patterns can be implemented quickly.
Main disadvantages of EBL: Cost of the equipment. Requiring the large amount of time (i.e., the desired patterns are generated sequentially and only one wafer can be handled at a time).
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Two kinds of silicon oxides: Gate-oxide (thinox): A thin highly controlled layer of SiO2 which defines the gate area of a transistor. Field-oxide: A thick layer of SiO2 is required elsewhere to isolate the individual transistors.
Figure 3.4(b) forms gate oxide. Figure 3.4(c) grows polysilicon gate. Figure 3.4(d) dopes the gate and source/drain regions. Doping of substrate only occurs at the regions where the polysilicon gate does not shadow the underlying substrate or where is not covered by SiO2. The case of using silicon gate as a mask is referred to as self-aligned process because the source and drain do not extend under the gate. Figure 3.4(e) forms the contact cuts. Figure 3.4(f) forms the contacts and interconnect. Note that parasitic MOS transistors exist between unrelated transistors as shown in Figure 3.5. These transistors have very thick gate oxide such that their threshold voltage is much higher than that of a regular transistor.
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Implanting of n+ by an n_plus mask: A thin-oxide area exposed by the n-plus mask will become an n+ diffusion area. If the n-plus area is in the p-substrate, then an n-channel transistor (see Figure 3.7(f)) or n-type diffusion wire may be constructed. If the n-plus area is in the n-well (not shown), then an ohmic contact to the n-well may be constructed. (An ohmic contact is one which is only resistive in nature and is not rectifying. In other words, there is no junction. Current can flow in ohmic contact.) To reduce hot electron effects for modern small dimension processes , drain engineering is performed. This consists of performing a shallow n-LDD (Light Doped Drain) implant that covers the source/drain region where there is no poly. A spacer oxide is then grow over the polysilicon gate. An n+ implant is then used to produce n+ implant that are spaced from the edge of the original poly gate edges. The spacer is then removed, resulting in a structure that is more resistant to hot-electron effects (see Fig. 3.7(g)). Implanting of p+ by a complement (i.e. p+ mask) of the n-plus mask: A thin-oxide area exposed by the p+ mask will become a p+ (or p-active) diffusion area. P-active in the n-well defines possible ptransistors and wires (see Fig. 3.7(h)). A p-active area in the p-substrate allows an ohmic contact to be made. The LDD step is not needed for p-transistors. Defining of contact cuts (see Fig. 3.7(i)). Metalization ( see Fig. 3.7(j)) passivation (not shown)
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The cross section of a CMOS inverter is shown in Figure 3.8. Substrate contacts: Topside p-substrate contact to VSS is preferred because it reduces parasitic resistances that could cause latch-up. Well contacts to VDD is also from topside.
Substrate (p-substrate versus n-well) contacts are formed by placing n+ regions in the n-well (VDD contacts) and p+ in the p-type substrate (VSS contacts) as shown in Figure 3.9(a).
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This process provides separately optimized wells, balanced performance n-transistors and p-transistors may be constructed.
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Because the diffusion regions extend down to the insulating substrate, only sidewall areas associated with source and drain diffusions contribute to the parasitic junction capacitance. Since sapphire and SiO2 are extremely good insulators, leakage currents between transistors and substrate and adjacent devices are almost eliminated.
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In order to improve the yield, some processes use preferential etch, where the island edges are tapered (Figure 3.12).
Figure 3.12
Advantages of SOI: Due to the absence of wells, transistor structures denser than bulk silicon are feasible. Lower substrate capacitance. No field-inversion problems (the existence of parasitic transistor between two normal transistors) No latch up is possible because of the isolation of transistors by insulating substrate.
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No body-effect problems because of no conducting substrate. With enhanced radiation tolerance. Disadvantages of SOI : Lack of substrate diodes makes I/O protection difficult. Coupling capacitance still exists. More expensive to build.
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No restrictions on the placement of the via with respect to underlying layers (Figure 3.14(a)). Placement of via inside (Figure 3.14(b)) or outside (Figure 3.14(c)) the underlying polysilicon or diffusion areas. Stacking of vias on top of contacts (Figure 3.14(d)). The steps for a two-metal process The oxide below the first-metal layer is deposited by atmospheric chemical vapor deposition (CVD). The second oxide layer between the two metal layers is applied in a similar manner. Removal of the oxide by a plasma etcher.
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3.3.2.2 Capacitors
Figure 3.17 shows a typical polysilicon capacitor for analog applications. One extra layer of polysilicon and a second thin-oxide layer are required.
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Figure 3.18(a) shows a structure of the trench capacitor used as a memory capacitor. The trench is 4 m deep and has a capacitance of 90 fF. The sides of the trench are doped n+ and coated with a 10nm oxide.This forms the top plate of the capacitor and one side of the pass transistor. The trench is filled with a polysilicon plug, which forms the bottom plate of the cell storage capacitor. This is held at VDD/2 via a metal connection. The bottom of the trench has a p+ plug that forms a channel stop region to isolate adjacent capacitors.
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Comparisons of -rules versus micron-rules (at =0.5 m) Metal 1 contact pitch is 3.5 m for -rule, but 2.75 m for micron-rule. Metal 2 via pitch is 4.0 m for -rule, but 2.75 m for micron-rule. Transistor pitch (contact-poly-contact pitch) is 4 m for -rule, but 3.75 m for micron-rule.
Table 3.3 summarizes the basic dimensions for the representative processes ranged from 0.25 - 0.6 m.
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Contact Rules : Contact types Metal to p-active (p-diffusion) contact. Metal to n-active (n-diffusion) contact. Metal to polysilicon contact. VDD and VSS substrate contacts. Split (substrate contacts). Well and substrate contacts must be employed to tie the well to VDD and to tie the substrate to VSS, respectively. The split (merged, abutting) contact is equivalent to two separate metal-diffusion contacts that are strapped together with metal (Figure 3.27). This structure is used to tie transistor sources to either the substrate or the n-well.
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Guard Rings (Figure 3.28): p+ guard ring is a p+ diffusion on p-substrate whereas n+ guard ring is a n+ diffusion on n-well to collect injected minority carriers. n-devices are constructed upon p-substrate with n+ diffusion source/drain. The minority carriers are holes. Thus, p+ guard ring connected to VSS is employed to collect holes. p-devices are constructed upon n-well with p+ diffusion source/drain. The minority carriers are electrons. Thus, n+ guard ring connected to VDD is employed to collect electrons.
n+ guard ring
2 3
p+ guard ring
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Metal Rules : Metal spacings may vary with the width of the metal line (so-called flat-metal rules). There may also be maximum-metal rules. There may require the whole chip to be covered by a certain portion (e.g., 2/3 ) of metal.
Special via rules, metal2 rules, via2 rules, and metal3 rules may be specifically presented for manufacturability requirement.
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3.5 Latchup
Latchup is the shorting of the VDD and VSS lines due to the parasitic circuit effect present in CMOS structure. This usually results in chip self-destruction or at least system failure with the requirement to power down.
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Latchup Triggering Two distinct triggering are possible : (1) Lateral triggering occurs when a current flows in the emitter of the lateral npn-transistor. The static trigger point is set by , where
V pnp I ntrigger voltageon Vpnp-on 0.7 volts the turn-on= R of the vertical pnp-transistor. npn well npn=common base gain of the lateral npn transistor. Rwell=well resistance. (2) Vertical triggering occurs when a sufficient current is injected into emitter of the vertical-pnp transistor. Current has to be injected into either the npn-or pnp-emitter to initiate latch up. This may occur for internal circuit due to supply voltage transients. It commonly happens at the I/O circuits where internal circuit meets the external world and large currents can flow.
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Figure 3.30(a) shows an example where the source of an nMOS output transistor experiences undershoot with respect to VSS. When the output dips below VSS by more than 0.7V, the drain of the nMOS output driver is forward biased, which initiates latch up. Figure 3.30(b) shows a complementary case where the pMOS output transistor experiences an overshoot more than 0.7V beyond VDD.
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where
I Rsubstrate =
I Rwell =
Vbe pnp
Reducing the resistor values and reducing the gain of the parasitic transistors are the basis for eliminating latchup. This can be approached by, Latchup resistant CMOS process Layout techniques
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Latch up resistant process (Layout techniques will be presented in the following section) : Use of silicon starting-material with a thin epitaxial layer on top of a highly doped substrate. This decreases the value of the substrate resistor. Retrograde well structure formed by a highly doped area at the bottom of the well and by lightly doping on the top portion of the well. This preserves good characteristics for the p-transistors and also reduces the well resistance deep in the well. Increasing holding voltage above VDD such that latchup will not occur. It is hard to reduce the betas (gains) of the bipolar transistors.
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3.7 Summary
CMOS fabrication processes are studied : n-well process, p-well process, twin-tub process, and SOI process. Process enhancement is introduced multiple metal interconnect, polysilicon/refractory metal interconnect, local interconnect. resistors, capacitors, programmable ROM. Layout design rules. Latch up. CAD issues.