REFERENCES

[1] P. Burton and D.R. Noaks, High-Speed Iterative Multiplier, Electronics Letters, Vol. 4, p. 262, 1968. [2] G.Goto, High Speed Digital Parallel Multipliers, U.S. Patent 5 465 226, Nov 7,1995. [3] H.Guilt, Fully Iterative Fast Array for Binary Multiplication, Electronics Letters, vol. 5, p. 263, 1969. [4] V Oppenheim and R. W Schafer, Discrete-Time Signal Processing. Prentice Hall,1989. [5] Zhijun Huang, Milo D. Ercegovac, "High-Performance Left-to-Right Array Multiplier Design," arith, pp.4, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003 [6] S. Gorgin and G. Jaberipur, Fully Redundant Decimal Arithmetic, Proc. 19th IEEE Symp. Computer Arithmetic, pp. 145-152, 2009. [7] Soojin Kim and Kyeongsoon Cho, Design of High-speed Modified Booth Multipliers [8] Aamir A Farooqui;Vojin G Oklobdzija General Data Path Organization of a MAC Unit for VLSI Implementation of DSP Processors 1998. [9] Ramalatha, M Dayalan, K D Dharani, P Priya, and S Deborah, "High speed energy efficient ALU design using Vedic multiplication techniques", ICACTEA, 2009. pp. 600-3, Jul 15-17, 2009. [10] H Thapliyal, M B Srinivas, and H R Arabnia, "Design and Analysis of a VLSI Based High Performance Low Power Parallel Square Architecture", in Proc. Int. Conf. Algo. Math. Comp. Sc., Las Vegas, pp. 72-6, Jun. 2005. [11] Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong Beom Cho, Multiplier design based on ancient Indian Vedic Mathematics [12] Harpreet Singh Dhillon Abhijit Mitra, A Digital Multiplier Architecture using Urdhava Tiryabhyam Sutra of Vedic Mathematics, Indian Institue of Technology, Guwahatti. [13] Purushottam D. Chidgupkar and Mangesh T. Karad, The Implementation of Vedic Algorithms in Digital Signal Processing on 8085/8086, Global J. of Engng. Educ., Vol.8 No.2 2004 UICEE Published in Australia. [14] Himanshu Thapliyal and Hamid R. Arabnia, A Time-Area- Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic, Department of Computer Science, The University of Georgia, 415 Graduate Studies Research Center Athens, Georgia 30602-7404, U.S.A. [15] K. Hwang, Computer arithmetic: Principles, Architecture and Design, New York: John Wiley & Sons,1979. [16] M.M.Mano, Computer system Architecture, Englewood Cliffs, NJ: Prenticehall,1982 [17] G-K-Ma, F.J.Taylor, Multiplier Policies for Digital Signal Processing, IEEE ASSP Mag, Vol-7, no.1, PP 6-20, Jan1990. [18] M.Morris Mano, Digital Logic and Computer Design, Englewood Cliffs, NJ: Prentice Hall, 1979 (Page 119-124). [19] Neil H.E Weste, David Harris, Ayan Banerjee, CMOS VLSI Design, A Circuits And Systems Perspective, Third Edition, Published by Pearson Education, PP327- 328

[20] Mrs M Ramalatha, Prof.D.Sridharan, VLSI based High Speed Karatsuba Multiplier for Cryptographic Applications Using Vedic Mathematics, IJSCI, 2007. [21] El hadj you ssef wajih, Zeg hid Medien, Machhout Mohsen, Bouallegue Belgacem, Tourki Rached, Efficient Hardware Architecture of Recursive Karatsuba-Ofman Multiplier, 2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era. [22] Jagadguru Swami Sri Bharati Krishna Tirthji Maharaja,Vedic Mathematics, Motilal Banarsidas, Varanasi, India, 1986. [23] Harpreet Singh Dhillon and Abhijit Mitra, A Reduced- Bit Multiplication Algorithm for Digital Arithmetics, International Journal of Computational and Mathematical Sciences, 2008. [24] H Thapliyal, M B Srinivas, and H R Arabnia: A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics. ESA /VLSI 2004:440-446. [25] Shanthala S and S. Y. Kulkarni, VLSI Design and Implementation of Low Power MAC Unit with Block Enabling Technique, European Journal of Scientific Research ISSN 1450-216X Vol.30 No.4 (2009), pp.620-630. [26] Spartan-3E FPGA Starter Kit Board User Guide, UG230 (v1.1) June 20, 2008. [27] Deming Chen, Jason Cong, and Peichan Pan, FPGA Design Automation: A Survey, Foundations and Trends in Electronic Design Automation Volume 1,Issue 3, November 2006. [28] Ken Chapman, Initial Design for Spartan-3E Starter Kit (LCD Display Control), Xilinx Ltd 16th February 2006.