8085 INTERRUPTS Interrupt is a process where an external device can get the attention of the microprocessor.

The process starts from the I/O device and is asynchronous. Classification of Interrupts Interrupts can be classified into two types: -Maskable Interrupts (Can be delayed or Rejected) -Non-Maskable Interrupts (Can not be delayed or Rejected) Interrupts can also be classified into: -Vectored (the address of the service routine is hard-wired) -Non-vectored (the address of the service routine needs to be supplied externally by the device) An interrupt is considered to be an emergency signal that may be serviced. The Microprocessor may respond to it as soon as possible. What happens when MP is interrupted ? When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR. Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non-maskable and whether interrupts are being masked or not. There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored. -Vectored: The address of the subroutine is already known to the Microprocessor -Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The EI instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The DI instruction is a one byte instruction and is used to Disable the non-maskable interrupts. The 8085 has a single Non-Maskable interrupt. The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop. The 8085 has 5 interrupt inputs: 1- The INTR input. The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair.

2,3,4- RST 5.5, RST 6.5, RST 7.5 are all automatically vectored. RST 5.5, RST 6.5, and RST 7.5 are all maskable. 5- TRAP is the only non-maskable interrupt in the 8085 TRAP is also automatically vectored An interrupt vector is a pointer to where the ISR is stored in memory. All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT). The IVT is usually located in memory page 00 (0000H 00FFH). The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives. Example: Let , a device interrupts the Microprocessor using the RST 7.5 interrupt line. Because the RST 7.5 interrupt is vectored, Microprocessor knows , in which memory location it has to go using a call instruction to get the ISR address. RST7.5 is knows as Call 003Ch to Microprocessor. Microprocessor goes to 003C location and will get a JMP instruction to the actual ISR address. The Microprocessor will then, jump to the ISR location The 8085 Non-Vectored Interrupt Process 1- The interrupt process should be enabled using the EI instruction. 2- The 8085 checks for an interrupt during the execution of every instruction. 3- If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted 4- INTA allows the I/O device to send a RST instruction through data bus. 5- Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to call location (ISR Call) specified by the RST instruction 6- Microprocessor Performs the ISR. 7- ISR must include the EI instruction to enable the further interrupt within the program. 8- RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted.

RESTART SEQUENCE The restart sequence is made up of three machine cycles In the 1st machine cycle: The microprocessor sends the INTA signal. While INTA is active the microprocessor reads the data lines expecting to receive, from the interrupting device, the opcode for the specific RST instruction. In the 2nd and 3rd machine cycles: the 16-bit address of the next instruction is saved on the stack. Then the microprocessor jumps to the address associated with the specified RST instruction.

How does the external device produce the opcode for the appropriate RST instruction? The opcode is simply a collection of bits. So, the device needs to set the bits of the data bus to the appropriate value in response to an INTA signal. During the interrupt acknowledge machine cycle, (the 1st machine cycle of the RST operation): The Microprocessor activates the INTA signal. This signal will enable the Tri-state buffers, which will place the value EFH on the data bus. Therefore, sending the Microprocessor the RST 5 instruction. Issues in Implementing INTR Interrupts How long must INTR remain high? The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction. The INTR must remain active long enough to allow for the longest instruction. The longest instruction for the 8085 is the conditional CALL instruction which requires 18 Tstates. Therefore, the INTR must remain active for 17.5 T-states. If f= 3MHZ then T=1/f and so, INTR must remain active for [ (1/3MHZ) * 17.5 5.8 micro seconds]. How long can the INTR remain high? The INTR line must be deactivated before the EI is executed. Otherwise, the microprocessor will be interrupted again. Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0). Therefore, INTR should be turned off as soon as the INTA signal is received. Can the microprocessor be interrupted again before the completion of the ISR? As soon as the 1st interrupt arrives, all maskable interrupts are disabled. They will only be enabled after the execution of the EI instruction. Therefore, the answer is: only if we allow it to. If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done. How do we allow multiple devices to interrupt using the INTR line? The microprocessor can only respond to one signal on INTR at a time. Therefore, we must allow the signal from only one of the devices to reach the microprocessor. We must assign some priority to the different devices and allow their signals to reach the microprocessor according to the priority. The solution is to use a circuit called the priority encoder (74LS148). This circuit has 8 inputs and 3 outputs. The inputs are assigned increasing priorities according to the increasing index of the input. Input 7 has highest priority and input 0 has the lowest.

The 3 outputs carry the index of the highest priority active input. Figure 12.4 in the book shows how this circuit can be used with a Tri-state buffer to implement an interrupt priority scheme. Multiple Interrupts & Priorities Note that the opcodes for the different RST instructions follow a set pattern. Bit D5, D4 and D3 of the opcodes change in a binary sequence from RST 7 down to RST 0. The other bits are always 1. This allows the code generated by the 74366 to be used directly to choose the appropriate RST instruction. The one draw back to this scheme is that the only way to change the priority of the devices connected to the 74366 is to reconnect the hardware.

QUESTIONS 1. What are the various registers in 8085? Accumulator register, Temporary register, Instruction register, Stack Pointer, Program Counter are the various registers in 8085 . 2. In 8085 name the 16 bit registers? Stack pointer and Program counter all have 16 bits. 3. What are the various flags used in 8085? Sign flag, Zero flag, Auxillary flag, Parity flag, Carry flag. 4. What is Stack Pointer? Stack pointer is a special purpose 16-bit register in the Microprocessor, which holds the address of the top of the stack. 5. What is Program counter? Program counter holds the address of either the first byte of the next instruction to be fetched for execution or the address of the next byte of a multi byte instruction, which has not been completely fetched. In both the cases it gets incremented automatically one by one as the instruction bytes get fetched. Also Program register keeps the address of the next instruction. 6. Which Stack is used in 8085? LIFO (Last In First Out) stack is used in 8085.In this type of Stack the last stored information can be retrieved first. 7. What happens when HLT instruction is executed in processor?

The Micro Processor enters into Halt-State and the buses are tri-stated. 8. What is meant by a bus? A bus is a group of conducting lines that carriers data, address, & control signals. 9. What is Tri-state logic? Three Logic Levels are used and they are High, Low, High impedance state. The high and low are normal logic levels & high impedance state is electrical open circuit conditions. Tri-state logic has a third line called enable line. 10. Give an example of one address microprocessor? 8085 is a one address microprocessor. 11. In what way interrupts are classified in 8085? In 8085 the interrupts are classified as Hardware and Software interrupts. 12. What are Hardware interrupts? TRAP, RST7.5, RST6.5, RST5.5, INTR. 13. What are Software interrupts? RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7. 14. Which interrupt has the highest priority? TRAP has the highest priority. 15. Name 5 different addressing modes? Immediate, Direct, Register, Register indirect, Implied addressing modes. 16. How many interrupts are there in 8085? There are 12 interrupts in 8085. 17. What is clock frequency for 8085? 3 MHz is the maximum clock frequency for 8085. 18. What is the RST for the TRAP? RST 4.5 is called as TRAP. 19. In 8085 which is called as High order / Low order Register? Flag is called as Low order register & Accumulator is called as High order Register. 20. What are input & output devices? Keyboards, Floppy disk are the examples of input devices. Printer, LED / LCD display, CRT Monitor

are the examples of output devices. 21. Can an RC circuit be used as clock source for 8085? Yes, it can be used, if an accurate clock frequency is not required. Also, the component cost is low compared to LC or Crystal. 22. Why crystal is a preferred clock source? Because of high stability, large Q (Quality Factor) & the frequency that doesn t drift with aging. Crystal is used as a clock source most of the times. 23. Which interrupt is not level-sensitive in 8085? RST 7.5 is a raising edge-triggering interrupt. 24. What does Quality factor mean? The Quality factor is also defined, as Q. So it is a number, which reflects the lossness of a circuit. Higher the Q, the lower are the losses. 25. What are level-triggering interrupt? RST 6.5 & RST 5.5 are level-triggering interrupts.

Intel 8085 microprocessor architecture

Memory
Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB. Program memory - program can be located anywhere in memory. Jump, branch and call instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB. All jump/branch instructions use absolute addressing. Data memory - the data can be placed anywhere as the 8085 processor always uses 16-bit addresses. Stack memory is limited only by the size of memory. Stack grows downward. First 64 bytes in a zero memory page should be reserved for vectors used by RST instructions.

Interrupts
The 8085 microprocessor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest): INTR is maskable 8080A compatible interrupt. When the interrupt occurs the processor fetches from the bus one instruction, usually one of these instructions:
y

One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction). CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of the instruction.

RST5.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 2Ch (hexadecimal) address. RST6.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 34h (hexadecimal) address. RST7.5 is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 3Ch (hexadecimal) address. Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24h (hexadecimal) address. All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.

I/O ports
256 Input ports 256 Output ports

Registers
Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store operations. Flag is an 8-bit register containing 5 1-bit flags:
y y y y

Sign - set if the most significant bit of the result is set. Zero - set if the result is zero. Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result. Parity - set if the parity (the number of set bits in the result) is even.

Carry - set if there was a carry during addition, or borrow during subtraction/comparison.

General registers:
y y y

8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte. Some instructions may use BC register as a data pointer. 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte. Some instructions may use DE register as a data pointer. 8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte. HL register usually contains a data pointer used to reference memory addresses.

Stack pointer is a 16 bit register. This register is always incremented/decremented by 2. Program counter is a 16-bit register.

Instruction Set
Instruction set of Intel 8085 microprocessor consists of the following instructions:
y y y y y y

Data moving instructions. Arithmetic - add, subtract, increment and decrement. Logic - AND, OR, XOR and rotate. Control transfer - conditional, unconditional, call subroutine, return from subroutine and restarts. Input/Output instructions. Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

Addressing modes
Register - references the data in a register or in a register pair. Register indirect - instruction specifies register pair containing address, where the data is located. Direct. Immediate - 8 or 16-bit data.