CHAPTER-1 INTRODUCTION

Most educational institutions' administrators are concerned about student irregular attendance. Absenteeism and repent for such issues can cause the institution to lose its reputation as well as resulting in inadequate learning on the part of the student. Truancies can affect a student overall academic performance. It is vital for educational sectors to have ready-to-use solutions that simplify and increase the speed of data collection and increase the lectures efficiency assumed is a found icon for all. To address these problems, any institution must look for a better system. Such as RFID-based system that could log in the coming and going of any students. The important aspect of this paper is to research on the use of an automated system and to identify these problems.

1.1 OBJECTIVE: To implement G - ID in schools using MI FARE technology. To intimate students activities to parents using mobile communication technologies

1.2 BLOCK DIAGRAM

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INDIVIDUAL SECTION

CLASSROOM SECTION

ADMIN SECTION

Block diagram Description:

The Block diagram involves three sections: Individual section Class room section Admin section Individual section consists of Battery power, Encoder and RF transmitter. Classroom section consists of RF receiver, Decoder, Microcontroller, Finger print sensor and PC. Admin section consists of PC and GSM modem. 1.2.1 Individual section: In individual section, a person ID is identified and transmitted to classroom section. A power supply of 5V is given to encoder circuit from battery power which transforms 230V ac supply. Encoder is used to encode the person RF signal to ASCII codes. These codes are transmitted using the RF
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transmitting antenna. This same antenna is followed for the identification of successive persons. 1.2.2 Classroom section: Here transmitted codes received and decoded, where the controller section verify the persons identification. The codes that are transmitted from the individual section by RF transmitter is received by the RF receiver and the ASCII codes are decoded by the decoder (HT12D). After the identification of codes the system requires the fingerprint matching for this information is displayed in the computer screen to keep the finger print. When the person keeps his finger it is scanned and checks with the already stored template .When both the RFID identification and finger print identification matches with the already stored identification then the person is authorised person and his presence is stored in the computer and it is transmitted to the Admin section through LAN. 1.2.3 Admin section: The datas that are stored in the classroom section are received through the LAN and it is stored in the PC. The students database is updated to their parents using GSM. 1.3 Hardware and Software choices: Hardware Components Power supply Microcontroller (AT89S51) Serial communication RF Module Finger Print Sensor GSM Module

Tools Used Keil IDE

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CHAPTER-2 LITERATURE REVIEW Circuit diagram:

1 D 1 2 9 V 1 2 A C 4 7 0 u F / 2 5 V 3 4 D B 1 + 2 1 0 C 6 5 I N 7 8 0O 5U T G N D 1 0 0 u F /1 6 V C D 6 3 V S C 4 5 9 4 8 3 7 2 6 1 S F - L X H 1 0 1 U 1 2 3 4 5 6 7 8 9 A A A A A A A A V H 0 1 2 3 4 5 6 7 s 1 1 d 1d V T1 O s 1c O s 1c D I 1N D 1 1 1 D 1 1 0 D 91 s D 8 V T - 1 2 V C 8 7 6 51 42 3 2 1 0 D C C 3 3 K R 3 C r V C R 3 3 3 0 E C

R F
GND DATA DATA VCC

4 3 3 . 9 2 M H z
VCC GND GND ANT C

16

R C 1 0 C 1 0 u 4 u 3

D9 1

VCC

R R C C C C

1 2 +

O O

U U

TR TR

8 2 1 I N3 1 I N

F 3 4 F5

M 1 2 2 +

2 6 C 1 0 5 u F 1 2 3 4 5 6 7 8 R T X X D D 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 P P P P P P P P P P P P P P P P 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 V C C 0 C 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 . 1 20 u F U P P P P P P P P 0 0 0 0 0 0 0 0 . . . . . . . . 0 1 2 3 4 5 6 7 1 V 3 3 3 3 3 3 3 3 / / / / / / / S/ 9 8A 7A 6A 5A 4A 3A 2A AI 2 3D 4D 5D 6D 7D 8D 9D PD P O R 0 1 2 3 4 5 6 79 C G 3 1 C

V GND

S E R IA L P O R T

1 D1

U 1 0T T

1 1 2

u T T

F 1 2

I N I N

1 4 O 7 U O U

T T

V+

VCC

40 . . . . . . . . . . . . . . . .

15

GND

V SW 0

C C2

R e a d e r C 1 X C 3 3 1 1 4 P . 0 5 C 3 9 3 3

RST

10uF

8K2

3 / R E X A D / 3V / A T LX ED / 2 P / I N P TS O E / I N T 1 / T O 2 / TP 1 2 . 7 2 / / WP 2 R . 6 2 / / RP D2 . 5 2 / P 2 . 42 / 9 R S T P 2 . 32 / P 2 . 22 / 1 8 X T A L 2 P 2 . 12 P 2 . 0 21 M9 H z X T A L 1 P F A T 8 9 S 5

1 0P 9R N 8 7A 6A 5A 4A 3A 2A /1 A / A

1 1 1 1 1 1

9 8

5 4 3 2 1 0

2.1 POWER SUPPLY

2.1.1 Block Diagram The ac voltage, typically 220V rms, is connected to a transformer, which steps that ac voltage down to the level of the desired dc output. A diode rectifier then provides a full-wave rectified voltage that is initially filtered by a simple capacitor filter to produce a dc voltage. This resulting dc voltage usually has some ripple or ac voltage variation. A regulator circuit removes the ripples and also remains the same dc value even if the input dc voltage varies, or the load connected to the output dc voltage changes. This voltage regulation is usually obtained using one of the popular voltage regulator IC units.

TRANSFOR MER

RECTIFI ER

FILTE R

IC REGULAT

LOA D

Block Diagram of Power supply

2.1.2 Working principle: Transformer: The potential transformer will step down the power supply voltage (0-230V) to (0-6V) level. Then the secondary of the potential transformer will be connected to the precision rectifier, which is constructed with the help of opamp. The advantages of using precision rectifier are it will give peak voltage output as DC, rest of the circuits will give only RMS output.

Bridge rectifier: When four diodes are connected as shown in figure, the circuit is called as bridge rectifier. The input to the circuit is applied to the diagonally opposite corners of the network, and the output is taken from the remaining two corners. Let us assume that the transformer is working properly and there is a positive potential, at point A and a negative potential at point B. the positive potential at point A will forward bias D3 and reverse bias D4. The negative potential at point B will forward bias D1 and reverse D2. At this time D3 and D1 are forward biased and will allow current flow to pass through them; D4 and D2 are reverse biased and will block current flow. The path for current flow is from point B through D1, up through RL, through D3, through the secondary of the transformer back to point B. this path is indicated by the solid arrows. Waveforms (1) and (2) can be observed across D1 and D3.One-half cycle later the polarity across the secondary of the transformer reverse, forward biasing D2 and D4 and reverse biasing D1 and D3. Current flow will now be from point A through D4, up through RL, through D2, through the secondary of T1, and back to point A. This path is indicated by the

broken arrows. Waveforms (3) and (4) can be observed across D2 and D4. The current flow through RL is always in the same direction. In flowing through RL this current develops a voltage corresponding to that shown waveform (5). Since current flows through the load (RL) during both half cycles of the applied voltage, this bridge rectifier is a full-wave rectifier. One advantage of a bridge rectifier over a conventional full-wave rectifier is that with a given transformer the bridge rectifier produces a voltage output that is nearly twice that of the conventional full-wave circuit. This may be shown by assigning values to some of the components shown in views A and B. assume that the same transformer is used in both circuits. The peak voltage developed between points X and y is 1000 volts in both circuits. In the conventional full-wave circuit shownin view A, the peak voltage from the center tap to either X or Y is 500 volts. Since only one diode can conduct at any instant, the maximum voltage that can be rectified at any instant is 500 volts. The maximum voltage that appears across the load resistor is nearly-but never exceeds-500 v0lts, as result of the small voltage drop across the diode. In the bridge rectifier shown in view B, the maximum voltage that can be rectified is the full secondary voltage, which is 1000 volts. Therefore, the peak output voltage across the load resistor is nearly 1000 volts. With both circuits using the same transformer, the bridge rectifier circuit produces a higher output voltage than the conventional full-wave rectifier circuit.

IC voltage regulator:
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Voltage regulators comprise a class of widely used ICs. Regulator IC units contain the circuitry for reference source, comparator amplifier, control device, and overload protection all in a single IC. IC units provide regulation of either a fixed positive voltage, a fixed negative voltage, or an adjustably set voltage.

Figure-power supply circuit The regulators can be selected for operation with load currents from hundreds of mille amperes to tens of amperes, corresponding to power ratings from mille watts to tens of watts. A fixed three-terminal voltage regulator has an unregulated dc input voltage, Vi, applied to one input terminal, a regulated dc output voltage, Vo, from a second terminal, with the third terminal connected to ground.

The series 78 regulators provide fixed positive regulated voltages from 5 to 24 volts. Similarly, the series 79 regulators provide fixed negative regulated voltages from 5 to 24 volts. For ICs, microcontroller, LCD --------- 5 volts For alarm circuit, op-amp, relay circuits ---------- 12 volts

2.2 Microcontroller (AT89S51):

The generic 8051 architecture sports a Harvard architecture, which contains two separate buses for both program and data. So, it has two distinctive memory spaces of 64K X 8 size for both program and data. It is based on an 8 bit central processing unit with an 8 bit Accumulator and another 8 bit B register as main processing blocks. Other portions of the architecture include few 8 bit and 16 bit registers and 8 bit memory locations.

Fig-Block Diagram

DIFFERENCES BETWEEN MICROCONTROLLER AND MICROPROCESSOR: Microprocessors have many instructions for moving data from external memory to internal memory. But microcontrollers have a few such instructions. Microprocessors have less bit handling instructions, but microcontrollers have many such instructions. Microprocessors are concerned with rapid movement of code and data from external memory. But Microcontroller is concerned with that of bits within the chip. Of course Microprocessor needs additional chips for memory, parallel port.

2.2.1 Description: The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmels high-density non-volatile memory technology and is compatible with the industry standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional non-volatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power
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saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. 2.2.2 CENTRAL PROCESSING UNIT: The CPU is the brain of the microcontrollers reading users programs and executing the expected task as per instructions stored there in. Its primary elements are an 8 bit Arithmetic Logic Unit (ALU), Accumulator (Acc), few more 8 bit registers, B register, Stack Pointer (SP), Program Status Word (PSW) and 16 bit registers, Program Counter (PC) and Data Pointer Register (DPTR). 2.2.3 THE ACCUMULATOR: If worked with any other assembly language you will be familiar with the concept of an accumulator register. The Accumulator, as its name suggests, is used as a general register to accumulate the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most versatile register the 8051 has due to the sheer number of instructions that make use of the accumulator. More than half of the 8051s 255 instructions manipulate or use the Accumulator in some way. For example, if you want to add the number 10 and 20, the resulting 30 will be stored in the Accumulator. Once you have a value in the Accumulator you may continue processing the value or you may store it in another register or in memory.

2.2.4 THE "R" REGISTERS:

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The "R" registers are sets of eight registers that are named R0, R1, through R7. These registers are used as auxiliary registers in many operations. To continue with the above example, perhaps you are adding 10 and 20. The original number 10 may be stored in the Accumulator whereas the value 20 may be stored in, say, register R4. To process the addition you would execute the command: As mentioned earlier, there are four sets of R registers, register bank 0, 1, 2, and 3. When the 8051 is first powered up, register bank 0 (addresses 00h through 07h) is used by default. In this case, for example, R4 is the same as Internal RAM address 04h. However, your program may instruct the 8051 to use one of the alternate register banks; i.e., register banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address 04h. For example, if your program instructs the 8051 to use register bank 1, register R4 will now be synonymous with Internal RAM address 0Ch. If you select register bank 2, R4 is synonymous with 14h, and if you select register bank 3 it is synonymous with address 1Ch. The concept of register banks adds a great level of flexibility to the 8051, especially when dealing with interrupts (we'll talk about interrupts later). However, always remember that the register banks really reside in the first 32 bytes of Internal RAM. 2.2.5 THE "B" REGISTER: The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte) value. The "B" register is only used implicitly by two 8052 instructions: MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or divide A by another number, you may store the other number in "B" and make use of these two instructions. Aside from the MUL and DIV instructions, the B register are often used as yet another temporary storage register much like a ninth "R" register.
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2.2.6 THE PROGRAM COUNTER (PC): The Program Counter (PC) is a 2-byte address that tells the 8051 where the next instruction to execute is found in memory. When the 8051 is initialized PC always starts at 0000h and is incremented each time an instruction is executed. It is important to note that PC isnt always incremented by one. Since some instructions are 2 or 3 bytes in length the PC will be incremented by 2 or 3 in these cases. The Program Counter is special in that there is no way to directly modify its value. That is to say, you cant do something like PC=2430h. On the other hand, if you execute LJMP 2430h youve effectively accomplished the same thing. It is also interesting to note that while you may change the value of PC (by executing a jump instruction, etc.) there is no way to read the value of PC. That is to say, there is no way to ask the 8051 "What address are you about to execute?" As it turns out, this is not completely true: There is one trick that may be used to determine the current value of PC. 2.2.7 THE DATA POINTER (DPTR): The Data Pointer (DPTR) is the 8051s only user-accessible 16bit (2-byte) register. The Accumulator, "R" registers, and "B" register are all 1byte values. The PC just described is a 16-bit value but isnt directly useraccessible as a working register. DPTR, as the name suggests, is used to point to data. It is used by a number of commands that allow the 8051 to access external memory. When the 8051 accesses external memory it accesses the memory at the address indicated by DPTR. While DPTR is most often used to point to data in external memory or code memory, many developers take advantage of the fact that its the only true 16-bit register available. It is often used to store 2-byte values that have nothing to do with memory locations.

2.2.8 THE STACK POINTER (SP): The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value. The Stack Pointer is used to indicate where the next value to be removed from the stack should be taken from. When you push a value onto the stack, the 8051 first increments the value of SP and then stores the value at the resulting memory location. When you pop a value off the stack, the 8051 returns the value from the memory location indicated by SP and then decrements the value of SP. This order of operation is important. When the 8051 is initialized SP will be initialized to 07h. If you immediately push a value onto the stack, the value will be stored in Internal RAM address 08h. This makes sense taking into account what was mentioned two paragraphs above: First the 8051 will increment the value of SP (from 07h to 08h) and then will store the pushed value at that memory address (08h). SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an interrupt is triggered (more on interrupts later. Dont worry about them for now!).

2.2.9 INPUT / OUTPUT PORTS: The 8051s I/O port structure is extremely versatile and flexible. The device has 32 I/O pins configured as four eight bit parallel ports (P0, P1, P2 and P3). Each pin can be used as an input or as an output under the software control. These I/O pins can be accessed directly by memory instructions during program execution to get required flexibility.

These port lines can be operated in different modes and all the pins can be made to do many different tasks apart from their regular I/O function executions. Instructions, which access external memory, use port P0 as a multiplexed address/data bus. At the beginning of an external memory cycle, low order 8 bits of the address bus are output on P0. The same pins transfer data byte at the later stage of the instruction execution. Also, any instruction that accesses external Program Memory will output the higher order byte on P2 during read cycle. Remaining ports, P1 and P3 are available for standard I/O functions. But all the 8 lines of P3 support special functions: Two external interrupt lines, two counter inputs, serial ports two data lines and two timing control strobe lines are designed to use P3 port lines. When you dont use these special functions, you can use corresponding port lines as a standard I/O. Even within a single port, I/O operations may be combined in many ways. Different pins can be configured as input or outputs independent of each other or the same pin can be used as an input or as output at different times. You can comfortably combine I/O operations and special operations for Port 3 lines. 2.2.10 TIMERS / COUNTERS: 8051 has two 16 bit Timers/Counters capable of working in different modes. Each consists of a High byte and a Low byte which can be accessed under software. There is a mode control register and a control register to configure these timers/counters in number of ways. These timers can be used to measure time intervals, determine pulse widths or initiate events with one microsecond resolution up to a maximum of 65 millisecond (corresponding to 65, 536 counts). Use software to get longer delays. Working as counter, they can accumulate occurrences of external events (from DC to 500 KHz) with 16 bit precision.

Fig-Modes of Timer Registers 2.2.11 SERIAL PORT: Each 8051 microcomputer contains a high speed full duplex (means you can simultaneously use the same port for both transmitting and receiving purposes) serial port which is software configurable in 4 basic modes: 8 bit UART; 9 bit UART; Internal processor Communications link or as shift register I/O expander. For the standard serial communication facility, 8051 can be programmed for UART operations and can be connected with regular personal computers, teletype writers, modem at data rates between 122 bauds and 31 kilo bauds. Getting this facility is made very simple using simple routines with option to select even or odd parity. You can also establish a kind of internal processor
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communication facility among many microcomputers in a distributed environment with automatic recognition of address/data. Apart from all above, you can also get super fast I/O lines using low cost simple TTL or CMOS shift registers. TMOD: This register is the timer mode selection register. It can be used for 64k external memory. There are totally 8bits they are,
GATE C/T M1 M0 GATE C/T M1 M0

The first four bits corresponds to timer 1 The rest four bits corresponds to timer 0
MODE0 00 13 bit Pre scalar timer/ counter MODE1 01 16 bit timer/counter MODE2 10 8 bit mode auto reload MODE3 11 Split timer mode

Depending upon the values of the modes m1&m0, the mode selection operation is chosen.

TCON: The TCON register is the timer control register. It contains the run control and the over flow, edge trigger and the level trigger flags. This also contains the interrupts and timer also. There are totally 8 bits here.
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TF1 TIMER 1

TR1

TF0 TIMER0

TR0

IE1

IT1

IE0

IT0

INTERRUPTS

TF1 & TF0 Corresponds to timer overflow flag of mode 1 and mode0.TR0& TR1 Corresponds to run control flag of mode 1 and mode0The rest are interrupts SCON:
SMO SM1 SM2 REN TB8 RS8 TI RI

It is used for serial communication. the total no of bits here is also the same 8.
SM0 SM1 MODE OPERATION TRANSMISSION RATE 0 0 1 1 0 1 0 1 0 1 2 3 Shift reg. 8 bit UART 9 bit UART 9 BIT UART Fixed Variable Fixed Variable

The sm0 and sm1 is used for bit mode selection. Depending upon these two values the operation is performed. The sm2 is used for multipurpose transmission.REN is the receiver enable bit. When the bits are to be received this is made high.TB8, RS8, these bits are used to tell whether the 8 bits are transmitted. The TI & RI are transmitting and receive interrupts.

PCON: The PCON is the power control register. This register is mainly used for power consumption. Baud rate can be changed by using this register. This also contains totally 8 bits.
SMOD GF1 GF0 PDM IDL

When s mod is 0 implies 57600hz

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When s mod is 1 implies 28800hz.

SERIAL BUFFER: This buffer is used for converting the datas to ASCII language which is loaded in PC.This is used for storing single bit. Pin diagram:

. Fig-pin Diagram

2.2.12 Pin Description: VCC GND Port 0 Supply voltage. Ground Port 0 is an 8-bit open drain bi-directional I/O port. As an output

port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be
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the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups.

The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.

P3.1 (TXD)

The UART/serial port uses P3.1 as the transmit line. In

circuit designs that will be using the microcontrollers internal serial port, this is the line that the microcontroller will clock out all data which is written to the SBUF SFR. Note that when interfacing an 8052 to an RS-232 port that you may not connect this line directly to the RS-232 pin; rather, you must pass it through a part such as the MAX232 to obtain the correct voltage levels. This pin is available for any use the developer may assign it if the circuit has no need to transmit data via the integrated serial port.

P3.2 (INT0)

When so configured, this line is used to trigger an External

0 Interrupt. This may either be low-level triggered or may be triggered on a 1-0 transition. Please see the chapter on interrupts for details. This pin is available for any use the developer may assign it if the circuit does not need to trigger an external 0 interrupt.
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P3.3 (INT1)

When so configured, this line is used to trigger an External 1

Interrupt. This may either be low-level triggered or may be triggered on a 1-0 transition. Please see the chapter on interrupts for details. This pin is available for any use the developer may assign it if the circuit does not need to trigger an external 1 interrupt.

P3.4 (T0)

When so configured, this line is used as the clock source for

timer 0. Timer 0 will be incremented either every instruction cycle that T0 is high or every time there is a 1-0 transition on this line, depending on how the timer is configured. Please see the chapter on timers for details. This pin is available for any use the developer may assign it if the circuit does not to control timer 0 externally.

P3.5 (T1)

When so configured, this line is used as the clock source for

timer 1. Timer 1 will be incremented either every instruction cycle that T1 is high or every time there is a 1-0 transition on this line, depending on how the timer is configured. Please see the chapter on timers for details. This pin is available for any use the developer may assign it if the circuit does not to control timer 1 externally.

P3.6 (WR)

This is external memory write strobe line. This line will be

asserted low by the microcontroller whenever a MOVX instruction writes to external RAM. This line should be connected to the RAMs write (-W) line. This pin is available for any use the developer may assign it if the circuit does not write to external RAM using MOVX.

P3.7 (RD)

This is external memory write strobe line. This line will be

asserted low by the microcontroller whenever a MOVX instruction writes to external RAM. This line should be connected to the RAMs write (-W) line. This pin is available for any use the developer may assign it if the circuit does not read from external RAM using MOVX. RST Reset input. A high on this pin for two machine cycles while

the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled ALE/PROG Address Latch Enable (ALE) is an output pulse for latching

the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode PSEN Program Store Enable (PSEN) is the read strobe to external

program memory. When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order

to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed,
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EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming. XTAL1 Input to the inverting oscillator amplifier and input to the internal

clock operating circuit. XTAL2 Output from the inverting oscillator amplifier

2.2.13 OSCILLATOR CHARACTERISTICS: XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by two flipflop, but minimum and maximum voltage high and low time specifications must be observed.

AT89S51 CLOCK: AT89S51 has an on-chip oscillator It needs an external crystal Crystal decides the operating frequency of the 8051

IDLE MODE: In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. POWER DOWN MODE: In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The onchip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. AT89S51 RESET:
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RESET is an active High input When RESET is set to High, 8051 goes back to the power on state Power-On Reset Push PB and active High on RST Release PB, Capacitor discharges and RST goes low RST must stay high for a min of 2 machine cycles

Figure-reset circuit

2.2.14 Special Function Registers: A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
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Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H- 83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power off Flag: The Power off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1 during power up. It can be set and rest under software control and is not affected by reset. 2.2.15 MEMORY ORGANIZATION: The 8051 architecture provides both on chip memory as well as off chip memory expansion capabilities. It supports several distinctive physical address spaces, functionally separated at the hardware level by different addressing mechanisms, read and write controls signals or both: On chip Program Memory On chip Data Memory Off chip Program Memory Off chip Data Memory On chip Special Function Registers The Program Memory area (EPROM in case of external memory or Flash/EPROM in case of internal one) is extremely large and never lose information when the power is removed. Program Memory is used for information needed each time power is applied: Initialization values, Calibration data, Keyboard lookup tables etc along with the program itself. The Program Memory has a 16 bit address and any particular memory location is addressed

using the 16 bit Program Counter and instructions which generate a 16 bit address. On chip Data memory is smaller and therefore quicker than Program Memory and it goes into a random state when power is removed. On chip RAM is used for variables which are calculated when the program is executed. In contrast to the Program Memory, On chip Data Memory accesses need a single 8 bit value (may be a constant or another variable) to specify a unique location. Since 8 bits are more than sufficient to address 128 RAM locations, the on chip RAM address generating register is single byte wide. Different addressing mechanisms are used to access these different memory spaces and this greatly contributes to microcomputers operating efficiency. The 64K byte Program Memory space consists of an internal and an external memory portion. If the EA pin is held high, the 8051 executes out of internal Program Memory unless the address exceeds 0FFFH and locations 1000H through FFFFH are then fetched from external Program Memory. If the EA pin is held low, the 8051 fetches all instructions from the external Program Memory. In either case, the 16 bit Program Counter is the addressing mechanism.

Figure - Program Memory

The Data Memory address space consists of an internal and an external memory space. External Data Memory is accessed when a MOVX instruction is executed. Apart from on chip Data Memory of size 128/256 bytes, total size of Data Memory can be expanded up to 64K using external RAM devices. Total internal Data Memory is divided into three blocks: Lower 128 bytes. Higher 128 bytes Special Function Register space.

Fig-Data Memory address space

Even though the upper RAM area and SFR area share same address locations, they are accessed through different addressing modes. Direct addresses higher than 7FH access SFR memory space and indirect addressing above 7FH access higher 128 bytes.

Figure - Internal Data Memory The next figure indicates the layout of lower 128 bytes. The lowest 32 bytes (from address 00H to 1FH) are grouped into 4 banks of 8 registers. Program instructions refer these registers as R0 through R7. Program Status Word indicates which register bank is being used at any point of time.

Figure - Lower 128 Bytes of Internal RAM

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The next 16 bytes above these register banks form a block of bit addressable memory space. The instruction set of 8031 contains a wide range of single bit processing instructions and these instructions can directly access the 128 bits of this area. The SFR space includes port latches, timer and peripheral control registers. All the members of 8051 family have same SFR at the same SFR locations. There are some 16 unique locations which can be accessed as bytes and as bits. COMMON MEMORY SPACE: The 8051s Data Memory may not be used for program storage. So it means you cant execute instructions out of this Data Memory. But, there is a way to have a single block of off chip memory acting as both Program and Data Memory. By gating together both memory read controls (RD and PSEN) using an AND gate, a common memory read control signal can be generated.

In this arrangement, both memory spaces are tied together and total accessible memory is reduced from 128 Kbytes to 64 Kbytes. The 8051 can read and write into this common memory block and it can be used as Program and Data Memory. You can use this arrangement during program development and debugging phase. Without taking Microcontroller off the socket to program its internal ROM (EPROM/Flash ROM), you can use this common memory for frequent program storage and code modifications. Watchdog Timer (One-time Enabled with Reset-out): The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in
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sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin. Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. WDT During Power-down and Idle: In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The
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interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and renters IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE. Interrupts: The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 10-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 10-1 shows that bit positions IE.6 and IE.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. Note: C1, C2 = 30 pF 10 pF for Crystals = 40 pF 10 pF for Ceramic Resonators IE1 IE0 1100 TF1 TF0 INT1 INT0 TI RI C2 XTAL2 GND XTAL1 Programming the Flash Serial Mode:
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The Code memory array can be programmed using the serial ISP interface while RST is pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before other operations can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required. The Chip Erase operation turns the content of every memory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz

Serial Programming Algorithm: To program and verify the AT89S51 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. b. Set RST pin to H. If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 16. 3. The Code array is programmed one byte at a time in either the Byte or Page mode. The write cycle is self-timed and typically takes less than 0.5 ms at 5V. 4. Any memory location can be verified by using the Read instruction that returns the con-tent at the selected address at serial output MISO/P1.6.

5. At the end of a programming session, RST can be set low to commence normal device operation. Power-off sequence (if needed): 1. Set XTAL1 to L (if a crystal is not used). 2. Set RST to L. 3. Turn VCC power off. 2.2.16 RS232 Serial Communication: Serial communication is basically the transmission or reception of data one bit at a time. Today's computers generally address data in bytes or some multiple thereof. A byte contains 8 bits. A bit is basically either a logical 1 or zero. Every character on this page is actually expressed internally as one byte. The serial port is used to convert each byte to a stream of ones and zeroes as well as to convert streams of ones and zeroes to bytes. The serial port contains a electronic chip called a Universal Asynchronous Receiver/Transmitter (UART) that actually does the conversion. The serial port has many pins. We will discuss the transmit and receive pin first. Electrically speaking, whenever the serial port sends a logical one (1) a negative voltage is effected on the transmit pin. Whenever the serial port sends a logical zero (0) a positive voltage is affected. When no data is being sent, the serial port's transmit pin's voltage is negative (1) and is said to be in a MARK state. Note that the serial port can also be forced to keep the transmit pin at a positive voltage (0) and is said to be the SPACE or BREAK state. (The terms MARK and SPACE are also used to simply denote a negative voltage (1) or a positive voltage (0) at the transmit pin respectively). When transmitting a byte, the UART (serial port) first sends a START BIT which is a positive voltage (0), followed by the data (general 8 bits, but could be 5, 6, 7, or 8 bits) followed by one or two STOP BITs which is a negative(1) voltage. The sequence is repeated for each byte sent. Figure 1 shows a diagram of a byte transmission would look like.

At this point you may want to know what the duration of a bit is. In other words, how long does the signal stay in a particular state to define a bit. The answer is simple. It is dependent on the baud rate. The baud rate is the number of times the signal can switch states in one second. Therefore, if the line is operating at 9600 baud, the line can switch states 9,600 times per second. This means each bit has the duration of 1/9600 of a second or about 100 sec. When transmitting a character there are other characteristics other than the baud rate that must be known or that must be setup. These characteristics define the entire interpretation of the data stream. The first characteristic is the length of the byte that will be transmitted. This length in general can be anywhere from 5 to 8 bits. The second characteristic is parity. The parity characteristic can be even, odd, mark, space, or none. If even parity, then the last data bit transmitted will be a logical 1 if the data transmitted had an even amount of 0 bits. If odd parity, then the last data bit transmitted will be a logical 1 if the data transmitted had an odd amount of 0 bits. If MARK parity, then the last transmitted data bit will always be a logical 1. If SPACE parity, then the last transmitted data bit will always be a logical 0. If no parity then there is no parity bit transmitted. The third characteristic is the amount of stop bits. This value in general is 1 or 2. Assume we want to send the letter 'A' over the serial port. The binary representation of the letter 'A' is 01000001. Remembering that bits are transmitted from least significant bit (LSB) to most significant bit (MSB), the
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bit stream transmitted would be as follows for the line characteristics 8 bits, no parity, 1 stop bit, 9600 baud. LSB (0 1 0 0 0 0 0 1 0 1) MSB The above represents (Start Bit) (Data Bits) (Stop Bit) To calculate the actual byte transfer rate simply divide the baud rate by the number of bits that must be transferred for each byte of data. In the case of the above example, each character requires 10 bits to be transmitted for each character. As such, at 9600 baud, up to 960 bytes can be transferred in one second. The above discussion was concerned with the "electrical/logical" characteristics of the data stream. We will expand the discussion to line protocol. Serial communication can be half duplex or full duplex. Full duplex communication means that a device can receive and transmit data at the same time. Half duplex means that the device cannot send and receive at the same time. It can do them both, but not at the same time. Half duplex communication is all but outdated except for a very small focused set of applications. Half duplex serial communication needs at a minimum two wires, signal ground and the data line. Full duplex serial communication needs at a minimum three wires, signal ground, transmit data line, and receive data line. The RS232 specification governs the physical and electrical characteristics of serial communications. This specification defines several additional signals that are asserted (set to logical 1) for information and control beyond the data signals and signal ground. These signals are the Carrier Detect Signal (CD), asserted by modems to signal a successful connection to another modem, Ring Indicator (RI), asserted by modems to signal the phone ringing, Data Set Ready (DSR), asserted by modems to show their presence, Clear To Send (CTS), asserted by modems if they can receive data, Data Terminal Ready (DTR), asserted by terminals to
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show their presence, Request To Send (RTS), asserted by terminals if they can receive data. The section RS232 Cabling describes these signals and how they are connected. The above paragraph alluded to hardware flow control. Hardware flow control is a method that two connected devices use to tell each other electronically when to send or when not to send data. A modem in general drops (logical 0) its CTS line when it can no longer receive characters. It re-asserts it when it can receive again. A terminal does the same thing instead with the RTS signal. Another method of hardware flow control in practice is to perform the same procedure in the previous paragraph except that the DSR and DTR signals are used for the handshake. Note that hardware flow control requires the use of additional wires. The benefit to this however is crisp and reliable flow control. Another method of flow control used is known as software flow control. This method requires a simple 3 wire serial communication link, transmit data, receive data, and signal ground. If using this method, when a device can no longer receive, it will transmit a character that the two devices agreed on. This character is known as the XOFF character. This character is generally a hexadecimal 13. Simple null modem without handshaking

Connector 1 Connector 2 Function 2 3 5 3 2 5 Rx Tx Tx Rx

Signal ground

Figure-handshaking signals connection Max 232: The Microcontroller and the PC are connected using the Max232 IC for the proper communication. The Microcontroller works with the logic of TTL logic, where as the PC works with the RS232 logic hence to connect the PC and microcontroller a logic converter is needed .here the Max 232 is used as level converter .the circuit diagram of Max 232 can be shown as
V D D C 11 0 u F

16

VC C

R T C 2 1 0 X

I N 8 R 1 I N 1 1 R 2 I N 1 0 T 1 I N T 2 I N 1 3 4 5 6 C C C C V 4 + 1 2 2 + M A

V+

R R T T

1 2

1 2

O O O O 3 2

1 2 9U T 1U 4 T 7U T T U T

R 2 O U T

X 2

C 3 1 0

2.3 RFID Reader Module:

2.3.1 Introduction: The Radio Frequency Identification (RFID) Reader Module is the first low-cost solution to read passive RFID transponder tags up to 1 - 3 inches away depending on the tag (see list below). The RFID Reader Module can be used in a wide variety of hobbyist and commercial applications,
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15 F

G N D

including access control, automatic identification, robotics navigation, inventory tracking, payment systems, and car immobilization. Fully-integrated, low-cost method of reading passive RFID transponder tags Single-wire, 2400 baud Serial TTL interface to PC, BASIC Stamp and other processors Requires single +5VDC supply

Bicolour LED for visual indication of activity0.100 pin spacing for easy prototyping and integration Radio Frequency.

2.3.2 Applications: Wireless mouse, keyboard Wireless data communication Alarm and security systems Home Automation, Remote control Automotive Telemetry Intelligent sports equipment Handheld terminals, Data loggers Industrial telemetry and tele-communications In-building environmental monitoring and control High-end security and fire alarms

Fig-RFID Module 2.3.3 TRANSMITTER: The TWS-434 extremely small, and are excellent for applications requiring short-range RF remote controls. The transmitter module is only 1/3 the size of a standard postage stamp, and can easily be placed inside a small plastic enclosure. TWS-434: The transmitter output is up to 8mW at 433.92MHz with a range of approximately 400 foot (open area) outdoors. Indoors, the range is approximately 200 foot, and will go through most walls.

Fig - transmitter The TWS-434 transmitter accepts both linear and digital inputs, can operate from 1.5 to 12 Volts-DC, and makes building a miniature hand-held RF transmitter very easy. The TWS-434 is approximately 1/3 the size of a standard postage stamp.

Fig -TWS-434 Pin Diagram

Fig- Transmitter Application Circuit 2.3.4 RECEIVER: RWS-434: The receiver also operates at 433.92MHz, and has a sensitivity of 3uV. The WS-434 receiver operates from 4.5 to 5.5 volts-DC and has both linear and digital outputs

Fig-RF Receiver

2.3.5 HT12E Encoder: General Description: The 212 encoders are a series of CMOS LSIs for remote control system applications. They are capable of encoding information which consists of N address bits and 12_N data bits. Each address/ data input can be set to one of the two logic states. The programmed addresses/data are transmitted together with the header bits via an RF or an infrared transmission medium upon receipt of a trigger signal. The capability to select a TE trigger on the HT12E or a DATA trigger on the HT12A further enhances the application flexibility of the 212 series of encoders. Features: Operating voltage 2.4V~12V for the HT12E Low power and high noise immunity CMOS technology Low standby current: 0.1_A (typ.) at VDD=5V Minimum transmission word Four words for the HT12E Built-in oscillator needs only 5% resistor Data code has positive polarity Minimal external components HT12E: 18-pin DIP/20-pin SOP package

Applications:
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 Burglar alarm system Smoke and fire alarm system Garage door controllers Car door controllers Car alarm system Security system Cordless telephones Other remote control system

Block Diagram

Fig- Encoder Block diagram

The 2 12 decoders are a series of CMOS LSIs for remote control system applications. They are paired with Holtek s 212 series of encoders (refer to the encoder/decoder cross reference table). For proper operation, a pair of encoder/decoder with the same number of addresses and data format should be chosen. The decoders receive serial addresses and data from a programmed 2 12 series of encoders that are transmitted by a carrier using an RF or an IR transmission medium. They compare the serial input data three times continuously with their local addresses. If no error or unmatched codes are found, the input data codes are decoded and then transferred to the output pins. The VT pin also goes high to indicate a valid transmission. The 212 series of decoders are capable of decoding informations that consist of N bits of address and 12_N bits of data. Of this series, the HT12D is arranged to provide 8 address bits and 4 data bits, and HT12F is used to decode 12 bits of address information.

2.3.6 HT-12D Decoder:

Fig- Decoder block Diagram Description: The 2^12 decoders are a series of CMOS LSIs for remote control system applications. They are paired with Holtek_s 2 ^12 series of encoders (refer to the encoder/decoder cross reference table). For proper operation, a pair of encoder/decoder with the same number of addresses and data format should be chosen. The decoders receive serial addresses and data from a programmed 2^12 series of encoders that are transmitted by a carrier using an RF or an IR transmission medium. They compare the serial input data three times continuously with their local addresses. If no error or unmatched codes are found, the input data codes are decoded and then transferred to the output pins.

The VT pin also goes high to indicate a valid transmission. The 2^12 series of decoders are capable of decoding informations that consist of N bits of address and 12_N bits of data. Of this series, the HT12D is arranged to provide 8 address bits and 4 data bits, and HT12F is used to decode 12 bits of address information.

Functional Description: The 2^12 series of decoders provides various combinations of addresses and data pins in different packages so as to pair with the 2^12 series of encoders. The decoders receive data that are transmitted by an encoder and interpret the first N bits of code period as addresses and the last 12_N bits as data, where N is the address code number. A signal on the DIN pin activates the oscillator which in turn decodes the incoming address and data. The decoders will then check the received address three times continuously. If the received address codes all match the contents of the decoders local address, the 12_N bits of data are decoded to activate the output pins and the VT pin is set high to indicate a valid transmission. This will last unless the address code is incorrect or no signal is received. The output of the VT pin is high only when the Transmission is valid. Otherwise it is always slow.

2.3.7 TRANSMIT AND RECEIVE DATA:

GENERATING DATA: The TWS-434 modules do not incorporate internal encoding. If you want to send simple control or status signals such as button presses or switch closures, consider using an encoder and decoder IC set that takes care of all encoding, error checking, and decoding functions. These chips are made by Motorola and Holtek. They are an excellent way to implement basic wireless transmission control. RECEIVER DATA OUTPUT: A 0 volt to Vcc data output is available on pins. This output is normally used to drive a digital decoder IC or a microprocessor which is performing the data decoding. The receivers output will only transition when valid data is present. In instances when no carrier is present the output will remain low. DECODING DATA: The RWS-434 modules do not incorporate internal decoding. If you want to receive Simple control or status signals such as button presses or switch closures, you can use the encoder and decoder IC set described above. Decoders with momentary and latched outputs are available. TRANSMITTING AND RECEIVING: Full duplex or simultaneous two-way operation is not possible with these modules. If a transmit and receive module are in close proximity and data is sent to a remote receive module while attempting to simultaneously receive data from a remote transmit module, the receiver will be overloaded by its close proximity transmitter. This will happen even if encoders and decoders are used

with different address settings for each transmitter and receiver pair. If two way communication is required, only half duplex operation is allowed. 2.3.8 ANTENNAS- WIRE WHIP: The WC418 is made of 26 gauge carbon steel music wire that can be soldered to a PC board. This antenna has a plastic coated tip for safety and is 6.8 inches long, allowing .1 inch for insertion in a terminal or PC board.

Figure Antenna

Antenna: The following should help in achieving optimum antenna performance: Proximity to objects such a users hand or body, or metal objects will cause an antenna to detune. For this reason the antenna shaft and tip should be positioned as far away from such objects as possible. Optimum performance will be obtained from a 1/4 or 1/2 wave straight whip mounted at a right angle to the ground plane. A 1/4 wave antenna for 418 MHz is 6.7 inches long. In many antenna designs, particularly 1/4 wave whips, the ground plane acts as a counterpoise, forming in essence, a 1/2 wave dipole. Adequate ground plane area will give maximum performance. As a general rule the ground plane to be used as counterpoise should have a surface area => the overall length of the 1/4 wave radiating element (2.6 X 2.6 inches for a 6.7 inch long antenna).

Remove the antenna as far as possible from potential interference sources. Place adequate ground plane under all potential sources of noise.

Electronic Connections: The Parallax RFID Reader Module can be integrated into any design using only four connections (VCC,/ENABLE, SOUT, GND). Use the following circuit for Connecting the Parallax RFID Reader Module to the BASIC Stamp microcontroller:

DC Characteristics:

2.3.9 RFID Technology Overview: Material in this section is based on information provided by the RFID Journal. Radio Frequency Identification (RFID) is a generic term for non-contacting technologies that use radio waves to automatically identify people or objects. There are several methods of identification, but the most common is to store a unique serial number that identifies a person or object on a
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microchip that is attached to an antenna. The combined antenna and microchip are called an "RFID transponder" or "RFID tag" and work in combination with an "RFID reader" (sometimes called an "RFID interrogator"). An RFID system consists of a reader and one or more tags. The reader's antenna is used to transmit radio frequency (RF) energy. Depending on the tag type, the energy is "harvested" by the tag's antenna and used to power up the internal circuitry of the tag. The tag will then modulate the electromagnetic waves generated by the reader in order to transmit its data back to the reader. The reader receives the modulated waves and converts them into digital data. In the case of the Parallax RFID Reader Module, correctly received digital data is sent serially through the SOUT pin. There are two major types of tag technologies. "Passive tags" are tags that do not contain their own power source or transmitter. When radio waves from the reader reach the chips antenna, the energy is converted by the antenna into electricity that can power up the microchip in the tag (known as "parasitic power"). The tag is then able to send back any information stored on the tag by reflecting the electromagnetic waves as described above. "Active tags" have their own power source and transmitter. The power source, usually a battery, is used to run the microchip's circuitry and to broadcast a signal to a reader. Due to the fact that passive tags do not have their own transmitter and must reflect their signal to the reader, the reading distance is much shorter than with active tags. However, active tags are typically larger, more expensive, and require occasional service. The RFID Reader Module is designed specifically for low-frequency (125 kHz) passive tags. Frequency refers to the size of the radio waves used to communicate between the RFID system components. Just as you tune your radio to different frequencies in order to hear different radio stations, RFID tags and readers have to be tuned to the same frequency in order to communicate effectively. RFID systems typically use one of the following frequency ranges: low frequency (or
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LF, around 125 kHz), high frequency (or HF, around 13.56 MHz), ultra-high frequency (or UHF, around 868 and 928 MHz), or microwave (around 2.45 and 5.8 GHz). It is generally safe to assume that a higher frequency equates to a faster data transfer rate and longer read ranges, but also more sensitivity to environmental factors such as liquid and metal that can interfere with radio waves. 2.3.10 Working of RFID module: Implementation and usage of the RFID Reader Module is straightforward. BASIC Stamp 1, 2, and SX28AC/DP code examples (SX/B) are included at the end of this documentation. The RFID Reader Module is controlled with a single TTL-level activelow /ENABLE pin. When the /ENABLE pin is pulled LOW, the module will enter its active state and enable the antenna to interrogate for tags. The current consumption of the module will increase dramatically when the module is active. A visual indication of the state of the RFID Reader Module is given with the on-board LED. When the module is successfully powered-up and is in an idle state, the LED will be GREEN. When the module is in an active state and the antenna is transmitting, the LED will be RED. The face of the RFID tag should be held parallel to the front or back face of the antenna (where the majority of RF energy is focused). If the tag is held sideways (perpendicular to the antenna) you'll either get no reading or a poor reading. Only one transponder tag should be held up to the antenna at any time. The use of multiple tags at one time will cause tag collisions and confuse the reader. The two tags available in the Parallax store have a read distance of approximately 3 inches. Actual distance may vary slightly depending on the size of the transponder tag and environmental conditions of the application. When a valid RFID transponder tag is placed within range of the activated reader, the
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unique ID will be transmitted as a 12-byte ASCII string via the TTL-level SOUT (Serial Output) pin in the following format:

The start byte and stop byte are used to easily identify that a correct string has been received from the reader (they correspond to a line feed and carriage return characters, respectively). The middle ten bytes are the actual tag's unique ID. All communication is 8 data bits, no parity, 1 stop bit, non-inverted, least significant bit first (8N1). The baud rate is configured for 2400bps, a standard communications speed supported by most any microprocessor or PC, and cannot be changed. The Parallax RFID Reader Module initiates all communication. The Parallax RFID Reader Module can connect directly to any TTL-compatible UART or to an RS232-compatible interface by using an external level shifter. Absolute Maximum Ratings and Electrical Characteristics

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

The decoded codes are transmitted to microcontroller (AT89S51). In the microcontroller the codes are verified and transmitted to PC through RS 232 serial cable. 2.4 Finger

print sensor:

2.4.1 Features: All-in-one Fingerprint module with USB connector. Easy to integrate with other devices Uses Fujitsu MBF200 Fingerprint Sensor Low Power 18 milliamps: Operating

500 micro amps: Standby

USB 1.1 compatible (to 13 FPS) 256 x 300 Pixel Array (50 m pixel pitch) 500 DPI resolution

8-bit gray scale (256 gray levels)

1

 On board A/D Converter Programmable gain control for image optimization 12.8mm x 15mm image area Lead-Free and ROHS compliant parts available 2.4.2 Description: The Fujitsu SPF200-USB is an all-in-one USB device. Simply connect it to your USB cable and you have a working fingerprint sensor! The SPF200-USB is ideal for integrating into devices where USB is the communication interface such as computer peripherals and embedded applications. Mount the SPF200-USB into your device and you have a completed product without going through the expense of board layout and debug. Users will no longer be required to remember and enter cumbersome passwords or PIN codes. Fingerprint authentication provides a reliable, quick and user friendly alternative to passwords. The SPF200-USB fingerprint sensor has the USB 1.1 controller logic built right into the sensor, no external hardware is required. Merely plug the sensor into the USB cable, the power and data communications is managed by the USB protocol. The Fujitsu SPF200-USB fingerprint sensor quickly captures the image of the fingerprint, analyzes it and compares it to a previously registered fingerprint template. The Fujitsu SPF200-USB fingerprint sensor consists of a 256 column x 300 row array of tiny metal electrodes. Each electrode acts as one plate in a capacitor and the finger acts as the second plate in a capacitor. A passivation layer on the surface of the device forms a tough outer shell, protecting the device from abrasion, chemicals, moisture and other forms of damage. The SPF200-USB is manufactured in standard CMOS technology, a mature and cost effective manufacturing method.

2.4.3 Applications:
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Computer peripherals improves security and convenience Physical access systems approval for entry Transportation systems validation of operators, drivers and inspectors Medical equipment authorization of operator or technician Kiosks and vending machines confirmation of person receiving the selection Point of Sale terminals authentication of tellers and cashiers 2.4.4 Specifications: Power: 5 volts DC (from USB) Operating Current: 18 milliamps Standby Current: 500 micro amps Fingerprint Sensor: MBF200 Operating Temperature: 0 to 60C Storage Temperature: -65 to 150C Resolution: 500 DPI, 8-bit gray scale

2.5 GSM Wireless Modems:

2.6.1 Introduction: A GSM modem is a wireless modem that works with a GSM wireless network. A wireless modem behaves like a dial-up modem. The main difference between them is that a dial-up modem sends and receives data through a fixed telephone line while a wireless modem sends and receives data through radio waves. A GSM modem can be an external device or a PC Card / PCMCIA Card. Typically, an external GSM modem is connected to a computer through a serial cable or a USB cable. A GSM modem in the form of a PC Card / PCMCIA Card is designed for use with a laptop computer. It should be inserted into one of the PC Card / PCMCIA Card slots of a laptop computer. Like a GSM mobile phone, a GSM modem requires a SIM card from a wireless carrier in order to operate. As mentioned in earlier sections of this SMS tutorial, computers use AT commands to control modems. Both GSM modems and dial-up modems support a common set of standard AT commands. You can use a GSM modem just like a dial-up modem. In addition to the standard AT commands, GSM modems support an extended set of AT commands. These extended AT commands are defined in the GSM standards. With the extended AT commands, you can do things like:

Reading, writing and deleting SMS messages. Sending SMS messages. Monitoring the signal strength. Monitoring the charging status and charge level of the battery. Reading, writing and searching phone book entries.

The number of SMS messages that can be processed by a GSM modem per minute is very low -- only about six to ten SMS messages per minute. 2.6.2 FACTS AND APPLICATIONS OF GSM/GPRS MODEM: The GSM/GPRS Modem comes with a serial interface through which the modem can be controlled using AT command interface. An antenna and a power adapter are provided. The basic segregation of working of the modem is as under

Voice calls

SMS GSM Data calls GPRS Voice calls: Voice calls are not an application area to be targeted. In future if interfaces like a microphone and speaker are provided for some applications then this can be considered. SMS: SMS is an area where the modem can be used to provide features like: Pre-stored SMS transmission These SMS can be transmitted on certain trigger events in an automation

system SMS can also be used in areas where small text information has to be sent. The transmitter can be an automation system or machines like vending machines, collection machines or applications like positioning systems where the navigator keeps on sending SMS at particular time intervals SMS can be a solution where GSM data call or GPRS services are not

available GSM Data Calls:

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Data calls can be made using this modem. Data calls can be made to a normal PSTN modem/phone line also (even received). Data calls are basically made to send/receive data streams between two units either PCs or embedded devices. The advantage of Data calls over SMS is that both parties are capable of sending/receiving data through their terminals. Some points to be remembered in case of data calls: The data call service doesnt come with a normal SIM which is purchased but has to be requested with the service provider (say Airtel). Upon activation of data/fax service you are provided with two separate numbers i.e. the Data call number and the Fax service number. Data calls are established using Circuit Switched data connections. 2.6.3 Operation of GSM: Devices that have communication on serial port either on PC or in the embedded environment. Devices that want to communicate with a remote server for data transfer The basic aim is to provide a wireless solution keeping the existing firmware intact. The clients firmware continues to work without any modifications (no changes in the existing software required). GSM data calls can be a good solution where data has to be transmitted from a hand-held device to a central server. The interface on two sides can be between PCs as well as embedded devices

Calls can be established by the terminals at either side to start data calls.
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 The Modem remains transparent during data transfer after the call is established. Call establishment utility to be provided in case PC terminals Call establishment to be automated in case of embedded terminals. Access control devices: Now access control devices can communicate with servers and security staff through SMS messaging. Complete log of transaction is available at the head-office Server instantly without any wiring involved and device can instantly alert security personnel on their mobile phone in case of any problem. RaviRaj Technologies is introducing this technology in all Fingerprint Access control and time attendance products. You can achieve high security any reliability. Transaction terminals: EDC machines, POS terminals can use SMS messaging to confirm transactions from central servers. The main benefit is that central server can be anywhere in the world. Today you need local servers in every city with multiple telephone lines. You save huge infrastructure costs as well as per transaction cost. Supply Chain Management: Today SCM require huge IT infrastructure with leased lines, networking devices, data centre, workstations and still you have large downtimes and high costs. You can do all this at a fraction of the cost with GSM M2M technology. A central server in your head office with GSM capability is the answer, you can receive instant transaction data from all your branch offices, warehouses and business associates with nil downtime and low cost. What applications is suitable for GSM communication? If your application needs one or more of the following features, GSM will be more cost-effective then other communication systems. Short Data Size:
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You data size per transaction should be small like 1-3 lines. e.g. banking transaction data, sales/purchase data, consignment tracking data, updates. These small but important transaction data can be sent through SMS messaging which cost even less than a local telephone call or sometimes free of cost worldwide. Hence with negligible cost you are able to send critical information to your head office located anywhere in the world from multiple points. You can also transfer faxes, large data through GSM but this will be as or more costly compared to landline networks. Multiple remote data collection points: If you have multiple data collections points situated all over your city, state, country or worldwide you will benefit the most. The data can be sent from multiple points like your branch offices, business associates, warehouses, agents with devices like GSM modems connected to PCs, GSM electronic terminals and Mobile phones. Many a times some places like warehouses may be situated at remote location may not have landline or internet but you will have GSM network still available easily. High uptime: If your business require high uptime and availability GSM is best suitable for you as GSM mobile networks have high uptime compared to landline, internet and other communication mediums. Also in situations where you expect that someone may sabotage your communication systems by cutting wires or taping landlines, you can depend on GSM wireless communication. Large transaction volumes: GSM SMS messaging can handle large number of transaction in a very short time. You can receive large number SMS messages on your server like emails without internet connectivity. E-mails normally get delayed a lot but SMS messages are almost instantaneous for instant transactions. consider situation like shop owners doing credit card transaction with GSM technology instead of conventional landlines. many a time you find local transaction servers busy as
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these servers use multiple telephone lines to take care of multiple transactions, whereas one GSM connection is enough to handle hundreds of transaction per minute. Mobility, Quick installation: GSM technology allows mobility, GSM terminals, modems can be just picked and installed at other location unlike telephone lines. Also you can be mobile with GSM terminals and can also communicate with server using your mobile phone.

CHAPTER-3
CONCLUSION This paper discusses on the implementation of wireless technology for student attendance system and updating students activities to their parents. This research has provides an excellent opportunity to study how human can be part of the system and integrate from information management to database system, integrated database system, wireless networking, computer and device interface. Wireless system is an emerging technology that should be included in education Field. Systematically, the proposed system can improve the manual procedures in managing attendance by incorporating technology elements into working system procedures. Reducing manpower, improving time management and Standard procedure, eliminating human error and flexibility, is the answers why Student Attendance System should be implemented. 3.1 FUTURE ENHANCEMENTS: The details such as Educational qualification, Health care, Age proof, Nativity, etc. of the G-ID holders can be updated in the web server. It can be accessed using their ID numbers. This can be used in many applications such as:

Voter ID: This design can be used for voting purpose i.e. the eligibility voters candidates can be identified and the number of votes polled in particular interval of time can be updated to the election commission office through GSM. Driving license: Using this technique the eligibility of the license holder to drive LCV, to batch holder can be identified with at most accuracy. In Hospitals: They can get the details such as Blood group, Address, Phone no of the patients with our G-ID when they met with an accident. Education details: The original qualification of the G-ID card holder is updated in server. For an example this details can be accessed for the verification by companies and other institution. PAN Card: This same G-ID can be used to provide the PAN card for ID holders. Family Card: The family card can also provided by using the same ID and by using this design the stock details can be updated to district office daily.

APPENDIX-i PROGRAM CODE: #include<stdio.h> #include<reg51.h> unsigned char ch;//Receiving sbit R_D1 = P2^0; sbit R_D2 = P2^1; sbit R_D3 = P2^2; sbit R_D4 = P2^3; sbit alarm = P0^0; void serial_init(void); void delay1(int); void delay2(int);//Serial To Test the Program void serial_init() { SCON = 0x50; // SCON: mode 1, 8-bit UART, enable rcvr TMOD |= 0x20; // TMOD: timer 1, mode 2, 8-bit reload TH1 = 0xFD; // TH1: reload value for 9600 baud @ 11.0592MHz TR1 = 1; TI=1; }//DELAY Routine void delay1(int n) {
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// TR1: timer 1 run

int i; for(i=0;i<n;i++); } void delay2(int n) { int i; for(i=0;i<n;i++) { delay1(1000); } }//Main Program void main(void) { P1=0x00; P0=0x00; P2=0xff; R_D1=1; R_D2=1; R_D3=1; EA=1; ES=1; serial_init();//Initialize serial port while(1)//loop forever { if(R_D1==0)
4

{ SBUF = 'A'; delay2(4); } if(R_D2==0) { SBUF = 'B'; delay2(4); } if(R_D3==0) { SBUF = 'C'; delay2(4); } if (R_D4==0) { SBUF = 'D'; delay2(4); }

} } void serial(void) interrupt 4 { int i;

6

ch=SBUF; if(RI==1) { if(ch=='Z') { for(i=0;i<12;i++) { alarm=1; delay2(10); alarm=0; delay2(7); } } //SCON=0x52; RI=0; } } APPENDIX-ii Specification of RF transmitter:
Symbol Parameter Vcc Icc Icc Vin Vii Operating voltage Peak Current (2V) Peak Current(12V) Input High Voltage Input Low Voltage supply Conditions Min 2.0 Typ Max 12 1.64 19.4 Vcc 0.3 Unit V mA mA V V

IData=100Ua (High) Vcc-0.5 IData=0Ua (Low) -

Fo

Absolute Frequency

433.72 433.92 417.8 418 +/-150 VCC 9V-12V VCC 5V-6V 16 14 512 4.8K -

434.12 MHz 418.2 MHz +/-200 KHz dBm

FO Po

Relative To 433.92MHz RF Out Power Into 50

Modulation Bandwidth Tf Modulation Fall Time

External Encoding

200K bps 100 uS

Notes : ( Case Temperature = +25C+/-2C Test Load Impedance = 50 )

APPENDIX-iii

Flash Programmer:

OrCAD - PCB Design:

REFERENCES [1] S. Gasson, Managing organizational change: the impact of

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information system development methods, Conference Proceedings of British Computer Society Special Interest Group on Information Systems Methodologies, Herriot-Watt University, UK, Sept. 1994. [2] Y. Zhang and J.Liu, The Design of Wireless Fingerprint Attendance System, Communication Technology, 2009. [3] P. G. Neumann, Responsibilities of Technologists, Communications of the ACM, Vol.48 (2), 2005, pp.128. [4] Utusan Malaysia, 25 Nov 2008. [5] J. Hagman, A. Hendrickson, and A. Whitty. Whats in a Barcode? Informed consent and machine scannable driver licenses, CHI 2003, Ft. Lauderdale, Florida, USA, 2003. [6] K. Kamijo, N. Kamijo and M. Sakamoto, Electronic Clipping System with Invisible Barcodes, MM06, October 2327, Santa Barbara, California, USA, 2006. [7] NEDA Supplier Guideline For 1-Dimensional Bar code & 2Dimensional Matrix Code Product Package & Shipment Labeling, May 2005.

WEBSITES REFERRED : 1.www.google.com 2.www.microcontroller.com 3.www.microchip.com 4.www.wikipedia.com 5.www.IEEE.com