Semiconductor technology: introduction to VLSI with Microwind 3.

Introduction DSCH and Microwind are computer aided design tools. Microwind works on a lower level of abstraction, where they geometry of materials on a transistor level is modeled, leading to variation in electrical characterisics. DSCH works on a higher level, with the main building blocks being logic gates. Also the logic editor will work for a range of different transistor models, at different scales and made from different materials. Abstraction is a very powerful tool in VLSI, it allows complex problems to be solved on a higher level, the lower level simulation can be done separately, perhaps by a completely separate company of university. Background to IC simulation

figure shows that the relative permittivity of the gate dielectric, as increased over time. This change has been necessary to increase the capacitance of the transistor.

Evaluation of gauses law show the capacitance is directly proportional to the dielectric constant; therefore the capacitance can be increased without increasing leakage current.

In industry this scaling effect is referred to in the context of moore law [1] relentless pressure and

silicon rapidly encroaching its miniaturization limits[2]

As more and more transistors are packed onto a semiconductor wafer the distance between identical features is reduced. 45nm technology means that the average half pitch on a memory cell is 45nm (half the distance between neighboring transistors.

Figure shows the three variants of 45nm technology. The choice depends on the application priorities. A mobile device will need to prolong the battery life, and is unlikely to be used for cpu intensive tasks. high end servers have their own power supply, therefore speed is their primary concern. Microwind is designed to model the general purpose variant of this technology.

DC characteristics of an n-channel MOS transistor (24-27)

Increasing the gate voltage causes an increase in source / drain current. Notice that the graphs start to level off when the transistor reaches saturation, meaning that an incrase in potential will no longer incrase the current How would you expect this to alter for different values of the gate width?

What is actually happening when we vary the geometry of the channel?

Width 1if the channel width is low then the resistance will be lower therefore the

Width 2

Width 3

Vertical aspect of MOS

Simulating transient characteristics(28-29) Apply clock to the gate and source and observe the drain

GATE Click on the Clock icon and then, click on the polysilicon gate. The clock menu appears again. Change the name into Vgate and click on OK to apply a clock with 0.1 ns period (45 ps at 0 , 5 ps rise, 45 ps at 1 , 5 ps fall).

Source

Apply a clock to the drain. Click on the Clock icon, click on the left diffusion. The Clock menu appears. Change the name into Vdrain and click on OK. A default clock with 0.2 ns period is generated. The Clock property is sent to the node and appears at the right hand side of the desired location with the name Vdrain. DRAIN Watch the output: Click on the Visible icon and then, click on the right diffusion. Click OK. The Visible property is then sent to the node. The associated text s1 is in italic, meaning that the waveform of this node will appear at the next simulation.

you may find that the "default" clock applied to the drain does not correspond to that shown in Fig. 2.7, in which case adjust the drain clock parameters by clicking on the drain to adjust them. Insert into your Word document a screenshot of the transient device characteristic you obtain. Describe in your own words what the transients characteristics show. Comparison of p-channel and n-channel MOS devices

Vertical aspect of MOS

Simulating transient characteristics(28-29) Download the file "pMOS.msk" from the VLE and save the file to your desktop (right-click the file and select desktop as the download location). Open the file in Microwind. Investigate the cross-section of the device, and say how it differs from the nchannel MOS device already investigated above. How would expect it's electrical characteristics to differ from those of the n-channel device? Simulate the DC and transient characteristics, and confirm whether your expectations are correct (you should include a screenshot of both the DC and transient characteristics in your discussion). Wide VLSI transistors suffer additional switching delays due to signal propagation when passing through the
1184 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 8, AUGUST 1996ate

polysilicide.

Effect of transistor geometry on transient effects You are asked to investigate the effect of channel geometry on the simulated transient characteristics (either the n-channel device or the p-channel). Alter the width and length of the channel and determine the effect this has on the transient characteristics, documenting your investigation as you go along (NB the "length" of the channel usually means the distance between the source and drain, while the "width" of the channel means the width of the path of current flow between source and drain). Describe any effects on the transient characteristics which you observe, and the possible reasons. Logic level editor - introduction

Figure shows the logic level representation of an inverter

This inverter (not gate) will output high when the input is low, and input low when the output is high. The timing diagram shows the inverted signal. A Low High nA High Low

Note, a common mistake is to assume that volts are on for logic 1 and off for logic 0. The inverter has on and off states that correspond to high and low voltages, which can be interpreted an either a 1 or a 0. A 0 1 nA 1 0

This logic level abstraction is useful to see what is going on in terms of inputs and outputs, however more can be understood by seeing what is going on under the hood.

n of CMOS inverter

Layout editor simulation of CMOS inverter (44 to 49 ) Start Microwind, and read pages 44 to 49 of the manual Now open cmos.msk from the toolbar menu,

TYPICAL study the V versus t

V verses I

V versus V waveforms

Minimum(slow, high temperature, low voltage)

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Maximum(fast, low temperature, high voltage)

The rise and fall times for the clock pulse are very short. Fourier analysis shows the this rising and falling edges are constructed of an large set of sinusoidal waves. The frequencies of which will be much larger than the clock pulse.

Noise margin

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When we have one transistor driving another it is important to make sure than a high voltage from the driving transistor is recognized as a high voltage on the driven transistor. If they were both designed with the same high and low voltage thresholds, it would be highly vulnerable to noise. Any small amount of noise would be enough to move an electron into the opposite region. The system is designed to remove this possibility. Firstly there is a forbidden intermediate region between the high and low regions. Also the range on the driver is smaller, meaning it is effectively working to tighter standards, this is refered to as a noise margin

what can you deduce from these in terms of the rise and fall times, gate propagation delays, gate threshold voltages (i.e. input voltage where output 50% of destination value) etc., and at different temperatures and process variations (i.e. for typical, and maximum and minimum conditions or typical, best and worst conditions). Try calculating the noise margins for this gate under typical conditions. Is there any difference for the best and worst processing and operating conditions?

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Now open the InvSteps.MSK file located in C:program files/Microwind 3.5/examples/inverter/

The Note that the polarization contact that the manual refers to is the same thing that Dr Steenson refers to as p-tap and n-tap or as a substrate contact and are used to ensure that the substrate doping in the channel is prevented from drifting to some indeterminate voltage and to try to avoid latchup the phenomenon that the Microwind manual refers to as to avoid short-circuit between VDD and VSS. Start a voltage versus time simulation, noting the input/output contacts which are being used in the setup of the simulation (NB only the completed inverter on the bottom right-hand-side is being simulated here). Describe the electrical characteristics you find. Referring to the top paragraph on page 50, explain why the switching characteristic changes over time.

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The first pulse rise is slower, this is because the Load the invSizing.msk file i.e. file>open>invSizing.msk file and look at the effect that the transistor scaling has on the switching i.e. the rise and fall time of the gate. Can you see any difference to the noise margins and gate threshold voltage as well?

Load the InvCapa.msk i.e. file>open>InvCapa.msk

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and investigate the effect that a large fan-out has on the switching (i.e. a large number of gates and long interconnects connected to the output will load the output in the same way as larger values of capacitance). Use the parametric analysis (from

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the toolbar choose, Analysis>Parametric Analysis then left mouse click in window) function to see the effect that this capacitance has on the rise and fall times.

Starting from an individual transistor we investigated the effect of modifying the geometry of the channel, and showed how this affected the IV characteristics. We then looked at the difference between n-channel and p-channel MOS devices. The next stage was to investigate how individual pmos and nmos transistors could be grouped together to from logic devices. We looked at the inverter (not GATE) in depth, and looked at how this architecture could be modified to from other higher level logic devices such as NAND XOR ect

[1] G.E. Moore, Electronics 38 (8) (1965).

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