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......................................................................... MSP430
ABSTRACT
The Power Management Module (PMM), Unified Clock System (UCS), Port Map (PMAP), and Flash modules are very flexible peripherals that require initialization within many applications. The MSP430F5xx and MSP430F6xx Core Library provide functions that implement the most common operations using the PMM, UCS, PMAP and Flash modules, such as changing the core voltage to operate at higher frequencies, crystal/clock initialization, mapping port I/O, and write/erase flash operations. This application note documents the definition and proper use of the available library calls. Project collateral and source code discussed in this application report can be downloaded from http://www.ti.com/lit/zip/slaa448.
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Contents PMM Library Files ........................................................................................................... 2 UCS Library Files ........................................................................................................... 7 Port Map Library Files .................................................................................................... 16 Flash Library Files ......................................................................................................... 17 Tag Length Value (TLV) Libraries ....................................................................................... 19 Associated Software ...................................................................................................... 22 References ................................................................................................................. 23 List of Figures
1 2 3
................................................................................... Changing VCORE and SVML / SVSL Levels ................................................................................ Latched OFIFG Architecture ...............................................................................................
System Frequency vs Supply Voltage List of Tables Recommended SVSH Settings
2 3 8
1 2 3 4 5 6
........................................................................................... ...........................................................................................
HAL_PMM Symbol Definitions ............................................................................................ 5 HAL_PMM Macro Definitions .............................................................................................. 5 Clock Sources on the MSP430 7 System Clocks and Functionality on the MSP430 ...................................................................... 7 HAL_UCS.h Macros ........................................................................................................ 9
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1 1.1
f2 2 f1 1 f0 1, 2 1, 2, 3 2, 3
0, 1
0, 1, 2
0, 1, 2, 3
Supply Voltage - V
Figure 1. System Frequency vs Supply Voltage Both the primary and secondary voltages, DVCC and VCORE, are protected by built-in SVM and SVS circuitry. Each SVM and SVS circuit is programmable to four voltage levels that map to the VCORE and minimum DVCC levels that are required for robust run-time behavior. The intended interaction between monitor and supervisor is as follows: the monitor has a threshold voltage slightly higher than the supervisor and triggers an interrupt in a decreasing voltage condition, so that the application can store any critical run-time parameters. If the voltage continues to fall and reaches the supervisor threshold, the PMM resets the device. For a detailed description of the SVS and SVM behavior and the status and error flags that are referenced in this application report, see the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208). [1]
NOTE: To align with the nomenclature in the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208) [1], the primary voltage domain (DVCC) is referred to as the high-side voltage (SVSH/SVMH) and the secondary voltage domain (VCORE) is referred to as the low-side voltage (SVSL/SVML).
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Moving between the different VCORE voltages requires a specific sequence of events and can be done only one level at a time; for example, to change from level 0 to level 3, the application code must step through level 1 and level 2. Figure 2 shows the sequence of events required to modify VCORE.
Voltage SVML
1 3 4 2 5
VCORE
6
SVSL Time
Figure 2. Changing VCORE and SVML / SVSL Levels VCORE increase: 1. 2. 3. 4. SVML monitor level is incremented. VCORE level is incremented. The SVML Level Reached Interrupt Flag (SVSMLVLRIFG) in the PMMIFG register is polled. When asserted, SVSMLVLRIFG indicates that the VCORE voltage has reached its next level. SVSL is increased. SVSL is changed last, because if SVSL were incremented prior to VCORE, it would potentially cause a reset.
The SetVCore() function appropriately handles an increase or decrease of the core voltage.
NOTE: The procedure recommended above provides a workaround for the erratum FLASH37. See the device-specific erratasheet to determine if a device is affected by FLASH37. The workaround is also highlighted in the source code for the PMM library (HAL_PMM.c).
1.2
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If the wake-up from low-power modes needs to be shortened to 5 s, the SVSL and SVML should be disabled after the initialization of the core voltage at the beginning of the application. Disabling SVSL and SVML prevents them from gating the CPU on wake-up from LPM2, LPM3, and LPM4. The application is still protected on the high side with SVSH and SVMH. The SetVCore() function automatically enables and disables the SVS and SVM as necessary if a non-zero core voltage level is required. If the application does not require a change in the core voltage (that is, when the target MCLK is less than 8 MHz), the DISABLE_SVSL_SVML() and ENABLE_SVSH_RESET() macros can be used to disable the low-side SVS and SVM circuitry and enable only the high-side SVS POR reset, respectively.
1.3
It is possible to set SVSMHRRL = 4, 5, 6, and 7 when the device is operating with SVSHRVL = 3 and PMMVCOREV = 3.
1.4
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Any writes to the SVSMLCTL and SVSMHCTL registers require a delay time for these registers to settle before the new settings take effect. This delay time is dependent on whether the SVS and SVM modules are configured for normal or full performance. See device-specific data sheet for exact delay times.
1.5
Description
(1)
Enables or disables the low-side SVS circuitry Enables or disables the low-side SVM circuitry Enables or disables the high-side SVS circuitry Enables or disables the high-side SVM circuitry Enables or disables the low-side SVS and SVM circuitry Enables or disables the high-side SVS and SVM circuitry Enables or disables the POR signal generation when a low-voltage event is registered by the low-side SVS Enables or disables the interrupt generation when a low-voltage event is registered by the low-side SVM Enables or disables the POR signal generation when a low-voltage event is registered by the high-side SVS Enables or disables the interrupt generation when a low-voltage event is registered by the high-side SVM Clear all interrupt flags for the PMM Enables supervisor low side in LPM with twake-up-fast (1) from LPM2, LPM3, and LPM4 Enables supervisor low side in LPM with twake-up-slow (1) from LPM2, LPM3, and LPM4 Disables supervisor low side in LPM with twake-up-fast (1) from LPM2, LPM3, and LPM4 Disables supervisor low side in LPM with twake-up-slow (1) from LPM2, LPM3, and LPM4 Enables supervisor high side in LPM with tpd = 20 s (1) Enables supervisor high side in LPM with tpd = 2.5 s (1) Disables supervisor high side in LPM with tpd = 20 s (1) Disables supervisor high side in LPM with tpd = 2.5 s (1) Optimized to provide twake-up-fast (1) from LPM2, LPM3, and LPM4 with least power Optimized to provide tpd = 2.5 s (1) in LPM with least power
See device-specific data sheet for accurate values of tpd and twake-up.
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1.5.1
uint16_t SetVCore(uint8_t level) Description Sets the appropriate VCORE level. Calls the static SetVCoreUp() or SetVCoreDown() function the required number of times depending on the current VCORE level, because the levels must be stepped through individually. Parameters level The target VCORE level Returns A status indicator equal to zero (PMM_STATUS_OK) or one (PMM_STATUS_ERROR) that indicates a valid or invalid VCORE transition, respectively. An invalid VCORE transition exists if DVCC is less than the minimum required voltage for the target VCORE voltage.
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2 2.1
System clocks of the MSP430x5xx generation are automatically enabled, regardless of the LPM mode of operation, if they are required for the proper operation of the peripheral module that they source. This additional flexibility of the UCS, along with improved fail-safe logic, provides a robust clocking scheme for all applications. 2.1.1 Fail-Safe Logic The UCS fail-safe logic plays an important part in providing a robust clocking scheme for MSP430x5xx and MSP430x6xx applications. This feature hinges on the ability to detect an oscillator fault for the XT1 in both low-frequency and high-frequency modes (XT1LFOFFG and XT1HFOFFG respectively), the high-frequency XT2 (XT2OFFG), and the DCO (DCOFFG). These flags are set and latched when the respective oscillator is enabled but not operating properly; therefore, they must be explicitly cleared in software. First call all clock initialization, then call Clear_All_Osc_Flags(), and finally enable interrupts. Figure 3 shows the oscillator fault logic.
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Figure 3. Latched OFIFG Architecture The oscillator fault flags on previous MSP430 generations are not latched and are asserted only as long as the failing condition exists. Therefore, an important difference between the families is that the fail-safe behavior in a 5xx-based MSP430 remains active until both the OFIFG and the respective fault flag are cleared in software. This fail-safe behavior is implemented at the oscillator level, at the system clock level and, consequently, at the module level. Some notable highlights of this behavior are described below. For the full description of fail-safe behavior and conditions, see the MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208). Low-frequency crystal oscillator 1 (LFXT1) The low-frequency (32768 Hz) crystal oscillator is the default reference clock to the FLL. An asserted XT1LFOFFG switches the FLL reference from the failing LFXT1 to the internal 32-kHz REFO. This can influence the DCO accuracy, because the FLL crystal ppm specification is typically tighter than the REFO accuracy over temperature and voltage of 3%. System Clocks (ACLK, SMCLK, MCLK) A fault on the oscillator that is sourcing a system clock switches the source from the failing oscillator to the DCO oscillator (DCOCLKDIV). This is true for all clock sources except the LFXT1. As previously described, a fault on the LFXT1 switches the source to the REFO. Because ACLK is the active clock in LPM3, there is a notable difference in the LPM3 current consumption when the REFO is the clock source (~3 A active) versus the LFXT1 (~300 nA active). Modules (WDT_A) In watchdog mode, when SMCLK or ACLK fails, the clock source defaults to the VLOCLK. The HAL_UCS.h and HAL_UCS.c library functions show how to properly initialize the XT1 in low-frequency and high-frequency modes, the XT2, and the FLL.
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2.2
Macro Description Selects the source for the reference into the FLL Example: SELECT_FLLREF(SELREF__XT1CLK) Selects the source for ACLK Example: SELECT_ACLK(SELA__XT1CLK) Selects the source for MCLK Example: SELECT_MCLK(SELM__XT2CLK) Selects the source for SMCLK Example: SELECT_SMCLK(SELS__XT2CLK)
(1)
Selects the source for MCLK and SMCLK Example: SELECT_MCLK_SMCLK(SELM__DCOCLK | SELS__DCOCLK) Sets ACLK frequency = ACLK/x; x = {1, 2, 4, 8, 12, 16} Sets MCLK frequency = MCLK/x; x = {1, 2, 4, 8, 12, 16} Sets SMCLK frequency = SMCLK/x; x = {1, 2, 4, 8, 12, 16} Sets the FLL reference frequency = FLLREF/x; x = {1, 2, 4, 8, 12, 16}
All macros mask the required bit changes in the UCS registers so that other clock settings are not affected.
2.2.1
void LFXT_Start(uint16_t xtdrive) Description Initializes the XT1 crystal oscillator to operate in low-frequency mode. This mode supports 32768-Hz crystals. Loops until all oscillator fault flags are cleared, with no timeout, and sets the drive strength to a user-defined level. The maximum drive strength is used to initiate the crystal startup, but then the user level is programmed to the UCS registers. Parameters xtdrive The target drive strength after the oscillator has been successfully initialized. The lowest drive strength is the recommended setting to provide low-power operation and reliable crystal operation. The highest drive strength is recommended when the application environment causes a high degree of risk to the crystal oscillation.
Returns None
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2.2.2
uint16_t LFXT_Start_Timeout(uint16_t xtdrive, uint16_t timeout) Description Initializes the XT1 crystal oscillator to operate in low-frequency mode. This mode supports 32768-Hz crystals. Loops until all oscillator fault flags are cleared or until a timeout counter is decremented and equals to zero. Sets the drive strength to a user-defined level. The maximum drive strength is used to initiate the crystal startup, and then the user level is programmed to the UCS registers. Parameters xtdrive The target drive strength after the oscillator has been successfully initialized. The lowest drive strength is the recommended setting to provide low-power operation and reliable crystal operation. The highest drive strength is recommended when the application environment causes a high degree of risk to the crystal oscillation. A count variable that is decremented every time the loop that clears the oscillator fault flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.
timeout
Returns A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). A UCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.
2.2.3
void XT1_Start(uint16_t xtdrive) Description Initializes the XT1 crystal oscillator to operate in high-frequency mode. This mode supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet for appropriate drive settings. Parameters xtdrive Returns None The target drive strength for the XT1 crystal oscillator.
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2.2.4
uint16_t XT1_Start_Timeout(uint16_t xtdrive, uint16_t timeout) Description Initializes the XT1 crystal oscillator to operate in high-frequency mode. This mode supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared or until a timeout counter is decremented and equals zero. See the device-specific data sheet for appropriate drive settings. Parameters xtdrive timeout The target drive strength for the XT1 crystal oscillator. A count variable that is decremented every time the loop that clears the oscillator fault flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.
Returns A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). A UCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.
2.2.5
void XT1_Bypass(void) Description Initializes the XT1 oscillator to accept an external logic-level input square wave between 4 MHz and 32 MHz in frequency. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet (general purpose I/O) for appropriate logic levels. Parameters None Returns None
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2.2.6
void XT2_Start(uint16_t int xtdrive) Description Initializes the XT2 crystal oscillator, which supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet for appropriate drive settings. Parameters xtdrive Returns None The target drive strength for the XT1 crystal oscillator.
NOTE: When calling XT2_Start() or XT2_Start_Timeout() on a device that does not define XT2DRIVE_x bits, pass zero as the xtdrive parameter.
2.2.7
uint16_t XT2_Start_Timeout(uint16_t xtdrive, uint16_t timeout) Description Initializes the XT2 crystal oscillator, which supports crystal frequencies between 4 MHz and 32 MHz, depending on the selected drive strength. Loops until all oscillator fault flags are cleared or until a timeout counter is decremented and equals zero. See the device-specific data sheet for appropriate drive settings. Parameters xtdrive timeout The target drive strength for the XT2 crystal oscillator. A count variable that is decremented every time the loop that clears the oscillator fault flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.
Returns A status indicator equal to zero (UCS_STATUS_ERROR) or a positive value (UCS_STATUS_OK). A UCS_STATUS_ERROR indicates a timeout has occurred and the crystal is not properly oscillating.
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2.2.8
void XT2_Bypass(void) Description Initializes the XT2 oscillator to accept an external logic-level input square wave between 4 MHz and 32 MHz in frequency. Loops until all oscillator fault flags are cleared, with no timeout. See the device-specific data sheet (general purpose I/O) for appropriate logic levels. Parameters None Returns None
2.2.9
void Init_FLL_Settle(uint16_t int fsystem, uint16_t ratio) Description Initializes the DCO to operate a frequency that is a multiple of the reference frequency into the FLL. Loops until all oscillator fault flags are cleared, with no timeout. If the frequency is greater than 16 MHz, the function sets the MCLK and SMCLK source to the undivided DCO frequency. Otherwise, the function sets the MCLK and SMCLK source to the DCOCLKDIV frequency. Note that the default FLL reference frequency is LFXT1. Therefore, call the LFXT_Start or LFXT_Start_Timeout function before calling Init_FLL to properly initialize and clear the oscillator fault flags of LFXT1. Otherwise, the fail-safe behavior of LFXT1 switches the FLL reference to the internal REFO, which operates at slightly higher current and is slightly less accurate than an external 32-kHz crystal. The FLL reference divider is assumed to be one. For dividers greater than one, the ratio parameter must account for the divider in the factor y (FLL reference frequency). This function executes a software delay that is proportional in length to the ratio of the target FLL frequency and the FLL reference. This allows the FLL an appropriate settling time before any other code is executed. Parameters fsystem ratio Returns None The target frequency for MCLK in kHz The ratio x/y, where x = fsystem and y = FLL reference frequency.
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2.2.10
void XT2_Stop(void) Description Stops the XT2 oscillator using the XT2OFF bit. Parameters None Returns None
2.2.11
void XT1_Stop(void) Description Stops the XT1 oscillator using the XT1OFF bit. Parameters None Returns None
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2.2.12
uint16_t Clear_All_Osc_Flags(uint16_t timeout) Description Clears and checks all oscillator fault flags. It uses a timeout feature and returns the appropriate oscillator fault flag errors. This function should be called after initializing all system clocks. For example:
// Startup LFXT1 32 kHz crystal do{ status = LFXT_Start_Timeout(XT1DRIVE_0, 50000); }while(status == UCS_STATUS_ERROR); // Startup HF XT2 crystal do{ status = XT2_Start_Timeout(XT2DRIVE_3, 50000); }while(status == UCS_STATUS_ERROR); SELECT_ACLK(SELA__XT1CLK); SELECT_SMCLK(SELS__XT2CLK); // Select XT1 as ACLK source // Select XT2 as SMCLK source
See the example API function call in MSP430xxxx_UCS_07.c. Parameters timeout A count variable that is decremented every time the loop that clears the oscillator fault flags is executed. When timeout reaches 0, the loop that checks and clears the oscillator fault flags is exited.
Returns Fault Oscillator fault flags. Software must parse the return value to determine the specific fault flag.
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3 3.1
3.2
3.2.1
Parameters port_mapping PxMAPy num_of_ports port_map_reconfig Returns None Pointer to initialization array Pointer to the first PortMap register to initialize Number of ports to be initialized Flag to enable/disable reconfiguration
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4.1
4.1.1
4.1.2
uint8_t Flash_EraseCheck(uint16_t *Flash_ptr, uint16_t len) Description Erase check of the flash memory. Parameters Flash_ptr len Returns A status indicator equal to 1 (FLASH_ERROR) or 0 (FLASH_OK). A FLASH_ERROR indicates a block of length len starting at address Flash_ptr. Pointer to the starting location of the erase check Number of bytes to be checked
4.1.3
void FlashWrite_8(uint8_t *Data_ptr, uint8_t *Flash_ptr, uint16_t count) Description Write data into the flash memory in byte format. Parameters Data_ptr Flash_ptr count Returns None Pointer to the data to be written Pointer into which to write the data Number of bytes to be written
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4.1.4
void FlashWrite_16(uint16_t *Data_ptr, uint16_t *Flash_ptr, uint16_t count) Description Write data into the flash memory in word format. Parameters Data_ptr Flash_ptr count Returns None Pointer to the data to be written Pointer into which to write the data Number of bytes to be written
4.1.5
void FlashWrite_32(uint32_t *Data_ptr, uint32_t *Flash_ptr, uint16_t count) Description Write data into the flash memory in long format, pass by reference Parameters Data_ptr Flash_ptr count Returns None Pointer to the data to be written Pointer into which to write the data Number of bytes to be written
4.1.6
void FlashMemoryFill_32(uint32_t value, uint32_t *Flash_ptr, uint16_t count) Description Write data into the flash memory in long format, pass by value Parameters Data_ptr Flash_ptr count Returns None Pointer to the data to be written Pointer into which to write the data Number of bytes to be written
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5.1
5.1.1
instance
*length
**data_address
5.1.2
uint16_t Get_Device_Type(void) Description Retrieves the unique device ID from the TLV structure. Parameters None Returns The device ID is returned as type unsigned int.
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5.1.3
uint16_t Get_TLV_Memory(uint8_t instance) Description The Peripheral Descriptor tag is split into two portions a list of the available flash memory blocks followed by a list of available peripherals. This function is used to parse through the first portion and calculate the total flash memory available in a device. The typical usage is to call the Get_TLV_Memory which returns a non-zero value until the entire memory list has been parsed. When a zero is returned, it indicates that all the memory blocks have been counted and the next address holds the beginning of the device peripheral list. Parameters instance In some cases a specific tag may have more than one instance. This variable specifies the instance for which information is to be retrieved (0, 1 etc). When only one instance exists; 0 is passed.
Returns The returned value is zero if the end of the memory list is reached.
5.1.4
uint16_t Get_TLV_Peripheral(uint8_t tag, uint8_t instance) Description The Peripheral Descriptor tag is split into two portions a list of the available flash memory blocks followed by a list of available peripherals. This function is used to parse through the second portion and can be used to check if a specific peripheral is present in a device. The function calls Get_TLV_Memory() recursively until the end of the memory list and consequently the beginning of the peripheral list is reached. Parameters tag This value represents the tag for a specific peripheral for which the information needs to be retrieved. In the header file HAL_TLV.h specific peripheral tags are pre-defined, for example USCIA_B and TA0 are defined as TLV_PID_USCI_AB and TLV_PID_TA2 respectively In some cases a specific tag may have more than one instance. For example a device may have more than a single USCI module, each of which is defined by an instance number 0, 1, 2, etc. When only one instance exists; 0 is passed.
instance
Returns The returned value is zero if the specified tag value (peripheral) is not available in the device.
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5.1.5
uint8_t Get_TLV_Interrupt(uint8_t tag) Description This function is used to retrieve information on available interrupt vectors. It allows the user to check if a specific interrupt vector is defined in a given device. Parameters tag This value represents the tag for the interrupt vector. Interrupt vector tags number from 0 to N depending on the number of available interrupts. Refer to the device datasheet for a list of available interrupts.
Returns The returned value is zero is the specified interrupt vector is not defined.
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Associated Software
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Associated Software
See the accompanying zip file for the software that is associated with this library. The zip file can be downloaded from http://www.ti.com/lit/zip/slaa448. The file structure and a brief description of the included files are provided in the Readme.txt file present in the zip folder, and they are also described here. The associated software is divided into two sections: (A) F5xx_F6xx_Core_Lib: This folder contains all of the librarys source code files. These include the HAL_xxx.c and HAL_xxx.h files for each peripheral PMM, UCS, PMAP, and flash. (B) Application Examples: The application examples call functions from the Core library and show their use based on functionality. The examples are divided based on the device. See the file Index.txt for a list of code examples for each device.
6.1
6.1.1 1. 2. 3. 4. 5. 6.
Using the Library in IAR Create a project in IAR and select the required device specialization under Project Options. The project is created in the same directory level as the folders F5xx_F6xx_Core_Lib and Fxxxx Application Examples. Right click on Project name Add Group and create a group F5xx_F6xx_Core_Lib. Right click on CoreLib and add all files in folder F5xx_6xx_Core_Lib to the group. Add the required example file from the folder Fxxxx Application Examples. Add the include directory path so the Project can find the location of the header file. This is done by Project Options C/C++ Compiler Preprocessor Tab. Insert the line: $PROJ_DIR$\F5xx_F6xx_Core_Lib\ in the blank space provided.
Now the project is ready to compile. 6.1.2 1. 2. Using the Library in CCS Open CCS and select a Workspace or create a new Workspace. Create a new CCS Project (click File New CCS Project). Name the project, choose the appropriate Project Type (MSP430), and choose the device variant that corresponds to the device in use. Right click on Project Name New Folder. Select the Project Name as the parent folder and name the new folder CoreLib. Add all the files in the folder F5xx_6xx_Core_Lib to the Project: Right click on Project Name Add Files (select files). Move the files to the CoreLib folder: Select files and right click Move select 'CoreLib' folder. Add required example file from the folder MSP430xxxx Application Examples: Right click on Project Name Add Files. Double check that the predefined symbol under Project Properties C/C++ Build Predefined Symbols corresponds to the device in use such as "__MSP430F5438A__" in case of an MSP430F5438A. Change the Include directory path so the Project can find the location of the F5xx_F6xx_Core_Lib folder. Click Project Properties C/C++ Build Include Options. Select the icon with the green plus sign and specify the path to the CoreLib folder.
3. 4.
5. 6.
7.
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References
References
1. MSP430x5xx/MSP430x6xx Family Users Voltage Supervisor chapter 2. MSP430x5xx/MSP430x6xx Family Users 3. MSP430x5xx/MSP430x6xx Family Users 4. MSP430x5xx/MSP430x6xx Family Users Guide (SLAU208), Power Management Module and Supply Guide (SLAU208), Unified Clock System (UCS) chapter Guide (SLAU208), Port Mapping Controller chapter Guide (SLAU208), Flash Memory Controller chapter
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