The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON) Nov.

5-8, 2007, Taipei, Taiwan

Real-Time ECG Monitoring System Based on FPGA

Yongming Yang I, Xiaobo Huang 1, Xinghuo Yu 2
The Key Lab. of High Voltage Eng. & Elec. New Technology, Ministry of Education, Elec. Eng. College of Chongqing University, Chongqing 400044, China. Email: gcq medu.cn 2Royal Melbourne Institute of Technology, Melbourne, VIC3001, Australia. u
1

Abstract Existing remote monitoring systems are usually situated in a hospital off line and the cost of sending physiology data by computer is high and the data can only be used within one hospital. In this paper, a real-time Electrocardiogram (ECG) monitoring system is proposed based on Field Programmable Gate Arrays (FPGA). The FPGA chip is taken as the central microprocessor and applies structured design on Very High Speed Integrated Circuit Hardware Description Language (VHDL) to collect and transmit real-time ECG signals. The experiment shows that the ECG monitoring system has a good performance. The digital filtering and data compression arithmetics are also integrated in the FPGA chip. This monitoring system has the advantages of high integration density, powerful function, low cost and convenience to carry around. Index Terms ECG, real-time monitoring, FPGA technology.

I. INTRODUCTION Telemedicine is having a great impact on the monitoring of patients located in remote non-clinical environments such as homes, elder communities, public and so on. Escalating health costs and aging population are placing a significant strain on today's healthcare systems. There is a growing need to reduce the health costs by some method that uses the technologies of telecommunications, computer systems and the apparatus of clinic monitoring to provide the medical information. Due to possible sudden outbreak of some diseases it is of practical importance to extend the physiological parameters monitoring from the bedside in the hospital to the patient's home or public. By remote monitoring, doctors can capture the patient's information remotely and timely to make a diagnosis. ECG transmission has been around for quite some time and it has been particularly useful for pacemaker follow-up and other patient monitoring

applications. Many ECG home monitoring architecture have been presented [1, 2]. Most of them make use of dedicated or PC based monitor devices which result in expensive solutions limiting a widespread diffusion of these applications. The architecture of low-cost home monitoring using a Java-based embedded computer is presented in [3]. The architecture has the advantage of low-cost, but it has the disadvantages of not really portable size and weight and without analyzing function. Field programmable gate arrays (FPGA) are becoming a commonly used technology for digital systems implementation due to their fast manufacturing turnaround time, low startup costs, and ease of design changes. Therefore FPGA are better suited for hardware implementation of real time signal processing [4] - [7]. By taking the characteristic of the ECG signal and the advantages of the FPGA into account, in this paper, the design and development of a remote real-time ECG monitoring system based on FPGA technique is presented. This systems has high integration density, powerful function, low cost and convenience to carry around. The function of each component of the system and the details regarding their implementation will be described in the following sections.

II. SYSTEM STRUCTURE The hardware of monitoring system is based on low-cost Spartan-3 part XC3S400-4TQ144C, including filter and amplifier, QRS-wave detection circuit, FPGA control system and display and alarm circuit. The system structure is shown in Fig. 1. A. Amplifier and Filter The functions of filter and amplifier are to pick up ECG signal from noise and magnify it to an appropriate level

1-4244-0783-4/07/$20.00 C 2007 IEEE

2136

for A/D conversion circuit, consisting of order preliminary difference mode amplifier, high-pass filter, main amplifier, low-pass filter, postamplifier and level translator. We choose AD620 as the preliminary difference mode amplifier to obtain high CMRR in appropriate magnification. The magnification time is 11. The Magnification times of the main amplifier and postamplifier are 50 and 1-3. The whole magnification time is continuously variable

and is applied structured design on VHDL to realize ECG signal sampling, processing, compressing and transmitting real time. III. FPGA SYSTEM Based on the high speed and programmable characteristic of FPGA, we design and compile program modules of data collection, compression, control and host computer communication and so on. There are A/D control module, SRAM control module, FIR filter module, ECG data compression module, clock generating module,

Fig. 1 Real-time monitoring system structure

Fig.2 The inner function graph of the FPGA chip

between 550 and 1650. High-pass filter is designed as simple passive RC filter. We design low-pass filter based on operational amplifier TLC2254. We design and implement 8-stage low-pass filter only in one chip because the chip TLC2254 has four channels. The 8-stage low-pass filter is built by cascade connection of four VCVS low-pass filter to obtain good performance and simple structure. B. A/D Conversion Circuit The distinguishability of digital processing to ECG signal of the system is set as 12 bit. Based on the FPGA chip's plentiful I/0 interfaces, we chose conversion mode as parallel and sampling rate as 1kHz. Because of the system stressing its cubage, low supply voltage and power consumption rather than speed and precision of A/D conversion, MAX1297 with parallel port is taken as A/D converter of the system. Connecting the parallel ports and control signal to FPGA's I/0 interface, conversion clock and pilot signal needed for MAX1297 are provided by FPGA. C. FPGA Circuit The FPGA chip is taken as the central microprocessor

and serial communication module in the FPGA. The inner function graph of the FPGA chip is shown in Fig.2. Top schemes and function simulation of the modules are shown in Fig.3-Fig.8. A. A/D Control Because the A/D conversion chip has dual channel, inside module was designed as dual channel too, which are outdatal and outdata2. The data is 12 bit. CLK is connected to outside clock interface. Interior clock generator was built in system to input 50MHz signal and output 400kHz ad clk signal, duty cycle is 50. Sampling one point per 400 cycles to outdatal and outdata2 for CHO and CHI.Sampling rate is 400kHz/400= kHz. B. Digital Filter For filtering 50Hz noise which is magnified in front end circuit, the distributed FIR digital filter is integrated in the FPGA chip [5]. C. SRAM Control The monitoring system has SRAM with 256KX 16bit, Address Bus with 18-bit, Data Bus with 16-bit. The SRAM's chip select, output enable and write enable signals are CS, OE and WE, which are effectual in low

2137

level. Either the high byte or low byte is written or read is controlled by UB and LB. We design SRAM control module inside the FPGA based on function of the
11.5us
Value: 1 0 0 I 0

chip.The control signals of the module are ram ce, ram-full, ram lb, ram oe, ram ub and ram we. The ram_ce is used to mark the space of the SRAM storage.
16.32us
1.5us

Ref

Jf

Time:

Intetal: 482us
5.Ous 7.5us

--adhdata<3:0> outdatal<11:0>
outdata2<I1 :0>

ad_clk out
ad clk

ad_cs
rd-

Nane: - ad status adclk ad dt ad_rd -e' ad cs ad data ctr J adudata ctr 69 ad hdata

2.5us

lOOus

12.5

7777711770
6 1111 00000 00 t11 00

QL outdatal
.............

ad-status

ad_data

ctr<7 0>

outdata2 d/ wr count

oooo000aC5aoo

1 1 1 1000
000000000000
1f

1111X

D 150

Fig.3 A/D control module top scheme and function simulation

ad_wdata

110>

dsp rdatac11:0>

clk

ad ollk

ram-addr<1 7:0>
dsp_addr<17:0>
ram-ce
ram-full

daGclk C

dsp cik
ram rclk
ram

------------------

ram

rclk

ram-lb

~~~~~~ram_oe
|ramwclk
rst

wclk

ram

ub

dsp_datarin<1 1:0>dsp_addrz17 0>

- dsp_clk
rst

ram -we
ram_data<1 1:0>|

|rst

dsp data out<l 1:0>

txclk

---

Fig.4 SRAM control module top scheme

Fig.5 Data compression module top scheme

Fig.6 Clock module top scheme

Ref

1.3ms

is
Value: 1
O
1

Time: 11 773ms
520 Ous _.

Interval:

27Ous
1.04ms
_-

1 .8ms

Name:
-wrn

rst
din<7:0>
sdo

-clk16x
sdo

1I
1 H 00 H 00
HOD H000
-

cIklCx
rst
wrn

gO din
i91tbr
clkdiv t
t tsr

no
CO

FO
FO
FO EU

00

00
00

00

8O1(

I~~~~~~~~~~~~~~~~~~~~~~~~~\-..t

0 -0

00

Fig.7 The top scheme and function simulation of transmit module

2138

Ref

E I 1.718ms

Time:

1136m
416.fus

Interval: 624 Ous

=412us
832.Qus

1 718n

cikl 6x rst
rxd

douts7:0>

Name: iso rxd rst _ clkl6x

framingerror

Value: I 1 O 0 framing error MO H 00 4D dout HUO 6-e rsr HOO EL rbr

208.Ous

.04ms

1.248ms

1.4ims

644m

1.

3
o

*l

fJ
FO 0O
FF 00

J
00 00

FO

Fig.8 The top scheme and function simulation of receiver module

The ram oe is used to output enable signal to outside SRAM chip. The ram we is used to output R&W control signal. The exterior SRAM chip has 16-bit Data Bus as I/00 -1015. The ram ub and ram-lb are used to control the high and low bytes. There are two clock signals used in this module. One is SRAM write clock: ram wclk, the other is SRAM read clock: ram_rclk. They are all generated by the clock generator. Because the written data of SRAM is switched by the A/D converter previously, so the ram wclk write clock should be consistent with data frequency of A/D converter as 1kHz. The SRAM read signal is for the ECG data compression module, which has 50MHz clock. So we set 50MHz frequency in read for real-time processing furthest. There are two address signals in this module: dsp_addr<17:0> and ram_addr<17:0>. dsp addr<17:0> comes from ECG data compression module. ram_addr<17:0> is used to give address signal to exterior SRAM, thereby data can be written and read in either address. There are three data signals: ad wdata<1 1:0>, dsp_rdata<1 1:0> and ram data<1 1:0>. They are separately connected to anterior A/D conversion module, ECG data compression module and SRAM chip outside the FPGA. D. ECG Data Compression and Transmission For storage and transmitting signal with enough quantity, the ECG signal collected must be compressed. The LADT (Linear Approximation Distance Threshold) data compression arithmetic is integrated in the system. The LADT module for ECG data compression is designed inside the FPGA. There are three input ports which are data input dsp data in<11:0>, system clock dsp_clk and halt signal rst and two output ports which are data output dsp_data out<1 1:0> and address signal send to SRAM: dsp addr<17:0>. Asynchronous communication module built by

communication elements of UART is used to send compressed data to main computer in real time. The frame format of asynchronous communication module is 8 data bit, one start bit and one stop bit. Baud rate is tunable and the clock signal is given by clock generator. In transmission module, din<7:0> is parallel data input, clkl6x is clock signal which is gave by clock generator and tunable. Rst is reset signal (reset signal is 1). Wmn is data transmission control signal (read in trailing edge). Sdo is serial data output. Add start bit and stop bit to data after conversion from parallel to serial then write some other control signals of transmission module. When system receives serial data from the computer, it needs to switch it to parallel data used in FPGA. So the receiving module works in serial-parallel conversion. In this module, clkl6x is clock control signal, rst is reset signal (all work signal reset when rst is 1), rxd is serial data send by serial port, dout<7:0> is parallel data switched by receiving module. Framing error is frame error signal. The main thought of program is putting serial data received in shift register bit by bit, when 8 bits is full, output it to buffer register and keep it provisionally, then output the 8 bits parallel data when transmit signal is received. Actually, it's an inverse process of transmission module. Shift serial data to parallel then write some other

control signals of receiving module.. An intact serial communication should have protocol. It means computer should send a control signal to system, then transmission module starts working. In order to let two modules work together. So we connect the two modules together and add some control signals to build a serial communication module. Rxd is used to receive signal from computer and estimate the signal is AA or 55. AA means start receiving data, 55 means stop. E. Clock Generator Module

2139

The module generates working clocks for all other modules. It is designed based on the requirement in the clock of several modules. The input clock is CLK with 50MHz, which is provided by global clock pin GCLKO of the FPGA connected with external active oscillator. The other output signals are clocks provided for the modules referred upwards. Thereinto, ad clk is for A/D conversion module, da clk is for D/A conversion module, ram rclk and ram wclk are for reading and writing of SRAM module, dsp_clk is for LADT module, rxclk and txclk are for receiving and transmission of UART module.

with integrated hardware and software. It has advantages such as low power consumption, high integrated level, good stability, convenience to carry around and long usage time. The system achieves most real-time monitoring functionalities in one FPGA chip, and can be improved or added with some other modules with software modification. It is more intelligent compared with existing portable ECG monitoring system.

REFERENCES
[1] Y. Mori, M. Yamauchi, K. kaneko, "Design and implementation of the Vital Sign Box for home healthcare," Proc. EEE EMBS Int.Conf. on Inf. Tech. Applications in Biomed., pp.104 -109, 2000. [2] A.I. Hernandez, F. Mora, M. Villegas, G Passariello, G Carrault, "Real-time ECG transmission via Internet for nonclinical applications," EEE Transactions on Information Technology in Biomedicine, vol. 5, no. 3, pp.253 - 257, 2001. [3] F. Lamberti, C. Demartini, "Low-cost home monitoring using a Java-based embedded computer," Proceedings of 4th International EEE EMBS Special Topic Conference on Information Technology Applications in Biomedicine, pp. 342 -345,2003. [4] Spartan-3 FPGA Family: Complete Data Sheet, XILINX Corporation [EB], DS099 March 4, 2004. [5] Jianming Wei, Yongming Yang, Qiaohui Quo, "Design of Real-time ECG signals processing system based on FPGA," Journal of Electron Devices, vol. 28, no. 3, pp. 581-583, 2005. [6] Uwe Meyer-Baese, The Inplement in FPGA of Digital Signal Process. Publish House of Qinghua University, 9 10, Beijng, 2003 [7] Heng Yang, Aiguo Li, Hui Wang. Guard of new applied technology in FPGA/CPLD. Publish House of Qinghua University, Beijing, 2005.

IV. RESULT The programs were downloaded to the FPGA chip to integrate all the modules and implement collection, real-time processing, compression and transmission. The chip used is XC3S400, which has 400K system gates. The application status of resource for final modular program in top layer is shown in Tablel. We can see the utilization percent of resource is low, just 80%. The plentiful leaving resources make consummating the system and adding some other modules possible, such as ECG data analysis module and wireless communication module, etc.
Tablel Device utilization summary Resource name

Occupied
279 143

total number
3584 7168 7168 97 8

proportion
8%

slices slice Flip Flops

2%
4%

4-input lookup tables I/O

GCLK

291
54
1

55%

12%

V. CONCLUSION This article has presented the design and development of a real-time ECG monitoring system based on FPGA with EDA technique. The system integrates the functions of ECG data collection, storage, processing and transmission

2140