Standard Products

UT6325 RadTol Eclipse FPGA

Data Sheeet March 2010 www.aeroflex.com/FPGA

FEATURES 0.25m, five-layer metal, ViaLink epitaxial CMOS process for smallest die sizes One-time programmable, ViaLink technology for personalization Typical performance characteristics -- 120 MHz 16-bit counters, 120 MHz datapaths, 60+ MHz FIFOs 2.5V core supply voltage, 3.3V I/O supply voltage Up to 320,000 system gates (non-volatile) I/Os - Interfaces with 3.3 volt - PCI compliant with 3.3 volt - Full JTAG 1149.1 compliant - Registered I/O cells with individually controlled enables Operational environment; total dose irradiation testing to MIL-STD-883 Test Method 1019 - Total-dose: 300 krad(Si) - SEL Immune: >120MeV-cm2/mg - LETTH (0.25) MeV-cm2/mg: >42 logic cell flip flops >64 for embedded SRAM - Saturated Cross Section (cm2) per bit 5.0E-7 logic cell flip flops 2.0E-7 embedded SRAM Up to 24 dual-port RadTol SRAM modules, organized in user-configurable 2,304 bit blocks - 5ns access times, each port independently accessible - Fast and efficient for FIFO, RAM, and initialized RAM functions 100% routable with full logic cell utilization and 100% user fixed I/O Variable-grain logic cells provide high performance and 100% utilization Typical logic utilization = 65-80% (design dependent)
TM

Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI Packaged in a 208-pin CQFP, 288 CQFP, 484 CCGA, 484 CLGA, 208 PQFP, 280 PBGA, and 484 PBGA Standard Microcircuit Drawing 5962-04229 - QML Q & V

INTRODUCTION The UT6325 RadTol Eclipse Field Programmable Gate Array Family (FPGA) offers up to 320,000 system gates including Dual-Port RadTol SRAM modules. It is fabricated on 0.25m five-layer metal ViaLink CMOS process and contains 1,536 logic cells and 24 dual-port SRAM modules (see Figure 1 Block Diagram). Each SRAM module has 2,304 RAM bits, for a maximum total of 55,300 bits. Please reference product family features chart on page 2. SRAM modules are Dual Port (one asynchronous/synchronous read port, one write port) and can be configured into one of four modes (see Figure 2). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 3). This approach allows a variety of address depths and word widths to be tailored to a specific application. The UT6325 RadTol Eclipse FPGA is available in a 208-pin Cerquad Flatpack, allowing access to 99 bidirectional signal I/ O, 1 dedicated clock, 8 programmable clocks and 16 high drive inputs. Other package options include a 288 CQFP, 484 CCGA and a 484 CLGA. Aeroflex uses QuickLogic Corporations licensed ESP (Embedded Standard Products) technology. QuickLogic is a pioneer in the FPGA semiconductor and software tools field.

UT6325 Product Features

Features Device System Gates 320,640 Logic Cells 1,536 Maximum Logic Flip Flops Cell Flip Flops 4,002 3072 RAM Modules 24 RAM Bits 55,300 I/O Standards Clocks High Drive Inputs 16

UT6325

LVTTL, LVCMOS3, PCI

Operational Environment Device UT6325 Total Dose 3E5 LETTH (0.25) MeV-cm2/mg >42 logic cell flip flops >64 embedded SRAM Saturated Cross Section 5.0E-7 logic cell flip flops 2.0E-7 embedded SRAM Latch-up Immune >120

Bidirectional I/O per Package Device UT6325 208 PQFP 99 208 CQFP 99 280PBGA 163 288 CQFP 163 484 PBGA 310 484 CLGA 316 484 CCGA 316

Embedded RAM Blocks

IP

Maximum of 24 RadTol SRAM Blocks

Fabric

Maximum of 1,536 High Speed Variable Grain Logic Cells

Embedded RAM Blocks

Bidirectional I//O and High-Drive Inputs

Figure 1. UT6325 Eclipse FPGA Block Diagram

PRODUCT DESCRIPTION I/O Pins (9:0) (17:0) WA WD WE WCLK (1:0) MODE RE RCLK RA RD ASYNCRD (9:0) (17:0) Up to 316 bi-directional input/output pins, PCI-compliant for 3.3V buses (see Table 4) Each bidirectional I/O contains RadTol flip-flops for input, output, and output enable lines Distributed Networks One, dedicated clock network, hardwired to each logic cell flip-flop clock pin to minimize skew Three programmable, global clock networks accessible from clock input only pins Figure 2. UT6325 Eclipse FPGA RAM Module Software support for the product is available from both Aeroflex and QuickLogic. The Windows PC-based QuickWorksTM package provides the most complete software solution from design entry to logic synthesis, place and route, simulation, static timing, and power analysis. Device libraries are available to provide support for designers who use Mentor, Synplicity, Synopsys or other third party tools for design entry, synthesis and simulation. Please visit QuickLogics website at www.quicklogic.com for more information. The variable grain logic cell features up to 17 simultaneous inputs and 6 outputs within a cell that can be fragmented into 6 independent sections. Each cell has a fan-in of 30 including register and control lines (see Figure 5). Five programmable quadrant clock networks, accessible from clock pins or internal logic 20 pre-defined Quad-clock networds, five per quadrant. Accessed by the five programmable quadrant clock networks Sixteen high drive inputs. Two inputs located in each of the eight I/O banks. Used as clock or enable signals for the I/O RadTol flip-flops, or as high drive inputs for internal logic Typical Performance Input + logic cell + output total delays under 12ns Data path speeds over 120 MHz Counter speeds over 120 MHz WDATA RAM Module (2,304 bits) RDATA FIFO speeds over 60+ MHz

WADDR

RADDR

RAM Module (2,304 bits) WDATA RDATA

Figure 3. UT6325 Eclipse FPGA Module Bits

+ -

INPUT REGISTER

PAD Q OUTPUT REGISTER D R

E OUTPUT ENABLE REGISTER D

Figure 4. RadTol Eclipse FPGA I/O Cell

QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 PS PP QC DCLK CLKSEL QR GRST

AZ

OZ

S D Q R

QZ

S D Q R

NZ Q2Z FZ

Figure 5. RadTol Eclipse FPGA Logic Cell

Table 1: 208-pin Ceramic Quad Flatpack Pinout Table

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function PLLRST(3) VCCPLL(3) GND GND IO(A) IO(A) IO(A) VCCIO(A) IO(A) IO(A) IOCTRL(A) VCC INREF(A) IOCTRL(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) IO(A) GND IO(A) TDI CLK(0) CLK(1) VCC CLK(2) PLLIN(2) CLK(3) PLLIN(1) VCC CLK(4), DEDCLK PLLIN(0) IO(B) IO(B) GND VCCIO(B) IO(B) Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Function IO(B) IO(B) IO(B) IOCTRL(B) INREF(B) IOCTRL(B) IO(B) IO(B) VCCIO(B) IO(B) VCC IO(B) IO(B) GND TDO PLLOUT(1) GNDPLL(2) GND VCCPLL(2) PLLRST(2) VCC IO(C) GND IO(C) VCCIO(C) IO(C) IO(C) IO(C) IO(C) IO(C) Pin 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function IO(C) VCCIO(C) IO(C) IO(C) GND VCC IO(C) TRSTB VCC IO(D) IO(D) IO(D) GND VCCIO(D) IO(D) VCC IO(D) IO(D) VCC IO(D) IO(D) IOCTRL(D) INREF(D) IOCTRL(D) IO(D) IO(D) IO(D) VCCIO(D) IO(D) IO(D) Pin 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Function VCCPLL(1) IO(E) GND IO(E) IO(E) VCCIO(E) IO(E) VCC IO(E) IO(E) IO(E) IOCTRL(E) INREF(E) IOCTRL(E) IO(E) IO(E) VCCIO(E) GND IO(E) IO(E) IO(E) CLK(5) PLLIN(3) CLK(6) VCC CLK(7) VCC CLK(8) TMS IO(F) IO(F) Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Function IO(F) IO(F) IO(F) IOCTRL(F) INREF(F) VCC IOCTRL(F) IO(F) IO(F) VCCIO(F) IO(F) IO(F) GND IO(F) PLLOUT(3) GNDPLL(0) GND VCCPLL(0) PLLRST(0) GND IO(G) VCCIO(G) IO(G) IO(G) VCC IO(G) IO(G) IO(G) IOCTRL(G) INREF(G) Pin 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 Function IO(G) VCCIO(G) GND IO(G) IO(G) IO(G) VCC TCK VCC IO(H) IO(H) IO(H) GND VCCIO(H) IO(H) IO(H) IOCTRL(H) IO(H) INREF(H) VCC IOCTRL(H) IO(H) IO(H) IO(H) IO(H) IO(H) IO(H) VCCIO(H) GND IO(H)

31 32 33 34 35

66 67 68 69 70

IO(C) IOCTRL(C) INREF(C) IOCTRL(C) IO(C)

101 102 103 104 105

GND PLLOUT(0) GND GNDPLL(1) PLLRST(1)

136 137 138 139 140

IO(F) GND VCCIO(F) IO(F) IO(F)

171 172 173 174 175

IOCTRL(G) IO(G) IO(G) IO(G) VCC

206 207 208

PLLOUT(2)
GND GNDPLL(3)

Table 2: 288-pin Ceramic Quad Flatpack Pinout Table

Pin 1 2 3 4 5 6 7 Function GND VCC PLLRST(1) VCCPLL(1) IO(E) IO(E) IO(E) Pin 36 37 38 39 40 41 42 Function CLK(7) CLK(8) TMS IO(F) IO(F) IO(F) IO(F) Pin 71 72 73 74 75 76 77 Function VCC GND GND VCC GND PLLRST(0) IO(F) Pin 106 107 108 109 110 111 112 Function IO(G) TCK VCC IO(H) IO(H) IO(H) IO(H) Pin 141 142 143 144 145 146 147 Function PLLRST(3) VCCPLL(3) VCC GND GND VCC GND Pin 176 177 178 179 180 181 182 Function IO(A) TDI CLK(0) CLK(1) CLK(2) PLLIN(2) CLK(3) PLLIN(1) CLK(4), DEDCIK, PLLIN(0) IO(B) IO(B) IO(B) IO(B) VCC GND VCCIO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IOCTRL(B) INREF(B) IOCTRL(B) IO(B) IO(B) IO(B) VCCIO(B) GND VCC IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B)

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

IO(E) IO(E) IO(E) IO(E) IO(E) IO(E) VCC GND VCCIO(E) IOCTRL(E) INREF(E) IOCTRL(E) IO(E) IO(E) IO(E) IO(E) IO(E) IO(E) IO(E) IO(E) VCCIO(E) GND VCC IO(E) IO(E) IO(E) CLK(5) PLLIN(3) CLK(6)

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

VCC GND VCCIO(F) IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) INREF(F) IOCTRL(F) IOCTRL(F) IO(F) IO(F) VCCIO(F) GND VCC IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) PLLOUT(3) GNDPLL(0) VCCPLL(0)

78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105

IO(F) IO(F) IO(G) IO(G) IO(G) IO(G) IO(G) IO(G) VCC GND VCCIO(G) IO(G) IOCTRL(G) INREF(G) IOCTRL(G) IO(G) IO(G) IO(G) IO(G) IO(G) IO(G) IO(G) VCCIO(G) GND VCC IO(G) IO(G) IO(G)

113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140

IO(H) IO(H) VCC GND VCCIO(H) IO(H) IO(H) IO(H) IOCTRL(H) IO(H) INREF(H) IOCTRL(H) IO(H) IO(H) IO(H) IO(H) VCCIO(H) GND VCC IO(H) IO(H) IO(H) IO(A) IO(A) IO(A) PLLOUT(2) GND GNDPLL(3)

148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175

IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IOCTRL(A) INREF(A) VCC GND VCCIO(A) IOCTRL(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCCIO(A) GND VCC IO(A)

183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210

Pin 211 212 213 214 215 216 217 218 219 220 221 222 223

Function TDO PLLOUT(1) GNDPLL(2) IO(B) VCC GND GND VCC GND VCCPLL(2) PLLRST(2) IO(B) IO(B)

Pin 224 225 226 227 228 229 230 231 232 233 234 235 236

Function IO(B) IO(C) IO(C) IO(C) IO(C) IO(C) VCC GND VCCIO(C) IO(C) IO(C) IO(C) IO(C)

Pin 237 238 239 240 241 242 243 244 245 246 247 248 249

Function IOCTRL(C) INREF(C) IOCTRL(C) IO(C) IO(C) IO(C) IO(C) VCCIO(C) GND VCC IO(C) IO(C) IO(C)

Pin 250 251 252 253 254 255 256 257 258 259 260 261 262

Function IO(C) IO(C) TRSTB VCC IO(D) IO(D) IO(D) IO(D) IO(D) VCC GND VCCIO(D) IO(D)

Pin 263 264 265 266 267 268 269 270 271 272 273 274 275

Function IO(D) IO(D) IO(D) IO(D) IO(D) IO(D) IO(D) IOCTRL(D) INREF(D) IOCTRL(D) VCCIO(D) GND VCC

Pin 276 277 278 279 280 281 282 283 284 285 286 287 288

Function IO(D) IO(D) IO(D) IO(D) IO(D) IO(E) IO(E) IO(E) PLLOUT(0) GND
GNDPLL(1)

VCC GND

Table 3: 484-pin Ceramic Land Grid Array and Plastic Ball Grid Array Pinout Table
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 Function IO(A) PLLRST(3) IO(A) IO(A) IO(A) IO(H) IO(H) IOCTRL(H) IO(H) NC IO(H) TCK IO(G) IO(G) IO(G) IO(G) IO(G) IO(G) IO(F) GND PLLOUT(3) IO(F) TDO PLLOUT(1) GND IO(B) IO(C) IO(C) IO(C) INREF(C) IO(C) IO(C) IO(C) IO(D) IO(D) Pin AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 Function IO(D) IO(D) IO(D) IO(D) IO(D) IO(E) GNDPLL(1) IO(E) IO(E) IO(B) GNDPLL(2) PLLRST(2) IO(B) IO(B) IO(C) IO(C) IOCTRL(C) IO(C) IO(C) IO(C) IO(D) IO(D) IO(D) IO(D) IOCTRL(D) IO(D) IO(D) IO(E) GND VCCPLL(1) IO(E) IO(A) GND GNDPLL(3) GND Pin B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Function IO(A) IO(H) IO(H) INREF(H) IO(H) IO(H) IO(H) NC NC NC IO(G) IO(G) IO(G) IO(G) PLLRST(0) IO(F) IO(F) IO(F) IO(A) IO(A) VCCPLL(3) PLLOUT(2) IO(A) IO(H) IO(H) IO(H) IOCTRL(H) IO(H) IO(H) IO(H) IO(G) IO(G) IO(G) IO(G) IO(G) Pin C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 Function IO(G) IO(F) GNDPLL(0) IO(F) IO(F) IO(A) IO(A) IO(A) IO(A) IO(A) IO(H) IO(H) IO(H) IO(H) IO(H) IO(H) IO(G) IO(G) IO(G) IOCTRL(G) IO(G) IO(G) IO(F) VCCPLL(0) IO(F) IO(F) IO(F) IOCTRL(A) IO(A) IO(A) IO(A) IO(A) IO(H) IO(A) IO(H) Pin E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 Function IO(H) IO(H) VCC IO(G) IO(G) IO(G) IOCTRL(G) IO(G) INREF(G) IO(G) IO(F) IO(F) IO(F) IO(F) IO(A) INREF(A) IO(A) IO(A) IO(A) VCCIO(A) VCCIO(H) IO(H) VCCIO(H) IO(H) VCCIO(H) VCCIO(G) IO(G) VCCIO(G) NC VCCIO(G) IO(F) IO(F) IO(F) IOCTRL(F) IO(F) Pin F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 Function IOCTRL(F) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) GND IO(H) IO(H) IO(H) IO(G) GND IO(G) IO(G) IO(G) GND VCCIO(F) IO(F) IO(F) IO(F) INREF(F) IO(F) IO(A) IO(A) IO(A) IO(A) IOCTRL(A) VCCIO(A) IO(H) GND VCC VCC VCC GND

10

Pin H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10

Function VCC VCC GND IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) IO(A) VCC GND VCC

Pin K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1

Function IO(A) IO(A) VCCIO(A) IO(A) VCC VCC GND GND GND GND VCC VCC IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) IO(F) CLK4, DEDCLK PLLIN(0) CLK(0) CLK(2) PLLIN(2) IO(A) IO(A) IO(A) GND GND GND GND GND GND GND VCC VCC CLK(6)

Pin L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14

Function VCCIO(F) IO(F) CLK(8) IO(F) IO(F) IO(F) IO(B) IO(B) IO(B) CLK(3) PLLIN(1) IO(B) VCCIO(B) CLK(1) VCC VCC GND GND GND GND GND

Pin N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5

Function VCC VCC GND GND GND GND VCC VCC IO(E) VCCIO(E) IO(E) IO(E) IO(E) IO(E) IO(E) IO(B) IO(B) IO(B) IO(B) IO(B)

Pin P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18

Function IO(E) IO(E) IO(B) INREF(B) IO(B) IO(B) IO(B) IO(B) IO(B) GND VCC VCC GND VCC VCC VCC GND IO(D) VCCIO(E) IO(E)

Pin T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9

Function IO(C) IO(D) IO(E) IO(D) GND IO(E) IO(E) IO(E) IO(E) IOCTRL(E) IO(E) IOCTRL(B) IO(B) IOCTRL(B) IO(B) IO(B) IO(C) VCCIO(C) NC VCCIO(C)

J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3

VCC GND VCC GND VCC IO(F) VCCIO(F) IO(F) IO(F) IO(F) IO(F) IO(F) TDI IO(A) IO(A)

L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16

M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7

GND GND IO(E) IO(E) IO(E) CLK(7) CLK(5) PLLIN(3) TMS IO(B) IO(B) IO(B) IO(B) IO(B) IO(B) IO(B)

P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20

VCCIO(B) IO(B) VCC GND VCC GND VCC VCC GND VCC IO(E) IO(E) IO(E) IO(E) IO(E)

R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

IO(E) IO(E) IO(E) IO(E) IO(B) IO(B) IO(B) IO(B) IO(B) VCCIO(B) GND IO(C) IO(B) TRSTB GND

U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2

IO(C) VCCIO(C) VCCIO(D) IO(D) VCCIO(D) NC VCCIO(D) VCCIO(E) IO(E) IO(E) IOCTRL(E) IO(E) INREF(E) IO(B) IO(B)

11

Pin V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13

Function IO(B) IO(B) IO(B) IO(C) IO(C) IO(C) NC IO(C) IO(C) VCC NC

Pin V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2

Function IO(D) IO(D) INREF(D) IO(D) IO(E) IO(E) IO(E) IO(E) IO(E) IO(B) IO(B)

Pin W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

Function IO(B) IO(B) IO(B) IO(C) NC IO(C) IO(C) IO(C) IO(C) IO(D) IO(D)

Pin W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2

Function IO(D) IO(D) NC IO(D) IO(E) IO(E) IO(E) IO(E) IO(E) IO(B) IO(B)

Pin Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13

Function VCCPLL(2) IO(C) IO(C) IO(C) IO(C) IOCTRL(C) IO(C) IO(C) IO(D) IO(D) IO(D)

Pin Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22

Function IO(D) IOCTRL(D) IO(D) IO(D) IO(E) PLLOUT(0) PLLRST(1) ID(E) IO(E)

12

Table 4: UT6325 Eclipse FPGA Pin Description

PIN TDI/RSI TRSTB/RRO TMS TCK TDO/RCO CLK1 IO(A)

FUNCTION Test data in for JTAG/RAM initialization Serial Data In Active low reset for JTAG/ RAM initialization reset out Test mode select for JTAG Test clock for JTAG Test data out for JTAG/RAM initialization clock out Global clock network driver Input/Output Pin

DESCRIPTION Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. Low skew global clock. This pin provides access to a programmable clock network. The I/O pin is a bi-directional pin, configurable to input and/or output. The A inside the parenthesis means that the I/O is located in Bank A. Low skew global clock. This pin provides access to a dedicated, distributed clock network capable of driving the CLOCK inputs of sequential elements of the device (e.g., RAM and flip-flops). Clock input for PLL.

DEDCLK1

Dedicated clock pin

PLLIN1 VCCPLL1

PLL clock input

Phase locked loop power supply pin

Voltage supply for PLLIN. VCCPLL should be connected to 2.5V supply if the PLLs are used. If the PLLs are not used, VCCPLL can be connected GND. Connect to GND. Reset input for PLL. If PLLs are not used, PLLRST should be connect to the same voltage as VCCPLL (e.g., GND). Dedicated PLL output pin. If PLLs are not used, PLLOUT should be connected to GND.

GNDPLL PLLRST1 PLLOUT2 INREF(A)

Ground pin for PLL Reset input pin for PLL PLL output pin

Differential reference voltage The INREF is the reference voltage pin for GTL+, SSTL2, and STTL3 standards. The A inside the parenthesis means that INREF is located in Bank A. This pin should be tied to GND for LVTTL, LVCMOS3 and PCI inputs. Highdrive input This pin provides fast RESET, SET, CLOCK and ENABLE access to the I/O cell flip flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a high-drive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in Bank A. Connect to 2.5V supply.

IOCTRL(A)1

VCC

Power supply pin

13

Table 4: UT6325 Eclipse FPGA Pin Description

PIN VCCIO(A)

FUNCTION Input voltage tolerance pin

DESCRIPTION Connect to 3.3V supply. The A inside the parenthesis means that VCCIN is located in Bank A. Every I/O pin in Bank A will be tolerance of VCCIO input signals and will output VCCIO level signals. Connect to ground.

GND

Ground pin

Note: Four PLL inputs are available on the RadTol Eclipse FPGA. These PLL pins are noted and available in the QuickWorks/SpDE place and route tools. Aeroflex has tested and characterized the PLL circuits for jitter performance vs frequency and SEE. Aeroflex cautions against the use of the PLL circuits without a full review of the test results. Please contact Aeroflex Colorado Springs directly for support. 1. All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are LVCMOS2 compliant (2.5V). Modifications to the ESD protection networks allow these pins to be driven up to VCCIO +0.3V. Slightly lower noise margins exist for these LVCMOS2 compliant inputs, as compared to the LVCMOS3 compliant bidirectional I/O. 2. All PLLOUT output pins are driven by the VCC rail, not the VCCIO rail. These output pins are LVCMOS2 compliant only (2.5V).

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ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL VCC VCCIO VIO ILU PD JC TJ ESDS II TLS PARAMETER Core supply voltage I/O supply voltage Voltage on any pin Electrical Latchup Immunity Power Dissipation Thermal resistance, junction-to-case2 Maximum junction temperature2 ESD pad protection DC input current Lead Temperature LIMITS -0.5 to 3.6V -0.5 to 4.6V -0.5V to VCCIO +0.5V +/-100mA .5 - 2.5W 6oC/W +150C +/-2000V

10 mA
300C

Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Test per MIL-STD-883; Method 1012.

RECOMMENDED OPERATING CONDITIONS

SYMBOL VCC VCCIO TA K1 tINRISE tINFALL

PARAMETER Core supply voltage I/O Input Tolerance Voltage Ambient Temperature Delay factor for FPGA Maximum input rise or fall time (VIN transitioning between VIL (max) and VIH (min))

LIMITS 2.3 to 2.7V 3.0 to 3.6V -55C to +125C 0.42 to 1.92 (speed grade -4) 20ns

Notes: 1. To conclude best and worst case delays, multiply the K factor from the operating conditions with the delay values defined in the following AC delay tables.

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DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-55C to +125C) (2.3V < VCC < 2.7V) SYMBOL IIN1 IIN2 IIN2 IOZ CI1 CI/O1 IOS2 ICC3 ICC3 ICC3 ICCIO3 ICCIO3 ICCIO3 IREF IPD PARAMETER Input or I/O leakage current, all I/O except TRSTB, TDI, TMS Input leakage current TRSTB, TDI, TMS Input leakage current TRSTB, TDI, TMS post 300 krads(Si) Three-state output leakage current Input capacitance Bi-directional capacitance Short-circuit output current CONDITION VIN = VCCIO or Gnd VIN = VCCIO or Gnd VIN = VCCIO or Gnd VIN= VCCIO or Gnd --VO = GND VO = VCCIO VCC = 2.7V VCC = 2.7V, post 100 krads(Si) VCC = 2.7V, post 300 krads(Si) VCCIO = 3.6V VCCIO = 3.6V, post 100 krads(Si) VCCIO = 3.6V, post 300 krads(Si) -10 VCCIO = 3.6V MIN -2 -20 -50 -10 -15 40 MAX 2 5 50 10 8 12 -180 210 15 5 400 50 0.5 5 10 150 UNIT A A A A pF pF mA mA mA mA mA A mA mA A A

Core quiescent current Core quiescent current Core quiescent current I/O quiescent current I/O quiescent current I/O quiescent current DC supply current on INREF Pad Pull-down (programmable)

Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Capacitance is sample tested for initial qualification or design changes only. Clock pins are 12pF maximum. 2. Input only or I/O. Duration should not exceed 1 second. Measured at initial qualification, or after any design or process change that may affect this parameter. 3. All quiescent current measurements utilize a worst case Standard Evaluation Circuit (SEC) which represents full utilization of synchronous, combinatorial and SRAM logic.

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Table 5: DC Input and Output Levels1

INREF
VMIN VMAX VMIN

VIL VMAX VMIN

VIH VMAX

VOL VMAX

VOH VMIN

IOL

IOH

mA 2.0 2.0 24.0 0.10 1.5

mA -2.0 -2.0 -24.0 -0.10 -0.5

LVTTL LVCMOS2 LVCMOS3 LVCMOS32 PCI

n/a n/a n/a n/a n/a

n/a n/a n/a n/a n/a

-0.3 -0.3 -0.3 -0.3 -0.3

0.8 0.7 0.8 0.8 0.3 x VCCIO

2.0 1.7 2.0 2.0 0.5 x VCCIO

VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3

0.4 0.7 .55 0.20

2.4 1.7 2.0 VCCIO -0.2

VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO

Notes: 1. The data provided in Table 5 are JEDEC and PCI specifications. See preceding AC Delay Data for information specific to Eclipse FPGA I/Os. 2. Low current mode for LVCMOS3 outputs.

Table 6: Max Bidirectional I/O per Device/Package Combination

Device UT6325 Eclipse FPGA

208 CQFP 99

288 CQFP 163

484 CLGA/484 CCGA 316

Notes: 1. Excludes input only signals such as DEDCLK. PROGCLK and IOCTRL.

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AC CHARACTERISTICS LOGIC CELLS (Pre/Post-Radiation)* (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Min TPD TSU THL TCO TCWHI TCWLO TSET TRESET TSW TRW Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup Time: time the synchronous input of the flip flop must be stable before the active clock edge Hold Time: time the synchronous input of the flip flop must be stable after the active clock edge Clock to Out Delay: the amount of time taken by the flip flop to output after the active clock edge Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum that the clock stays low Set Delay: time between when the flip flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal remains high/low Reset Width: time that the RESET signal remains high/low 0.205 0.231 0 0.46 0.46 --0.3 0.3 1.01 --0.43 --0.59 0.66 -Value (ns) Max

Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Stated timing for typical case propagation delay over process variation at VCC=2.5V and TA=25oC. Multiply by the appropriate delay factor, K, for voltage and temperature settings as specified in operating range. 2. These limits are derived from a representative selection of the slowest paths through the logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.

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SET

D Q CLK

RESET Figure 6: Logic Cell Flip Flop

CLK
tCWHI (MIN) tCWLO (MIN)

SET

RESET Q tRESET tRW tSET tSW

Figure 7: Logic Cell Flip Flop Timings - First Waveform

CLK

D tSU D tCO Figure 8: Logic Cell Flip Flop Timings - Second Waveform tHL

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Quad Net

Figure 9: Global Clock Structure

GLOBAL CLOCK TREE DELAY (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Min tPGCK tBGCK Global clock pin delay to quad net Global clock buffer delay (quad net to flip flop) Programmable Clock External Clock Global Clock Clock Select tPGCK tBGCK 0.990 0.534 Value (ns) Max 1.386 1.865

Global Clock Buffer

Figure 10: Global Clock Structure Schematic

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RAM CELL SYNCHRONOUS and ASYNCHRONOUS READ TIMING (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER RAM Cell Synchronous Read Timing tSRA tHRA tSRE tHRE tRCRD RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to RCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to RCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is delivered to RD RAM Cell Asynchronous Read Timing tPDRD RA to RD: time between when the READ ADDRESS is input and when the DATA is output -2.4 0.686 0 0.243 0 -Min ----2.3 Value (ns) Max

RCLK

RA tSRA RE tSRE RD old data tRCRD tPDRD tHRE new data tHRA

Figure 11: RAM Cell Synchronous and Asynchronous Read Timing

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RAM CELL SYNCHRONOUS WRITE TIMING (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Min tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD 0.675 0 0.654 0 0.276 0 -2.8 ----Value (ns) Max

WCLK

WA tSWA WD tSWD tHWD tHWA

WE tSWE RD old data tWCRD Figure 12: RAM Cell Synchronous Write Timing tHWE new data

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tIN - tINI

tICLK

tISU

+ -

tSID Q E D

PAD

Figure 13. Input Register Cell

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INPUT REGISTER CELL (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Min tISU tIHL tICO tIRST tIESU tIEH Input register setup time: time the synchronous input of the pin must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock to out: time taken by the flip-flop to output after the active clock edge Input register reset delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge 3.308 0 --0.830 0 Value (ns) Max 3.526 -0.494 0.464 --

STANDARD INPUT DELAYS (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Min tSID (LVTTL) tSID (LVCMOS3) LVTTL input delay: Low voltage TTL for 3.3V applications 0.34 0.42 Value (ns) Max

LVCMOS3 input delay: Low voltage CMOS for 3.3V applications -

R CLK

tISU

tIHL

tICO tIRST

E tIESU tIEH Figure 14. Input Register Timing

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PAD Q D

Figure 15. Output Register Cell

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OUTPUT REGISTER CELL (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Min tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-state Output Delay low to tri-state Clock to out delay (does not include clock tree delays) ----2.59 2.16 3.06 2.71 3.44 3.32 2.67 (fast skew) 9.0 (slow skew) Value (ns) Max

OUTPUT SLEW RATES (VCC = 2.5V, TA = 25oC, K=1.00, VCCIO = 3.3V) Fast Slew Rising Edge Falling Edge 2.8V/ns 2.86V/ns Slow Slew 1.0V/ns 1.0V/ns

H L tOUTHL

tOUTHL

L H Z tPZL

H Z L tPZH

L H Z L tPHZ

H Z L tPLZ

Figure 16. Output Register Cell Timing

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Power vs Operating Frequency The basic power equation which best models power consumption is shown below. PTOTAL = 0.350 + f(0.0031 NLC + 0.0948 NCKBF +0.01 NCLBF + 0.0263 NCKLD + 0.543 NRAM + 0.0035 NINP + 0.0257 NOUTP) (mW) Where NLC is the total number of logic cells in the design NCKBF = # of clock buffers NCLBF = # of column clock buffers NCKLD = # of loads connected to the column clock buffers NRAM = # of RAM blocks NINP is the number of input pins NOUTP is the number of output pins Figure 17 exhibits the power consumption in the device. The chip was filled with (300) 8-bit counters, approximately 76% logic cell utilization.

Power vs Frequency (Counter_300) 2.5 2 Power (W) 1.5 1 .5 0 0 20 40 60 80 100 120 140

Frequency (Mhz) Figure 17: Power Consumption

27

Power-Up Sequencing

VCCIO

VCC Voltage

tPOR VCCOFFSET

tRVCC

Time

Figure 18. Power-Up Requirements/Recommendations

Notes: 1. VCC and VCCIO should either be ramped simultaneously to their final values (as shown) or with the core voltage VCC leading the I/O voltage VCCIO. 2. Rise time for the voltage supplies (tRVCC) must be within the range of 1s < tRVCC <200ms. 3. Voltage power up/power down ramps for the supplies must be monotonically increasing/decreasing. 4. The starting point for power up (VCCOFFSET) must be less than or equal to 300mV. 5. Users must allow time for the asynchronous power on reset to complete initialization of the device (tPOR). For fast rise times, (tRVCC <10msec) a minimum tPOR =10 msec must be allowed. For slower rise times, 10ms <tRUCE <200ms, a minimum tPOR=tRVCC must be allowed.

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Joint Test Access Group (JTAG)

TCK TMS TRSTB

TAp Controller State Machine (16 States)

Instruction Decode & Control Logic

Instruction Register RDI Mux Boundary-Scan Register (Data Register) Mux TDO

Bypass Register

Internal Register

I/O Registers

User Defined Data Register Figure 19. JTAG Block Diagram

Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not in the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: Extest Instruction: The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAPs Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patters (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. Sample/Preload Instruction: This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed

29

via a data scan operation, allowing users to sample the functional data entering and leaving the device. Bypass Instruction: The Bypass instruction allows data to skip a devices boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.

Table 7: JTAG Pin Descriptions

Pin TDI/RSI

Function

Description

Test Data In for JTAG/RAM init. Serial Data In Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Active low Reset for JTAG/RAM init. reset out Hold LOW during normal operation. Connects to serial PROM data in for RAM initialization. Connect to GND if unused. Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG/RAM init. clock out Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or GND if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization.

TRSTB/RRO

TMS TCK TDO/RCO

Recommended Unused Pin Terminations for the UT6325 Eclipse FPGA Devices All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint ->Fix Placement in the Option pull-down menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in Table 8.

30

Table 8: Recommended Unused Pin Terminations

Signal Name IOCTRL <y> CLK/PLLIN <x> INREF <y> VCCPLL <x> PLLRST <x> PLLOUT <x>

Recommended Termination Any unused pins of this type should be connected to either VCC or GND (recommended: GND). Any unused clock pins should be connected to either VCC or GND (recommended: GND). If an I/O bank does not require the use of an INREF signal, that INREF pin should be connected to GND. If a PLL is not used, the associated VCCPLL must be connected to the same voltage as PLLRST (2.5V or GND; recommend GND). If a PLL is not used, the associated PLLRST must be connected to the same voltage as VCCPLL (2.5V or GND; recommend GND). Unused PLLOUT pins must be connected to either VCC or GND so that the input buffer portion never floats (recommend GND). Utilized PLLs which route the PLL clock outside of the chip require use of the associated PLLOUT pin.

Note: X---> number, Y ---> alphabetical character

31

PACKAGING

1. All exposed metalized areas are gold plated over nickel plating per MIL-PRF-38535. 2. Lead finishes are in accordance with MIL-PRF-38535. 3. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in repaired areas. 4. Letter designations are to cross-reference to MIL-STD-1835.

Figure 20. 208-pin Ceramic FLATPACK

32

Figure 21. 288-pin Ceramic Quad FLATPACK

1. All exposed metalized areas are gold plated over nickel plating per MIL-PRF-38535. 2. App note: Capacitor monitoring pads are dimensioned for a MIL-C-55581 CDR33 chip capacitor. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Letter designations are to cross-reference to MIL-STD-1835. 5. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in repaired area. 6. Seal ring is connected to VSS. 7. Drawing units are in millimeters.

33

1. Seal ring is connected to VSS. 2. Units are in millimeters (inches). 3. All top sides exposed metalized areas must be gold plated 100 to 225 micro-inches thick and all bottom side exposed metalized areas must be gold plated to 60 micro-inches thick nominal. Both sides shall be over electroplated nickel undercoating 100 to 350 micro-inches per MIL-PRF-38535. The bottom side plating is not subject to the salt atmosphere requirements of 40-7150-xx. 4. Camber: 0.08MM max. 5. Geometry is vendor optional. Cannot be alphanumeric and must be isolated within the shaded area. Must be electrically isolated. Plating is optional.

Figure 22. 484-pin Ceramic Column Grid Array

34

1. Seal ring is connected to VSS. 2. Units are in millimeters (inches). 3. All top sides exposed metalized areas must be gold plated 100 to 225 micro-inches thick and all bottom side exposed metalized areas must be gold plated to 60 micro-inches thick nominal. Both sides shall be over electroplated nickel undercoating 100 to 350 micro-inches per MIL-PRF-38535. The bottom side plating is not subject to the salt atmosphere requirements of 40-7150-xx. 4. Camber: 0.08MM max. 5. Geometry is vendor optional. Cannot be alphanumeric and must be isolated within the shaded area. Must be electrically isolated. Plating is optional.

Figure 23. 484-pin Ceramic Land Grid Array

35

1. Units are in millimeters. 2. The top package body size may be smaller than the bottom package body size by as much as 0.20. 3. Body mold protrusion of 0.25 max per side is allowed. 4. Lead finish is tin-lead plated.

Figure 24. 208-pin Plastic Quad Flat Pack

36

1. Units are in millimeters. 2. Dimension measured at maximum solder ball diameter parallel to primary Datum C. 3. Primary Datum C and the seating plane are defined by the spherical crowns of the solder balls.

Figure 25. 280-pin Plastic Ball Grid Array

37

1. Units are in millimeters. 2. Dimension measured at the maximum solder ball diameter parallel to primary datum C. 3. Primary datum C and the seating plane are defined by the spherical crowns of the solder balls.

Figure 26. 484-pin Plastic Ball Grid Array

38

ORDERING INFORMATION UT6325 RadTol Eclipse FPGA:

UT ***** *

*
Lead Finish: (NOTES 1 & 2) (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold, solder, or tinned)

Screening: (NOTES 3 & 4) (C) = HiRel Temperature Range flow (P) = Prototype flow

Packaging: (NOTE 5) (W) = 208-pin PQFP Plastic Quad Flatpack (X) = 208-pin CQFP Ceramic Quad Flatpack (P) = 280-pin PBGA Plastic Ball Grid Array (Y) = 288-pin CQFP Ceramic Quad Flatpack (R) = 484-pin PBGA Plastic Ball Grid Array (Z) = 484-pin CLGA Ceramic Land Grid Array (NOTE 6)

Device Type: (6325) = FPGA

Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an X is specified when ordering, then the part marking will match the lead finish and will be either A (solder) or C (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is FACTORY OPTION "X" only. Radiation neither tested nor guaranteed. 4. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither tested nor guaranteed. 5. Use the following table to determine which lead finishes to select for the corresponding package options. 6. Aeroflex offers COLUMN ATTACHMENT as an additional service for the ceramic land grid array (Case Outline "Z"). If needed, please ask for COLUMN ATTACHMENT when submitting your request for quotation. Package Option (W) 208-PQFP (X) 208-CQFP (P) 280-PBGA (Y) 288-CQFP (R) 484-PBGA (Z) 484-CLGA Associated Lead Finish Option (A) Hot Solder Dipped (C) Gold (A) Hot Solder Dipped (C) Gold (A) Hot Solder Dipped (C) Gold

39

UT6325 FPGA: SMD

5962 - 04229

** * * *
Lead Finish: (C) = Gold

Case Outline: (X) = 208-pin CQFP Ceramic Quad Flatpack (Y) = 288-pin CQFP Ceramic Quad Flatpack (Z) = 484-pin CLGA Ceramic Land Grid Array (NOTE 1)

Class Designator: (Q) = QML Class Q (V) = QML Class V

Device Type (NOTE 2) 01 = UT6325 (Temperature Range: -55oC to +125oC) 02 = No Longer Available. Contact Factory 03 = UT6325 assembled to Aeroflexs Q+ flow Drawing Number: 04229 Total Dose: (NOTE 3) (R) = 1E5 (100 krad)(Si)) (F) = 3E5 (300 krad)(Si)) Federal Stock Class Designator: No options Notes: 1. Aeroflex offers COLUMN ATTACHMENT as an additional service for the ceramic land grid array (Case Outline "Z"). If needed, please ask for COLUMN ATTACHMENT when submitting your request for quotation. 2. Aeroflexs Q+ assembly flow, as defined in section 4.2.2.d of the SMD, provides QML-Q product through that SMD that is manufactured with Aeroflexs standard QML-V flow. 3.Aeroflexs Total dose radiation must be specified when ordering. QML Q not available without radiation hardening.

40

Aeroflex Colorado Springs - Datasheet Definition

Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced HiRel

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Aeroflex Colorado Springs, Inc. reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.

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