Chapter 4, The Microarchitecture Level

4.1 An Example Microarchitecture 4.2 An Example ISA: Ijvm 4.3 An Example Implementation 4.4 Design Of The Microarchitecture Level 4.5 Improving Performance 4.6 Examples Of The Microarchitecture Level 4.7 Summary

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Integer JAVA Virtual Machine

Processor Block Diagram

This is a limited version of a hardware implementation to execute the JAVA programming language.

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Overview THE IJVM hardware architecture follows JAVA language implementation features that result in a very distinct implementation. Once you understand the philosophy of how a JAVA executes, then the implementation hardware becomes more logical. The initial architecture uses multiple clock cycles to execute each JAVA OPCODE instruction. For each instruction, there is a machine fetch to get the instruction followed by a sequence of microinstructions that perform the operation (decode and access operands, execute, and write back the result). The Data Path
PC MBR Program Counter: Access Data in Method Area Memory Branch Register: Instruction and Instruction Parameter 8-bit register Memory Address Register: Address for external data memory space Memory Data Register: Data input and output to external memory Stack Pointer: Address pointer to the top of the system stack Local Variable: Address pointer to the bottom of the local variable frame Constant Pool Pointer: Pointer to the bottom of the constant pool Top Of Stack: The data value at the top of the stack Old PC: A scratch or temporary register typically used for branching and the temporary storage of old PC values in computations Holding: A temporary register for holding one of the two ALU operands

MAR

MDR

SP LV

CPP

TOS OPC

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Data Movement using Registers Loading a Register 1) MAR provide an address to receive data 2) MDR inputs data 3) MDR data is placed on the B bus 4) B Bus Data passed through ALU to the C Bus 5) C Bus Data is written into a register Saving a Register 1) Register data is placed on the B bus 2) B Bus Data passed through ALU to the C Bus 3) C Bus Data is written into the MDR 4) MDR data is written at the MAR memory address Note: The MAR must hold the correct address value Executing a one operand instruction 1) Register data is placed on the B bus 2) B Bus Data is modified by the ALU based on the ALU control and output to the C Bus 3) C Bus Data is written into the appropriate register Executing a two operand instruction 1) Register data is placed on the B bus 2) B Bus Data passed through ALU to the C Bus 3) C Bus Data is written into the H register 4) Register data is placed on the B bus 5) A & B Bus Data is modified by the ALU based on the ALU control 6) C Bus Data is written into the appropriate register

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Arithmetic Logic Units (ALU)

Cascadeable 1-Bit ALU: AND, OR, INV, Binary Added with Cin and Cout Ripple ALU

An 8-bit ALU based on 1-bit ALU building blocks

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Ripple ALU Functions (Your extra homework assignment) Number of possible functions: 5 control bits (2^5) plus a carry bit (x2 for adder functions)

One-operand instructions do not enable the A Bus input: B, NOT(B), B+1, B-1, 0, 1, -1 Two-operand instructions enable both the A and B Bus inputs: A+B, A+B+1, B-A, A AND B, A OR B

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Data Path Timing

Text Book Latch Based Concept Alternate Super-Synchronous Design Timing Cycle

Possible Super-Synchronous Operation w x y z Control signal propagation to the components in the CPU A and B Bus propagation times ALU and Shifter input to output propagation times C Bus propagation time and register set-up time

The subcycles are asynchronous propagation times (if something can complete faster it does, but time is allocated to operate slower or at the worst case timing) The subcycles are implicit in how signals have to flow not explicit clock or gate periods The super-synchronous operation is consistent with our previous mux-register design! 7 of 13 ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Data Path Propagation

w x

x z

Clock rising edge

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Memory Operation (Two ports, one for data and one for instructions)

Data Memory Port MAR Memory Address Register: Address for external data memory space MDR Memory Data Register: Data input and output to external memory 32-bit Registers internal word access and word addressing MAR addressing of 32-bit words using an external Byte wide Memory Addressing Bus

Note: all external data memory is assumed to be perfectly aligned on 4-Byte boundaries.

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Instruction Memory Port

PC MBR

Program Counter: Access Data in Method Area (32-bit register) Memory Branch Register: Instruction and Instruction Parameter (8-bit register) Byte can be read with or without sign extension ( a signed or unsigned integer).

The instructions consist of 8-bit pieces that are addresses by the PC and loaded into the MBR. Reading memories (Cycle latency delays)
CPU CLK

Add Bus

MAR

RD#

Mem Data

Data Bus

MDR

@MAR Available

External Memory Read Latency Notice that the data isnt available during the first cycle. For writing, data can be written on the same cycle as a write command.

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Reading followed by write memories (Cycle latency delays)

CPU CLK

Add Bus

MAR

MAR

RD#

WR#

Mem Data

Data Bus

Data Bus

MDR

@MAR Available

MDR

Read Latency

Write Latency

CPU CLK

Add Bus

MAR1

MAR2

MAR3

MAR4

MAR5

RD#

WR#

can only write what was read

Mem Data

@MAR1

@MAR2

@MAR2

MDR1

@MAR5

MDR

@MAR1

@MAR2

MDR1

@MAR5 Read Latency

Read Latency Read Latency Write Latency Write Latency

MDR1 must be the value @MAR2 or else the read at MAR2 con not be used!

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Microinstructions Now that the functions have been defined, what about the control. Multiple clock cycles execute each instruction, what occurs on each and every clock cycle is defined by a microcontroller with a microPC and a microinstruction! Additional Register Definitions MPC or PC MicroProgram Counter: Internal microcode address register MIR or IR Microinstruction Register: Internal instruction used to control the IJVM

IJVM Block Diagram

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.

Elements of the microinstructions: Operands Execution Results Program Control what is the operand that goes on the B Bus what ALU and shift operation is to occur where are the execution results to be stored from the C Bus and does it involve memory operations where is the next instruction determined

MIR Content

The MIR Fields: B Bus, ALU & Shift, C Bus and Ext. Mem., Next MPC MIR bit width is: 9+3 = 12-bit next instruction with 8+9+3+4 = 24-bits data paths. Total 36-bits!

Encoded B-Bus Selection with a 4:16 Decoder B-Bus Register Selected B-Bus Instruction Field
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MDR PC MBR (signed) MBRU (unsigned) SP LV CPP TOS OPC Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned

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ECE 357

Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.