Puneet Gupta, PMP(R) 1372 Yukon Terrace, Sunnyvale, CA 94087 (408) 829-0275 (cell); pg115c742@westpost.

net CAREER OBJECTIVE To deliver nimble and resilient Supply Chains and robust Technologies that provi de a competitive advantage, through excellence in Program Management and Supply Chain Management LEADERSHIP PROFILE Expert Program Manager and Lean Leader with 16 years in Intel's premier Supply C hain organization delivering substantial results through innovation and persiste nce, a customer and metric focused methodological orientation, fostering collabo rative team and supplier relationships, and questioning everything. Includes * Program/Project Management in multi-year $1MM+ cross-functional, cross-organiz ational, global initiatives in supply chain velocity, test technology, and softw are * Lean implementation in an NPI design and manufacturing operation touching 5 pr oduct divisions, 3 suppliers, and 3 internal groups * Technology Development and High Volume ramp of the wafer level test interface hardware technology ecosystem for Intel's 65nm microprocessor and chipset test p rocess * NPI Design and Operations Management developing and managing design and supply chain capacity, quality, and delivery to meet customer requirements * Sourcing/Supplier Management of fab equipment suppliers to meet Intel's techno logy roadmap and manufacturing requirements for $200M+ in spends * Entrepreneurial experience developing a break-thru fractal based demand analyt ics model, investment management methodology, and product family, and driving bu siness development/marketing PROFESSIONAL EXPERIENCE 10/08 to Current Co-Founder The Absolute Return, LLC * Investors are advised to buy-and-hold financial securities for the long-term p er conventional financial wisdom based on the Efficient Market Hypothesis. Real annualized long-term investment returns however have been above 6% in only 14% of the last 110 years. Observed that the markets (and underlying drivers) are n ot efficient but are structured and can be effectively modeled by a self-similar fractal. Model can be used in demand analytics for supply chain probabilistic forecasting applications. Developed and systematized a proprietary investment m anagement methodology that harnesses this structure to deliver meaningful absolu te returns with less volatility in any market. Co-founded a Registered Investme nt Advisor firm to offer a family of portfolios based on this dynamic trend alig nment methodology to all investors. Intel Corporation, Hillsboro OR and Santa Clara CA 11/04 to 9/08 g Senior Program Manager, Technology and Manufacturing Engineerin

* Long cycle-times for custom Wafer Level Test Interface NPI's were going to lim it the product development cycle for Intel's SoC products like the Atom processo r. A 50% reduction of the 20 week cycle time was required to stay out of the cr itical path while design/manufacturing complexity was increasing by 4X in 18 mon ths. Established the program goals and the cross-division/function/supplier tea m, led the implementation of "Lean" thinking into the NPI Supply Chain and the i ntersection with Intel's product development teams (SoC, Chipset, CPU) through K aizen driven transformation of the 4-party design and 3-supplier manufacturing p rocess, envisioned and projectized break-thru design automation to manage the in crease in design complexity, established program processes in 5 project teams ac

ross three organizations. Delivered results on schedule. * A new Wafer Level Test Interface technology was being developed and qualified for Intel's 65nm test process, which would also give the supplier a >80% share o f the $50M business. A strategic sourcing decision to develop, qualify, and all ocate technology from a 2nd supplier would mitigate both the technology and pric ing risks. However the customer was resource strapped and reluctant to support. Championed the strategy and led the 18+ month program to develop the two techn ology eco-systems and ramp them on Intel's CPU and Chipset high volume test proc esses. Developed and delivered reliable solutions through rapid cycles of relia bility testing, technology improvement, and supply chain quality improvement. B oth the new technology and pricing risks came home to roost during the productio n ramp validating the strategy. 5/00 to 10/04 NPI Operations Manager, Technology and Manufacturing Engineering * Wafer Level Test Interface Hardware (Probe Card) NPI's are a custom, complex, high-speed/high-density electromechanical interface used to electrically test I C's. Intel's response to the Internet crash of 2000 was to invest through the d ownturn in new product development, which resulted in a 25% annual increase in P robe Card NPI's in an environment of flat headcount (HC). At the same time 1/3r d of Probe Card NPI's had design or manufacturing defects that resulted in delay s and irate internal customers. As the NPI Design and Operations Manager * Led the effort to outsource Probe Card Design by defining the strateg y, selecting, qualifying, and ramping design suppliers to match internal metrics , providing a 100% increase in NPI capacity with the existing HC. * Completed a comprehensive FMEA on the NPI design process and drove in itiatives including a 2-year development to re-engineer Probe Card Design, trans forming a manually intensive Netlist based process into an innovative, industry leading, Schematic Controlled Front-to-Back design process using Cadence PCB/Pac kage design tools. Design errors in NPI's dropped to <5%. 7/92 to 5/00 Supply Chain Manager, Technology and Manufacturing Engineering * As the fore-runner in the adoption of 300mm, Intel led the charge with the sem iconductor equipment industry in scaling the technologies without compromising p rocess performance or the 300mm cost advantage. Managed the selection and procu rement of the industry's first 300mm Wafer Level C4 equipment set (including Ele ctroplating, Lithography, Thin Films, Etch, and Metrology equipment) from 6 supp liers for $200M in spends. Defined requirements, evaluated supplier and equipme nt capability against requirements, negotiated deals resulting in $49M in saving s, recommended strategies and decisions to management, and managed schedules and first tool deliveries. * "Burn-In" of Semiconductor Fabrication Equipment is a key methodology used to develop robust tools which meet process, defect, safety, and reliability require ments. An immature methodology and insufficient time resulted in the ramp of In tel's 0.65um technology on an incapable high current ion implanter which quickly limited wafer output from Intel's first high volume factory in a demand constra ined environment. Stretching the traditional role of Technical User Group Chair , galvanized and led a structured cross-functional supplier/Intel response in a 2-year phased effort to rapidly engineer, test, and implement solutions, first r emoving the constraint, and then raising performance substantially to meet requi rements in 3 fabs. EDUCATION / CERTIFICATIONS University of Texas, Austin, TX M. S. in Electrical Engineering Indian Institute of Technology, Madras, India B. S. in Electrical Engineering Project Management Institute Project Management Professional (PMP)

SKILLS SUMMARY * Expert level end-to-end Project and Program Management * Supply Chain Management including Kaizen/Lean, NPI, strategic sourcing, contra ct negotiations * Technology and Supplier Development using DMAIC and Six-Sigma equivalent conce pts * Functional, Operations, and People management * Semiconductor Fabrication, C4 Packaging, Ion Implant, Sort Test, PCB design an d manufacturing, MEMS * Microsoft Project for enterprise level projects, Advanced Microsoft Office * Technical/Financial Analysis of Markets, Sectors, and Companies, Dynamic Portf olio Management SIGNIFICANT AWARDS/PUBLICATIONS * 2 Divisional Recognition Awards for innovations, and 3 published papers and pr esentations at annual Intel Manufacturing Excellence Conferences (conference has acceptance rate of < 20%).